Fast and Accurate Behavioral Simulation of Fractional-N Frequency Synthesizers and other PLL/DLL Circuits

Transcription

1 Fas ad Accurae Behavioral Simulaio of Fracioal-N Frequecy Syhesizers ad oher PLL/LL Circuis Michael H. Perro Microsysems Techology Laboraory, MIT hp://www-ml.mi.edu/ perro ABSTRACT Techiques for fas ad accurae simulaio of fracioal- N syhesizers a a deailed behavioral level are preseed. The echiques allow a uiform ime sep o be used for he simulaor, ad ca be applied o a variey of phase locked loop (PLL) ad delay locked loop (LL) circuis beyod fracioal-n syhesizers, as well as o a variey of simulaio frameworks such as Verilog ad Malab. Simulaed resuls from a cusom C++ simulaor are show o compare well o measured resuls from a prooype fracioal-n syhesizer usig a Σ- modulaor o diher is divide value. Caegories ad Subjec escripors I.6.5 [Simulaio ad Modelig]: Model evelopme Geeral Terms Algorihms Keywords fracioal-n,frequecy,syhesizer,sigma,dela,pll,ll. INTROUCTION Fracioal-N frequecy syhesizers provide high speed frequecy sources ha ca be accuraely se wih very high resoluio, which is of high value o may commuicaio sysems. Figure illusraes a fracioal-n syhesizer, which cosiss of a phase-frequecy deecor (PF), charge pump, loop filer, volage corolled oscillaor (VCO), ad a frequecy divider ha is dihered bewee ieger values o achieve fracioal divide raios. This paper will focus o a class of fracioal-n syhesizers kow as Σ- frequecy syhesizers [2], for which he divide value is dihered accordig o he oupu of a Σ- modulaor [8]. iherig of he divide value by he Σ- modulaor allows high frequecy resoluio o be achieved [2], bu also has he egaive side effec of iroducig quaizaio oise Permissio o make digial or hard copies of all or par of his work for persoal or classroom use is graed wihou fee provided ha copies are o made or disribued for pro or commercial advaage ad ha copies bear his oice ad he full ciaio o he rs page. To copy oherwise, o republish, o pos o servers or o redisribue o liss, requires prior speci c permissio ad/or a fee. AC 22, Jue -4, 22, New Orleas, Louisiaa, USA Copyrigh 22 ACM /2/6...$5.. ha degrades he overall PLL oise performace. I is highly desirable o be able o simulae he effecs of his quaizaio oise, alog wih oher oise sources i he PLL show i Figure 2, o he overall PLL performace. I is also desirable o simulae he dyamic respose of he syhesizer i respose o variaios of he Σ- ipu i order o evaluae sabiliy ad characerize he performace of he sysem whe i is used as a rasmier []. ref() N sd [m] div() PF Σ Modulaor Charge Pump ivider N[m] Loop Filer v() VCO ou() Figure : Σ- syhesizer ad associaed sigals. ref() div() PF Σ uaizaio Noise N sd [m] Σ Charge Pump Noise Charge Pump f f ivider Loop Filer N[m] v() VCO Noise VCO -2 db/dec ou() Figure 2: Specral desiies of PLL oise sources. Simulaio of fracioal-n syhesizers is paricularly challegig for a variey of reasos. Firs, he high oupu frequecy of he syhesizer (ofe i he GHz rage) imposes a high simulaio sample frequecy for radiioal simulaors. Uforuaely, he overall PLL dyamics have a badwidh ha is ypically hree o four orders of magiude lower i frequecy ha he oupu frequecy (ofe khz o MHz badwidh compared o a GHz oupu frequecy). Thus, radiioal simulaors ake a log ime o compue he dyamic respose of he sysem sice may simulaio samples are required. This is he classical problem ha is ecouered wih he simulaio of PLL circuis. For oise f

2 simulaio, he fracioal-n syhesizer adds he addiioal cosrai ha is behavior is o-periodic i seady-sae due o he diherig acio of he divide value, which preves he use of mehods developed for periodic seady-sae codiios [7] as used wih simulaors such as SpecreRF. I coras o he above approaches, wo echiques are preseed i his paper ha allow fas ad accurae simulaio of boh dyamic ad oise performace of fracioal-n syhesizers a a deailed behavioral level. The firs provides accurae represeaio of he coiuous-ime (CT) PF oupu wih a discree-ime (T) sequece usig a area coservaio priciple. The secod allows a dramaic reducio of he simulaio sample frequecy, ad herefore a loger sample period, by icludig he divider implemeaio i he VCO simulaio module. Boh of hese mehods allow a uiform ime sample period o be used, ad also allow o-ieraive compuaio of he sample values of he various sigals wihi he sysem. The uiform ime sample period allows he resuls of he simulaor o be readily examied i he frequecy domai wihou resamplig, ad he o-ieraive compuaio allows he echique o be easily used i maisream simulaors such as Verilog, VHL, Malab, ad cusom C/C++ programs. A oulie of he paper is as follows. Secio 2 provides a overview of he discreizaio echique for represeaio of he CT PF oupu wih a equece, ad preses he correspodig mahemaical aalysis. Secio 3 describes, a a high level, how he discreizaio echique ca be implemeed wih he PF described i erms of basic buildig blocks such as regisers ad logic gaes. Secio 4 focuses o he mehod of dramaically reducig he required simulaio sample rae by combiig he VCO ad divider fucios io oe simulaio block. Secio 5 compares simulaed resuls from a cusom C++ simulaor o measured resuls of a acual circui implemeaio described i []. Fially, Secio 6 cocludes. 2. PF ISCRETIZATION TECHNIUE For simulaio based o uiform ime samplig, a sraighforward approach of coverig he CT PF oupu o a T sequece is o apply he samplig operaio show i Figure 3 [6]. Uforuaely, his approach effecively quaizes he locaio of he PF edges accordig o he simulaio sample period,. A reasoable assessme of he dyamic performace of he PLL ca be achieved if is made sufficiely small. However, he resulig quaizaio oise overpowers he rue oise characerisics of he sigals, ad preves proper oise aalysis of he overall PLL. e[] Sample Period = Figure 3: Classical uiform ime sample mehod. To solve he quaizaio oise issue, eve-drive simulaio mehods have bee developed for classical frequecy syhesizers ha alig simulaio samples precisely o he edges of he PF oupu [2, 5, ]. Alhough higher accuracy ca be achieved wih such mehods, hey are geerally more complicaed ha uiform ime samplig mehods. Eiher closed-form calculaio of he loop filer sep respose mus be developed ad he isered io he simulaio, or ieraive mehods, as used i SPICE or Verilog-A, mus be icorporaed io he simulaor o calculae he loop filer respose wih varyig ime seps. The former approach is edious ad ypically resriced o a low loop filer order, so ha mos of he rece mehods focus o he laer approach [2, 5, ]. I his case, he up-fro work of he desiger is miimized, bu he simulaio ime is ofe loger due o he ieraive calculaios ha are performed a each ime sep. Uforuaely, for eiher case, eve-drive simulaors have o ye bee applied successfully o he oise aalysis of fracioal-n frequecy syhesizers i which he divide value is dyamically varied. I coras o he above approaches, a cosa ime sep mehod is proposed i his paper ha applies a area coservaio priciple whe coverig he CT PF oupu o he T domai. This approach allows o-ieraive compuaio of he loop filer dyamics by allowig hem o be covered from CT o T usig eiher impulse ivariace or biliear rasform mehods [9]. Figure 4 illusraes a example of he resulig T PF sigal, alog wih he correspodig T loop filer impulse respose. The charge pump is igored i his aalysis for simpliciy; is effec ca be icluded by simply scalig he PF oupu by he value of he charge pump curre. I he example, we see ha he T PF oupu akes o values a is rasiios ha vary bewee ad depedig o he locaio of he rasiio edge. The T versio of he loop filer simply cosiss of a T filer whose impulse respose correspods o samples of he CT impulse respose of he loop filer, h(). e[] /2 / h() Loop Filer h[]= h( ) Loop Filer v() v[] v( ) Figure 4: Proposed discreizaio mehod. The discreizaio procedure is ow discussed i more deail. As illusraed by Figure 5, we ca view he CT PF oupu,, as a series of recagular pulses wih heigh of oe or zero ad a widh ad ime offse ha varies accordig o he locaio of PF edges. For recagular pulses o associaed wih edges, he widh correspods o he sample period of he simulaio,. For recagular pulses a edge boudaries, he widh of he pulse varies bewee ad as show i he figure. I eiher case, hese pulses look like impulses o he loop filer so ha, from a iuiive sadpoi, heir ifluece ca be characerized by wo parameers heir area ad ime offse. Therefore, i lie wih his iuiio, he correspodig T PF sigal, e[], is chose as samples ha have ampliude proporioal o he area of he respecive recagular pulse i ha ime sample

3 ierval. The area of each pulse correspods o is associaed imig parameer ɛ show i he figure he mehod of calculaig ɛ for each pulse will be discussed i Secio 4. I will be show ha he proposed discreizaio procedure yields highly accurae resuls, fas compuaio, ad a simple implemeaio framework. e[] area = /2 / area = Figure 5: eails of PF discreizaio echique. To mahemaically jusify he echique, le us begi by specifyig a oaio for he recagular pulses composig ha are show i Figure 5, amely rec(, ɛ k ) = for ɛ k /2 ɛ k /2, elsewhere. We ca describe he loop filer oupu as v() = rec( k k,ɛ k ) h(), () where deoes covoluio, ad k shifs is associaed pulse i ime accordig o he value of ɛ k ad wheher he rasiio edge is risig or fallig. Noe ha ɛ k ad k are cosraied o ɛ k ad < k <. Takig he Fourier Trasform of boh sides of Equaio, we obai V (jw)= e jw(kts+ k) 2si((ɛ k /2)w) H(jw), (2) w where H(jw) is he loop filer frequecy respose. Oe migh be bohered ha he Fourier Trasform is beig ake wih sequeces ha are sochasic i aure, amely ɛ k ad k. Thissepisjusifiedbyoigha hese sequeces will be defied ad fiie i duraio for a specific simulaio ru. However, we cao ifer saisical properies from Equaio 2 or he aalysis ha follows. Equaio 2 ca be simplified i ligh of he followig assumpios: H(jw) is a lowpass filer such ha H(jw) for w >w o, The sample frequecy, /, is much higher ha he badwidh of H(jw), sohaw o. Sice ɛ k <,wehavesi((ɛ k /2)w o) (ɛ k /2)w o. The secod assumpio is well jusified i pracice sice i is ypical for w o /. For isace, he auhor recommeds samplig a a rae ha is greaer ha a facor of above he referece frequecy, which is, i ur, a leas a facor of higher i frequecy ha he loop filer badwidh i Hz, f o, o achieve sable PLL dyamics []. I his case, f o < /, so ha w o < /(2π). Based o he above assumpios, Equaio 2 is approximaed as V (jw) ɛ k e jw(kts+ k) H(jw). The iverse Fourier Trasform of he above expressio is v() = ɛ k h( k k ). (3) We are ow ready o develop he T model of he PF/loop filer ha we are seekig. We begi by samplig Equaio 3: v()= ɛ k h(( k) k ). (4) The above formulaio requires ouiform samplig of h() due o he iclusio of k i is preferable o remove his parameer if i ca be show ha is ifluece is egligible. We will examie his issue usig a specific form for h(), ad he comme o he exesio of he aalysis for more geeral forms of h(). Le us assume ha he loop filer correspods o a lead/lag ework wih rasfer fucio of he form: jw + wz H(jw)=K jw(jw + w. o) Usig he mehod of parial fracios [9], i is sraighforward o show ha he correspodig loop filer impulse respose is of he form h() =K e wo u()+k 2u() =(K e wo + K 2)u(), where u() is he ui sep ( for <, for ), ad K ad K 2 are cosa scale facors. Pluggig he above expressio io Equaio 4, we obai v()= ɛ k (K e wo(( k)ts k) +K 2)u(( k) k ). We oe ha: u(( k) k ) = u(( k)) sice < k <, ad e wo(( k)ts k) = e wo k e wo( k)ts ( + w o k )e wo( k)ts. Therefore, he effec of he ime shif operaio by k has o ifluece o samples of u(), ad oly slighly modulaes he ampliude of samples of he expoeial respose e wo. Alhough is effec could be icorporaed io he umerical model, he auhor has foud ha i ca be safely igored give ha wo codiios are me. The firs codiio is ha w o be much less ha so ha +w o k. This codiio is saisfied i pracice; i was argued earlier i his secio ha we ca ypically expec ha w o /. The secod codiio is ha he sample rae of he simulaor, /, be chose as a ieger muliple of he omial frequecy of he pulses associaed wih he CT PF oupu. The effec of violaig eiher of hese codiios is he (5)

4 iroducio of false spurs i he oupu phase oise of he syhesizer, as will be demosraed i Secio 5. Give ha he above codiios are saisfied, we ca simplify Equaio 5 as v()= ɛ k (K e wo( k)ts + K 2)u(( k)), so ha we have v()= ɛ k h(( k)). (6) Equaio 6 is he coclusio of our effor, ad maches he picure represeaio of he mehod illusraed i Figure 4 whe e[] =ɛ /. Alhough he above aalysis was performed for a simple lead/lag loop filer, higher order filers ca be aalyzed i similar fashio usig he parial fracio expasio mehod. Specifically, high order filers have impulse resposes ha cosis of a sum of expoeials, wih each expoeial correspodig o a disic pole i he loop filer. The impac of e k ad k o each of hese expoeials ca be assessed i he same maer as derived above. 3. IMPLEMENTATION OF PF Now ha i has bee esablished ha he PF oupu sigal ca be accuraely represeed as a equece usig a priciple of area coservaio, le us examie he pracical issue of represeig he PF opology i simulaio code. As revealed by Figure 6, compuaio of e[] for a give PF opology requires ha rasiio iformaio be passed alog ad processed by primiive elemes such as regisers ad logic gaes. Basic operaios such as complemeig sigals mus also be suppored. ref[] div[] R S Figure 6: XOR-based PF. e[] As illusraed i Figure 7, he compleme operaio is easily achieved as a sig chage by slighly modifyig he represeaio of e[k] such ha i aleraes bewee - ad as opposed o ad. The ew represeaio is achieved hrough he rasformaio e[] = 2e[]. The rasfer of rasiio iformaio hrough primiives is illusraed i Figure 8 for a regiser ad a represeaive logic gae, amely he ad gae. I he case of he regiser, he releva imig iformaio is coaied i he clock sigal. Specifically, wheever here is a rasiio a he oupu of he regiser, he locaio of ha rasiio i ime is se by he locaio of he risig (or fallig) edge of he clock. As show i he figure, his iformaio is rasfered o he regiser oupu by simply passig o he clk rasiio value whe he oupu rasiios i he same direcio, ad passig o he compleme of he clk rasiio value whe he - e[] /2 e[] / - 2e[]- -+2/ - / /2-2/ - Figure 7: A beer sigal represeaio. oupu rasiios i he opposie direcio. I he case of he ad gae, eiher ipu ca cause he oupu o rasiio. As gleaed from he figure, i is sraighforward o deermie which ipu is causig he rasiio, ad appropriaely pass is edge locaio value o he oupu of he ad gae. Similar argumes ca be made for more complicaed regisers ha iclude se ad rese fucios, ad oher primiives such as or ad xor gaes. clk clk[] ou[] ou[] ou ou a b a[] b[] ou[] Figure 8: Example of regiser ad logic gae sigals. 4. VCO AN IVIER Simulaio of he VCO ad divider porios of he PLL is ow discussed, ad a echique illusraed whereby he simulaio sample period,,cabeseaccordigohe referece frequecy raher ha he much higher VCO frequecy. This echique ypically allows more ha wo orders of magiude speedup i simulaio ime of he PLL sice he VCO frequecy is ypically more ha wo orders of magiude higher ha he referece frequecy. Ulike a previous mehod ha provided speedup for a PLL wih o divider ad a memoryless phase deecor by modelig he VCO eirely i he phase domai [3], he preseed echique accommodaes fracioal-n syhesizers ha have dividers wih dyamically varyig value ad digial PF opologies as described i he previous secios. The key idea behid he echique is o combie he VCO ad divider io oe compuaio block. To begi, le us defie he phase of he VCO, Φ vco(), as he iegral of is oupu frequecy. Sice he oupu frequecy of he VCO is varied abou is omial frequecy by is ipu volage, we have: Φ vco() = ou 2π(K vv(τ)+f c)dτ +Φ v(), (7) where v() is he VCO ipu volage, K v is he VCO gai (Hz/V), f c correspods o he omial VCO frequecy whe v() =, ad Φ v() is VCO oise as illusraed i Figure 2. To model a oliear relaioship from ipu volage

5 o VCO frequecy, he VCO ipu would be muliplied by a polyomial gai expressio raher ha jus K v. I geeral, Φ vco() looks like a ramp i ime, ad risig edges of he VCO oupu occur each ime i icremes by 2π radias. Simulaio of he VCO is performed by simply discreizig Equaio 7 as Φ vco()= 2π(K vv(k)+f c)+φ v(). (8) To preve loss of iformaio i he CT o T coversio, / mus be higher ha wice he highes frequecy coe of v() adφ v(), as saed by he Nyquis heorem [9]. From a pracical perspecive, his codiio will ofe be saisfied by meeig he samplig requiremes for he PF oupu. Choosig a sample rae such ha w o / is obviously sufficie for v() sice i is he oupu of he loop filer wih badwidh w o rad/s. Φ v() is also badlimied sice i rolls off a -2 db/decade, or more, before eveually hiig a low valued oise floor [3]. Risig edges of he divider oupu occur every N[m] risig edges of he VCO oupu, where N[m] correspods o he isaaeous divide value. Therefore, as illusraed o he lef side of Figure 9, he VCO phase, Φ vco(), compleely specifies he locaio of he divider edges. As such, we ca deermie he value of ɛ k a he rasiio pois of he divider oupu based eirely o compued VCO phase, as show o he righ side of Figure 9 for firs-order ierpolaio [2]. Noe ha he expressios assume ha phase is wrapped every 2πN[m] radias. I suffices o choose a sample rae for he VCO phase compuaio accordig o he divider frequecy, which equals he referece frequecy, raher ha he much higher VCO frequecy. Relaioship of ivider Edges o VCO Phase 2πN[m] 2πN[m-] ivider oupu: div() div[] Φ vco () Φ[k] = Φ vco (k ) Φ[k-] = Φ vco ((k-) ) Calculaio of k div() div[] div() div[] k k 2πN[m]-(Φ[k]+Φ[k-]) k = Φ[k]-Φ[k-] Figure 9: VCO ad divider sigals. Φ[k]+Φ[k-] k = Φ[k]-Φ[k-] 5. RESULTS The resuls of simulaig he dyamic behavior ad oise performace of a prooype syhesizer described i [] usig a cusom C++ simulaor employig he preseed echiques are ow preseed, ad simulaed oise compared o measured resuls. Figure provides a block diagram of he prooype sysem; he reader is referred o [] for more deails. Boh dyamic ad oise simulaios will iclude he oise sources depiced i Figure 2, wih VCO oise beig ipu referred as a whie oise source as described i []. Parameers associaed wih he oise sources are show i Figure, which were compued from Hspice simulaios ad VCO measuremes. ref_clk.ou PF vco.ou (VCO module coais divider) I_chp I_chp 2 i ch,p 2 i ch, S (f) =.85e-25 i ch,p A2 /Hz (from Hspice) S (f) = 3.25e-6 v vco V2 /Hz (from VCO measureme) vco_i Loop Filer S (f) =.2e-24 i ch, A2 /Hz (from Hspice) Figure : Model of charge pump ad VCO oise. Releva characerisics of he prooype iclude a referece frequecy of 2 MHz, a VCO wih f c =.84GHzad K v = 3 MHz/V, a secod order Σ- modulaor, a charge pump ha oupus ±.5 µamps, a omial divide value of 92.3, a PF opology as show i Figure 6 [4], ad a lead/lag filer wih rasfer fucio +jw/(2πf z) H(jw)= C 3jw( + jw/(2πf, p)) where f z =.6kHz, f p = 27.2 khz, C 3 =3e-2. Figure shows he measured syhesizer phase oise of he prooype ake from [], alog wih he measured ope loop VCO oise from which he ipu referred VCO oise variace i Figure was compued. Measured VCO Noise (ope loop) Measured Overall Syhesizer Noise (closed loop) Noise Floor of Measureme Sysem Figure : Measured syhesizer oise. The simulaio sample frequecy was chose as / = 4 MHz, which is a facor of 2 higher ha he referece frequecy. The CT loop filer was covered o T usig he biliear rasform [9]. All simulaios were ru o a 65 MHz Peium III lapop compuer. Begiig wih dyamic behavior, Figure 2 shows he simulaed VCO oupu frequecy (cosruced from he simulaed VCO ipu) i respose o variaios a he ipu of he Σ- modulaor ha iclude sep ad ramp fucios. The sep size is chose o be large eough o kock he syhesizer ou of frequecy lock he correspodig oscillaios i he VCO oupu frequecy are a resul of cycle slippig before he VCO becomes frequecy locked agai. The subseque ramp i divide value illusraes he high resoluio of he syhesizer as is oupu frequecy is varied over a 4 MHz rage. For his simulaio, 26 housad ime seps were compued i less ha 5 secods.

6 N sd VCO Frequecy (MHz) Time (Micro Secods) Figure 2: Simulaed syhesizer dyamics. Noise simulaios of he prooype (cosruced from he simulaed VCO ipu) are show i Figure 3 wih he ipu o he Σ- modulaor beig held cosa. The op plo shows he simulaed oupu oise specral desiy wih he simulaio sample frequecy, /, se o a ieger muliple of he referece frequecy, as recommeded o reduce he effecs of k i Equaio 4. The boom plo shows he impac of choosig / o be a o-ieger muliple of he referece frequecy. We see ha, i boh cases, he simulaed phase oise agrees quie well wih measured resuls. The larger discrepacy a frequecies close o khz is probably due o o-ideal characerisics of he charge pump, such as duy cycle offse ad rasie dyamics, o beig modeled. Such effecs could be icluded wihi he give framework, bu i is useful o observe ha, despie igorig such effecs, he simulaio resuls are sill quie accurae for his prooype. As observed i he boom plo, he impac of choosig / o be a o-ieger muliple of he referece frequecy is ha he referece spur a 2 MHz offse is aliased o oher frequecy values. This aliasig occurs due o he presece of harmoics above 42 MHz of he 2 MHz referece spur i he CT PF oupu. For each simulaio, 5 millio ime seps were compued i 8 secods. 6. CONCLUSION Two echiques were preseed i his paper ha allow fas ad accurae simulaio of fracioal-n syhesizers a a deailed behavioral level usig a uiform ime sample period. The firs provides accurae represeaio of he CT PF oupu wih a equece usig a area coservaio priciple. The secod allows a dramaic reducio of he simulaio sample frequecy by icludig he divider implemeaio i he VCO simulaio module. The echiques were icorporaed io a cusom C++ simulaor, which was used o simulae he dyamic ad oise performace of a prooype Σ- frequecy syhesizer. The simulaed oise performace was show o agree quie well wih measured resuls. The echiques ca also be applied o oher phase locked loop circuis, ad be implemeed i oher simulaio frameworks such as Verilog ad Malab. 7. REFERENCES [] B. e Smed ad G. Giele. Noliear Behavioral Modelig ad Phase Noise Evaluaio i Phase Locked Loops. I CICC, pages 53 56, 998. [2] A. emir, E. Liu, A. L. Sagiovai-Viceelli, ad I. Vassiliou. Behavioral Simulaio Techiques for L(f) (dbc/hz) L(f) (dbc/hz) / = 2*(referece frequecy) -6-7 Simulaed Noise -8 Measured Noise (From Figure ) khz khz MHz MHz 25 MHz -6 / = 2.*(referece frequecy) -7 Simulaed Noise -8 Measured Noise (From Figure ) khz khz MHz MHz 25 MHz Frequecy Offse from Carrier Figure 3: Simulaed syhesizer phase oise. Phase/elay-Locked Sysems. I Cusom Iegraed Circuis Coferece (CICC), pages , 994. [3] A. Hajimiri ad T. Lee. A Geeral Theory of Phase Noise i Elecrical Oscillaors. IEEE Joural of Solid Sae Circuis (JSSC), 33(2):79 94, Feb [4] A. Hill ad A. Surber. The PLL ead Zoe ad How o Avoid I. I RF esig, pages 3 34, Mar [5] M. Hiz, I. Koekamp, ad E.-H. Horeber. Behavioral Modelig ad Simulaio of Phase-locked Loops for RF Fro Eds. I 43rdMidwesSymp.o Circuis ad Sysems, pages 94 97, 2. [6]. Johs ad K. Mari. Aalog Iegraed Circui esig. Wiley, 997. [7] K. Kuder, J. Whie, ad A. Sagiovai-Viceelli. Seady-Sae Mehods for Simulaig Aalog ad Microwave Circuis. Kluwer, Boso, 99. [8] S. Norsworhy, R. Schreier, ad G. Temes. ela-sigma aa Coverers: Theory, esig, ad Simulaio. IEEE Press, New York, 997. [9] A. V. Oppeheim ad R. W. Schafer. iscree Time Sigal Processig. Preice Hall, N.J., 999. [] M. Perro, T. Tewksbury, ad C. Sodii. A 27 mw CMOS Fracioal-N Syhesizer usig igial Compesaio for 2.5 Mb/s GFSK Modulaio. JSSC, 32(2):248 26, ec [] B. Razavi. Moolihic Phase-Locked Loops ad Clock Recovery Circuis: Theory ad esig. IEEE Press, New York, 996. [2] T. A. Riley, M. A. Copelad, ad T. A. Kwasiewski. ela-sigma Modulaio i Fracioal-N Frequecy Syhesis. JSSC, 28(5): , May 993. [3] P. Va Hale ad G. Boyle. SPICE-Compaible Behavioral Phase-Space Simulaio Techiques for Phase-Locked Sysems. I 38h Symposium o Circuis ad Sysems Coferece, volume, pages 53 56, 996.