Implementation of Variable Duty Cycle Ring Oscillator for Unique Identification

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1 Imlemeaio of Variable Duy Cycle Rig Oscillaor for Uique Ideificaio N.Sivasakari (), B.Balambiga () ad P.Idumahi (3) () Assisa Professor, Dearme of Elecroics ad Commuicaio Egieerig Meco Schlek college of Egieerig, Sivakasi-66005, Tamiladu, Idia. () Dearme of Elecroics ad Commuicaio Egieerig, Meco Schlek college of Egieerig, Sivakasi-66005, Tamiladu, Idia. (3) Dearme of Elecroics ad Commuicaio Egieerig, Meco Schlek college of Egieerig, Sivakasi-66005, Tamiladu, Idia. Absrac Differe duy cycle rig oscillaor is reseed i his aer. This aer aims o drive a rig oscillaor wih differe duy cycle wihou he kowledge of exeral ersos, oher ha maufacurer. Firs we roose a deedece of duy cycle variaio by chagig differe widh ad legh raio, ad deedece of variaio of ower suly volage. The simulaio resuls cofirm ha duy cycle of CMOS iverers show he addiioal overhead wih ower suly ad widh o legh raio. This roery ca be used for auheicaig oe erso i he commo orgaizaio who is havig he correc ower suly value ad /L raio. The simulaio resuls usig TANNER EDA for 0.5 μm CMOS shows a good agreeme wih aalysis resuls. I addiio i his aer he mahemaical jusificaio for duy cycle variaio is exlaied. e rese he arameers /L ad suly volage o ideify a erso by roducig differe radom umber. Key words: Asymmeric duy cycle, Rig oscillaor, radom umber geeraio. I. INTRODUCTION Hardware soluios are useful for he recogiio of iegraed circuis, auheicaio geeraio i cryograhic archiecures ad roocols. All hese differe alicaios ake advaage of he caaciy of hardware devices o sore or geerae a oly oe of is kid, secure ad uredicable key i order o avoid hacker aacks or ulicesed use of hardware desigs. Raher ha creaig may sofware s, i is more advaage ad beeficial o imleme a simle hardware wih equivale securiy. Same iu alied o differe rig oscillaors wih differe L raio should resul i uforeseeable resoses wih each oher. This feaure makes he devices suiable for securiy alicaios ad hey have become a mai rimiive i hardware securiy imlemeaios. Firs, heir radomess is assured by he rocess variabiliy. Secodly, hey are low cos as hey do o suose ay overhead o he rocess fabricaio. Ad hirdly, he securiy ad aack resisace are guaraeed because ay couerfei aem resuls i he device fucioaliy desrucio. Rig oscillaors [4] are used i may alicaios such as hase locked loo, radom umber geeraio ec., wih a symmeric duy cycle. Bu his coce is slighly varied i [] o roduce asymmeric duy cycle o geerae radom waveform. The same coce is alied i [] o roduce Physical Ucloable Fucio (PUF) which will roec he circui uder differe emeraures ad eviromeal codiios. I [3] rig oscillaor wih high erformace i erms of avoidace of hase oise is roosed, wih he cos of addiioal MOS rasisor for biasig. The auhors of [5] made aalysis o CMOS rig oscillaor wih hyrisor srucure. The auhors of [6] roose ew soluio based o loo gai of rig ad ew frequecy equaios were described. I his aer we roose II.. Auheicaio of ersos wihou alyig ay addiioal circuiry.. Mahemaical sudy of iverer ad is behaviour as a fucio of ower suly, ier-caaciace ad /L raio. 3. Imlemeaio aalysis of ower suly wih rasie aalysis ad /L raio wih rasie aalysis 4. we ehace he uceraiy of he Rig oscillaor ad we rovide more oeial challeges for he same umber of rig oscillaors. PROPOSED METHOD Coveioal Rig oscillaors measure he ouu frequecy ad hey deermie relaioshis amog hem. Isead of measurig frequecy, we desig a rig oscillaor based o measurig differeces i he duy cycle of differe sigals. e iroduce a mehodology o desig a rig oscillaor wih cofigurable duy cycle, which are o clocks of 50% duy cycle. The whole sysem for alicaio is show i figure. I fids alicaios i auheicaio of cocered orgaizaio users. The users chi secificaio is kow oly o he maufacurer. Durig he issue of chi, he corresodig secificaios for ideificaio (V DD,) are rovided. By agai alyig he same secificaio se (V DD,) he same 75

v=average velociy of carriers, =elecro/hole mobiliy cosa, C ox =caaciace er ui area of gae oxide, =chael widh, V =rasisor hreshold volage, V gs =gae-source volage, V ds =drai source volage.

2 aer is execed o be reeaed. If he user is able o reroduce he aer as secified by he maufacurer, he he is ideified as auhorized user. Accordig o his model, he equaio which is used o rule he source-drai curre of a idividual rasisor is: Qch I ds Cox ( Vgs Vds / ) Vds L / v L ----() here Qch=charge iside he chael, L=chael legh, v=average velociy of carriers, =elecro/hole mobiliy cosa, C ox =caaciace er ui area of gae oxide, =chael widh, V =rasisor hreshold volage, V gs =gae-source volage, V ds =drai source volage. Equaio () is divided io hree differe regios deedig o heir iu volages: Figure : Issue of chi secificaio The chi secificaio is give a he circui maufacure level. I maufacurig, all he circuis have bee imlemeed as CMOS. The secificaio i dimesio of CMOS ad ower suly give o hem are uique for each ad idividual user. The basic eleme i CMOS circuis is iverer. Le us see he desig of iverer i is dimesio level ad how i affecs he erformace o disiguish each ersos. A. CMOS Iverer: As er figure, he comoes rese i CMOS iverer circui are PMOS ad NMOS. 0, Vgs, Off I ds ( Vgs Vds / ) Vds, Vds V, Liear DSAT ( Vgs ), Vds V, Sauraio DSAT () here V DSAT slis ohmic ode from sauraio mode ad C ox / L.The load caaciace should be kow o se he roagaio delay of a iverer. The load caaciace of each iverer is highly iflueced by he gae caaciace of he ex iverer sice he iverers of rig oscillaors are liable i a loo cofiguraio. Thus oher imora arameer o deermie he roagaio delay of CMOS iverers wihi rig oscillaors is heir gae caaciace which is defied as: Cg Cox( ) L (3) e defie he roagaio delay fall ime df as he ime lased o chage a ode volage from V DD o V DD /. VDDC l df ( VDD ) (4) e also defie he roagaio delay rise ime dr as he ime lased o chage a ode volage from 0 o V DD /. here VDDC l dr...(5) ( VDD ) is he resul of relacig by elecro mobiliy.from (4) ad (5) hus we ca coclude ha he roagaio delay fall ad rise deeds o he bias volage of a iverer, he load caaciace ad he rasisor size raio from equaios (4) ad (5) he rise ad fall imes are he fucios of V DD, C l, ad /L raio. d ( VDD, Cl, / L).(6) Figure : CMOS iverer The above equaio (6) imlies ha he roagaio delay for rise ad fall ime is a fucio of facors like bias volage, caaciace, ad widh o legh raio of he CMOS rasisor. By chagig hese arameers, differe resoses ca be obaied. 76

This defiiio remais as: Figure 3: Rig oscillaors wih symmeric dimesio The radiioal rig oscillaor srucure is show i figure 3.Now le us see he deedece of duy cycle wih resec o widh o legh raio.

3 B. Duy cycle as a fucio of /L raio: ( dr df ) d N N( dr df ).(3) dri is he resul of he aggregaio of β,(3) ad(4) ad cosequely is deedecy wih resec o i is: dri i i i.. (4) If we brig β,(3) ad (4)ogeher, he we ca defie dfi for each iverer wih resec o he rasisor widhs i. This defiiio remais as: Figure 3: Rig oscillaors wih symmeric dimesio The radiioal rig oscillaor srucure is show i figure 3.Now le us see he deedece of duy cycle wih resec o widh o legh raio. Usig he develoed equaios i he revious secio we ca sudy he rig oscillaor as he chai of various CMOS iverers. The rig oscillaor eriod T ca be deermied as he addiio of all iverer roagaio delays: T * (7) This work is maily focused o corollig he duy cycle of every sage ouu isead of he ouu frequecy. Thus, he eriod ca be divided io high ad low. high -he ouu is higher ha V DD / ad low he ouu is lower ha V DD /.Therefore (7) is redefied as: di T low high (8) A more secific aalysis of he erms of he rig oscillaor whe hey have combied is give below: N highn drn ( df ) i dr i N lown dfn ( df ) i dr i (9)..(0) The aricularizaio of he deedecy i (6) for he rig oscillaor odes resuls i: i dfi V DDi, Cl( i), Li () The duy cycle of a digial sigal is defied as he raio highi bewee ad is eriod T. di highi T.. () All rig oscillaors desigs make use of iverers ha are exacly he same, he all dri ad dfi are equal ad he duy cycle for each ode N is deermied from (9),(0),() by: i i dfi. i Subsiuig (5) ad (4) i (3),we ge..(5) i i i i i i d N N i i i i i i equaio (4) ca be rewrie as i i dri. (7) i i ad subsiuig he relaio = / ( ) (8) dri similiarly dfi ( ) (9) by subsiuig (8),(9) i (3),we ge, d N ( ) ( ) N ( ) ( ) Furher simlificaio yields, d N Le d N d N ( ) ( ) N ( ) ( ) / N ( ) N ( )..().().(3).(0) (6) 77

Here, he widh ad legh of he CMOS are o chaged ad are se o be i fixed value. The volage is varied from V o he sauraio level of he rasisor.

4 The widh of odd ad eve iverers are varied as er o e e o.thus o e e o By subsiuig he φ relaios i equaios (4) ad (5),we ge dri dfi Subsiuig (4)ad (5) i (3), d N d N N N...(4)...(5) (7) C. Duy cycle as a fucio of ower suly: The secod mehod for obaiig he variable duy cycle is based o chagig he bias volage V DD of each iverer as show i Fig 4. Here, he widh ad legh of he CMOS are o chaged ad are se o be i fixed value. The volage is varied from V o he sauraio level of he rasisor. Duy cycle is varied as er he ower disribuio as show i equaio 8. Pavg Duy cycle.. (8) Peak D. Duy cycle as a fucio of caaciace: As er equaio 6, oe of facor affecig he duy cycle is caaciace. Bu wih he chai of iverers, roagaio delay is o a fucio of ier-ode caaciace. Subsiuig (4) ad (5) i equaio(3),we ge, By simlifyig, d N V DD VDD V DD V VDD V N d N (3) N..(3) Figure 4: Various bias volages alied o each iverer From he equaio 3, he duy cycle does o deed o ierode caaciace. The rig oscillaor ca be laced verically as give i figure 5, o roduce uique waveform for ideificaio. The order ad φ values are differe for each user. I is show i figure III. Figure 5: User chi circui RESULTS AND DISCUSSION The exerimes are coduced wih differe suly volages. I each oscillaor 8 iverers have bee coeced, he volages a differe odes have bee ake ad he eak volage amog hem is calculaed. Value of ϕ is ses as 3. The variaio i duy cycle, calculaed as er equaio (8) is show i able. Table : Bias volage Vs Duy cycle Average volage Peak volage Bias volage Duy cycle The ier ode caaciace value is measured, ad he variaios i duy cycle wih resec o caaciace is ake ad abulaed i able. Table : Caaciace Vs Duy cycle V DD (V) Caaciace T high (s) Toal Period(s) Duy Cycle f f f f f f f f f

5 From he able, i is observed ha duy cycle is o a fucio of caaciace. I is slighly varied wih resec o bias volage. φ value is fixed as 3 for all he measuremes i able. The value of φ is chaged by keeig V DD cosa, ad duy cycle is measured. Table 3: /L(φ) raio Vs Duy cycle φ T high (s) Toal Period(s) Duy Cycle From able 3, i is iferred ha duy cycle is highly varied wih resec o widh o legh raio φ, comared o bias volage ad caaciace deedece. Hece more radom waveforms wih differe duy cycle ca be geeraed by chagig he value of φ. I our exerime, i is assumed ha 64 users are erolled. Hece 64 imes rig oscillaor is isaiaed wih differe φ value, wih he deh of 8.They are combied wih XOR gae o roduce he uique required waveform. From he aalysis of able, ad 3 we se φ=7,v DD =5V.The radom waveforms are show i figure 6,7 ad 8. Figure 6: Duy cycle for /L =7 Figure 7: Duy cycle for /L =5 IV. CONCLUSION Figure 8: Duy cycle for /L =0 I his aer, he imlemeaio of variable duy cycle rig oscillaor chi is roosed by wo mehods. Duy cycle variaio is doe by rasisor sizig ad bias volage.the idea used i his aer, for rasisor sizig is,v aryig he widh o legh raio(asec raio)of NMOS ad PMOS rasisor is uilized o roduce radom waveforms for ideificaio. I rasisor sizig,he legh of he PMOS ad NMOS are ke as same whereas he widh is chaged so ha he curre varyig arameers wo affec he erformace more. REFERENCES []. Javier Agusi ad Marisa Loez-Vallejo, A I- Deh Aalysis Of Rig Oscillaors:Exoliig Their Cofigurable Duy Cycle,IEEE Tras.Circuis ad Sysems,Vol.6,No.0,Oc.05 []. Javier Agusi ad Marisa Loez- Vallejo, A Temeraure-Ideede PUF wih a Cofigurable duy cycle of CMOS Rig Oscillaors,IEEE,06. [3]. Yusuf Jameh Bozorg ad Mohammad Jafar Taghizadeh Marvas, Desigig a New Rig Oscillaor For High Performace Alicaios I 65m CMOS Techology Idia Joural of Fudameal ad Alied Life Scieces, Vol. 4 (S4), ,04. [4]. V. Sikarwar, N. Yadav ad S. Akashe, "Desig ad aalysis of CMOS rig oscillaor usig 45 m echology," 03 3rd IEEE Ieraioal Advace Comuig Coferece (IACC), Ghaziabad, 03, doi: 0.09/IAdCC [5]. Balaji Ramakrisha S, Shivaada Yali, Nihi Kumar L, Ravidra H.B, Chaia Ram, Desig ad Performace Aalysis of Low Frequecy CMOS Rig Oscillaor usig 90m Techology, IEEE Ieraioal Coferece,May 0-,06. [6]. P.M.Farahabadi, H.Miar-Naimi ad A.Ebrahimzadeh, A New soluio o aalysis of CMOS Rig Oscillaors, Iraia Joural, Vol. 5, No., March

Analysis of Current Starved Voltage Controlled Oscillator using 45nm CMOS Technology

Analysis of Current Starved Voltage Controlled Oscillator using 45nm CMOS Technology SSN (Pri) : 30 3765 SSN (Olie): 78 8875 eraioal Joural of Advaced Research i Elecrical, Elecroics ad srumeaio Egieerig (A SO 397: 007 erified Orgaizaio) ol. 3, ssue 3, March 014 Aalysis of urre Sarved