PONTIFICIA UNIVERSIDAD CATÓLICA DEL PERÚ

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1 PONTIFICIA UNIVERSIDAD CATÓLICA DEL PERÚ FACULTAD DE CIENCIAS E INGENIERÍA DISEÑO DE UN SISTEMA ELECTRÓNICO PARA LOS MOVIMIENTOS DE UN CAÑÓN ANTIAÉREO A ESCALA ANEXOS Tesis para optar el Título de Ingeniero Electrónico, que presenta el alumno: Don Henoel Quispe Chafloque ASESOR: Miguel Ángel Cataño Sanchez Lima, Agosto del 2009

2 SLRS008C SEPTEMBER 986 REVISED NOVEMBER 2004 Featuring Unitrode L293 and L293D Products Now From Texas Instruments Wide Supply-Voltage Range: 4.5 V to 36 V Separate Input-Logic Supply Internal ESD Protection Thermal Shutdown High-Noise-Immunity Inputs Functionally Similar to SGS L293 and SGS L293D Output Current A Per Channel (600 ma for L293D) Peak Output Current 2 A Per Channel (.2 A for L293D) Output Clamp Diodes for Inductive Transient Suppression (L293D) description/ordering information The L293 and L293D are quadruple high-current half-h drivers. The L293 is designed to provide bidirectional drive currents of up to A at voltages from 4.5 V to 36 V. The L293D is designed to provide bidirectional drive currents of up to 600-mA at voltages from 4.5 V to 36 V. Both devices are designed to drive inductive loads such as relays, solenoids, dc and bipolar stepping motors, as well as other high-current/high-voltage loads in positive-supply applications. HEAT SINK AND GROUND HEAT SINK AND GROUND L N OR NE PACKAGE L293D... NE PACKAGE (TOP VIEW),2EN A Y 2Y 2A V CC V CC 4A 4Y 3Y 3A 3,4EN L DWP PACKAGE (TOP VIEW),2EN A Y NC NC NC NC NC 2Y 2A V CC V CC 4A 4Y NC NC NC NC NC 3Y 3A 3,4EN HEAT SINK AND GROUND HEAT SINK AND GROUND All inputs are TTL compatible. Each output is a complete totem-pole drive circuit, with a Darlington transistor sink and a pseudo- Darlington source. Drivers are enabled in pairs, with drivers and 2 enabled by,2en and drivers 3 and 4 enabled by 3,4EN. When an enable input is high, the associated drivers are enabled, and their outputs are active and in phase with their inputs. When the enable input is low, those drivers are disabled, and their outputs are off and in the high-impedance state. With the proper data inputs, each pair of drivers forms a full-h (or bridge) reversible drive suitable for solenoid or motor applications. TA PACKAGE ORDERING INFORMATION ORDERABLE PART NUMBER TOP-SIDE MARKING 0 C to 70 C HSOP (DWP) Tube of 20 L293DWP L293DWP PDIP (N) Tube of 25 L293N L293N PDIP (NE) Tube of 25 L293NE L293NE Tube of 25 L293DNE L293DNE Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS SLRS008C SEPTEMBER 986 REVISED NOVEMBER 2004 schematics of inputs and outputs (L293D) EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC2 Current Source Input Output GND GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note ) V Output supply voltage, V CC V Input voltage, V I V Output voltage range, V O V to V CC2 + 3 V Peak output current, I O (nonrepetitive, t 5 ms): L ±2 A Peak output current, I O (nonrepetitive, t 0 µs): L293D ±.2 A Continuous output current, I O : L ± A Continuous output current, I O : L293D ±600 ma Package thermal impedance, θ JA (see Notes 2 and 3): DWP package TBD C/W N package C/W NE package TBD C/W Maximum junction temperature, T J C Storage temperature range, T stg C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values are with respect to the network ground terminal. 2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/ JA. Operating at the absolute maximum TJ of 50 C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD POST OFFICE BOX DALLAS, TEXAS 75265

3 SLRS008C SEPTEMBER 986 REVISED NOVEMBER 2004 recommended operating conditions Supply voltage VIH High-level input voltage MIN MAX UNIT VCC V VCC2 VCC 36 VCC 7 V 2.3 VCC V VCC 7 V V VIL Low-level output voltage V TA Operating free-air temperature 0 70 C The algebraic convention, in which the least positive (most negative) designated minimum, is used in this data sheet for logic voltage levels. electrical characteristics, V CC = 5 V, V CC2 = 24 V, T A = 25 C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage L293: IOH = A L293D: IOH = 0.6 A VCC2.8 VCC2.4 V VOL Low-level output voltage L293: IOL = A L293D: IOL = 0.6 A.2.8 V VOKH High-level output clamp voltage L293D: IOK = 0.6 A VCC2 +.3 V VOKL Low-level output clamp voltage L293D: IOK = 0.6 A.3 V IIH High-level input current IIL Low-level input current A EN A EN VI = 7 V VI = All outputs at high level 3 22 µa A µa A ICC Logic supply current IO = 0 All outputs at low level ma All outputs at high impedance 8 24 All outputs at high level 4 24 ICC2 Output supply current IO = 0 All outputs at low level 2 6 ma All outputs at high impedance 2 4 switching characteristics, V CC = 5 V, V CC2 = 24 V, T A = 25 C PARAMETER TEST CONDITIONS L293NE, L293DNE MIN TYP MAX tplh Propagation delay time, low-to-high-level output from A input 800 ns tphl Propagation delay time, high-to-low-level output from A input ttlh Transition time, low-to-high-level output CL = 30 pf, See Figure UNIT 400 ns 300 ns tthl Transition time, high-to-low-level output 300 ns switching characteristics, V CC = 5 V, V CC2 = 24 V, T A = 25 C PARAMETER TEST CONDITIONS L293DWP, L293N L293DN UNIT MIN TYP MAX tplh Propagation delay time, low-to-high-level output from A input 750 ns tphl Propagation delay time, high-to-low-level output from A input ttlh Transition time, low-to-high-level output CL = 30 pf, See Figure 200 ns 0 ns tthl Transition time, high-to-low-level output 350 ns 5 POST OFFICE BOX DALLAS, TEXAS SLRS008C SEPTEMBER 986 REVISED NOVEMBER 2004 APPLICATION INFORMATION VCC2 SES500 M SES500 M2 8 3A 4A 5 4 /2 L VCC EN EN 3A M 4A M2 H H Fast motor stop H Run H L Run L Fast motor stop L X Free-running motor stop L = low, H = high, X = don t care X Free-running motor stop GND 4, 5, 2, 3 Figure 4. DC Motor Controls (connections to ground and to supply voltage) VCC2 2 SES500 M 2 SES500 2A A /2 L293 4, 5, 2, 3 GND VCC EN Figure 5. Bidirectional DC Motor Control EN A 2A FUNCTION H L H Turn right H H L Turn left H L L Fast motor stop H H H Fast motor stop L X X Fast motor stop L = low, H = high, X = don t care POST OFFICE BOX DALLAS, TEXAS

4 .OPERATINGSUPPLY VOLTAGE UP TO 46 V.TOTALDCCURRENTUPTO4A.LOW SATURATION VOLTAGE.OVERTEMPERATURE PROTECTION.LOGICAL 0 INPUTVOLTAGEUP TO.5 V (HIGH NOISE IMMUNITY) DESCRIPTION The L298 is an integratedmonolithic circuit in a 5- lead Multiwatt and PowerSO20 packages. It is a high voltage, high current dual full-bridge driver designedto acceptstandardttllogiclevelsanddrive inductive loads such as relays, solenoids, DC and steppingmotors. Two enableinputsare providedto enableordisablethe deviceindependentlyof theinput signals. The emitters of the lower transistors of each bridge are connected togetherand the correspondingexternalterminal can be used for thecon- BLOCK DIAGRAM Jenuary 2000 L298 DUAL FULL-BRIDGE DRIVER Multiwatt5 PowerSO20 ORDERING NUMBERS : L298N (Multiwatt Vert.) L298HN (Multiwatt Horiz.) L298P (PowerSO20) nectionofanexternalsensingresistor.anadditional supplyinputisprovidedsothatthelogicworksata lower voltage. /3 L298 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VS Power Supply 50 V VSS Logic Supply Voltage 7 V VI,Ven Input and Enable Voltage 0.3 to 7 V IO Peak Output Current(each Channel) NonRepetitive(t=0µs) Repetitive(80%on 20%off;ton=ms) DC Operation A A A Vsens Sensing Voltage to 2.3 V Ptot Total Power Dissipation(Tcase = 75 C) 25 W Top Junction Operating Temperature 25 to 30 C Tstg, Tj Storage and JunctionTemperature 40 to 50 C PIN CONNECTIONS(top view) 5 CURRENT SENSING B 4 OUTPUT 4 3 OUTPUT 3 2 INPUT 4 ENABLEB INPUT 3 9 LOGICSUPPLYVOLTAGEV SS Multiwatt5 8 GND 7 INPUT 2 6 ENABLEA 5 INPUT 4 SUPPLYVOLTAGEV S 3 OUTPUT 2 2 OUTPUT CURRENT SENSING A TABCONNECTEDTOPIN8 D95IN240A GND 20 GND Sense A N.C. Out Out PowerSO Sense B N.C. Out4 Out3 V S 6 Input Input 4 Enable B Enable A 8 3 Input 3 Input VSS GND GND D95IN239 THERMAL DATA Symbol Parameter PowerSO20 Multiwatt5 Unit Rth j-case Thermal Resistance Junction-case Max. 3 C/W Rth j-amb Thermal Resistance Junction-ambient Max. 3(*) 35 C/W (*) Mounted on aluminumsubstrate 2/3

5 L298 PIN FUNCTIONS(referto the block diagram) MW.5 PowerSO Name Function ;5 2;9 Sense A; Sense B Between this pin and ground is connected the sense resistor to control the current of the load. 2;3 4;5 Out;Out2 OutputsoftheBridgeA;thecurrentthatflowsthroughtheload connected between these two pins is monitored at pin. 4 6 VS Supply Voltage for the Power Output Stages. A non-inductive 0nF capacitor must be connected between this pin and ground. 5;7 7;9 Input; Input 2 TTL Compatible Inputs of the Bridge A. 6; 8;4 Enable A; EnableB TTL Compatible Enable Input: the L state disables the bridge A (enablea)and/orthebridgeb(enableb). 8,,,20 GND Ground. 9 2 VSS Supply Voltage for the Logic Blocks. A0nF capacitor must be connected between this pin and ground. ; 2 3;5 Input3; Input 4 TTL Compatible Inputs of the Bridge B. 3;4 6;7 Out3;Out4 OutputsoftheBridgeB.Thecurrentthatflowsthroughtheload connected between these two pins is monitored at pin 5. 3;8 N.C. Not Connected ELECTRICAL CHARACTERISTICS(VS = 42V; VSS = 5V, Tj = 25 C; unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit VS Supply Voltage(pin 4) Operative Condition VIH V VSS Logic SupplyVoltage(pin 9) V IS QuiescentSupplyCurrent(pin4) Ven=H; IL=0 Vi=L Vi=H ISS QuiescentCurrentfromVSS(pin9) Ven=H; IL=0 Vi=L Vi=H ViL Input Low Voltage (pins5,7,,2) ViH Input High Voltage (pins5,7,,2) IiL Low Voltage Input Current (pins5,7,,2) IiH High Voltage Input Current (pins5,7,,2) Ven=L Vi=X 4 ma Ven=L Vi=X 6 ma ma ma ma ma V 2.3 VSS V Vi=L µa Vi=H VSS 0.6V 30 0 µa Ven=L EnableLowVoltage(pins6,) V Ven=H EnableHighVoltage(pins6,) 2.3 VSS V Ien=L LowVoltageEnableCurrent (pins6,) Ien=H HighVoltageEnableCurrent (pins6,) VCEsat(H) Source Saturation Voltage IL = A IL=2A VCEsat(L) Sink Saturation Voltage IL = A (5) IL=2A (5) VCEsat TotalDrop IL = A (5) IL=2A (5) Ven=L µa Ven=H VSS 0.6V 30 0 µa V V V V V V Vsens Sensing Voltage(pins, 5) () 2 V 3/3

6 DME34 DIMENSIONS Unit mm(inch) MODEL CODE VOLTAGE OUTPUT CURRENT SA 2V.3W 0.2A SB 24V.3W 0.A BA 2V 4.5W 0.65A BB 24V 4.5W 0.3A KB 24V 7W 0.4A Model L Weight g lb DME34SA DME34SB DME34BA DME34BB DME34KB CONNECTION RED (+) CW ( ) BLACK CURRENT, SPEED-TORQUE CURVE DME34SA, DME34SB DME34BA, DME34BB CURRENT (A) : 2V CURRENT (A) : 24V SPEED r / min OZ In CURRENT SPEED gf cm 0 TORQUE 25 50mN m STANDARD SPECIFICATIONS CURRENT (A) : 2V CURRENT (A) : 24V Rated No load Stall torque Model Output Voltage Torque Current Speed Current Speed mn-m W V mn-m oz in A r/min A r/min oz in DME34SA DME34SB DME34BA DME34BB DME34KB REVOLUTION SENSOR MAGNET TYPE SPEED r / min OZ In CURRENT SPEED CURRENT (A) : 24V gf cm TORQUE mn m DME34KB SPEED r / min OZ In SPEED CURRENT gf cm TORQUE 50 0 mn-m Model L Weight g lb DME34SMA DME34SMB DME34BMA DME34BMB DME34KMB

7 Compact DC Motors Japan Servo s DC Miniature Motors are widely used in a variety of application fields, from copiers and other office equipment, to remote-controlled equipment, medical equipment, vending machines, and game machines. These motors may be combined with Japan Servo s full line of gearheads to meet a wide range of torque and output speed specifications. Japan Servo provides a practical and economic choice as drive actuators. Strict quality control ensure reliable performance as well as prompt delivery at reasonable price. Japan Servo provides a full variation line-up of stock model and customized design motors to best meet your specific application needs. DC SMALL MOTORS DME Series The DME Series motor is a feasible and practical DC motor that is used popularly in many applications. According to user demands, Japan Servo combines the DME motor with a wide variation of high-performance gearboxes to further increase the application possibilities for the DME Series. Also, in response to demands for a simple, low-cost motor that has a certain amount of controllability, Japan Servo provides DME models that feature pulse generators (magnetic or optical PG). For certain models of the DME Series, the motor and gearboxes can be ordered separately, allowing for much greater versatility by combining various type motors with a wide range of reduction gears. Please refer to the product line-up chart to select the DME Series motor that is just right for your specific needs. DME SERIES MOTOR S CONSTRUCTION AND CHARACTERISTICS. LIFE* OUTPUT POWER (W) MODEL BRUSH HOLDING CORE SLOTS BEARING MAGNET PAGE (hrs) S B K 5 5 DME 25 Holder 3 slots Sintered sleeve bearing Anisotropic 00 K 6 3 Isotropic DME 33 Spring plate 3 slots Sintered sleeve bearing Anisotropic K S K S3 DME 34 Spring plate 3 slots Sintered sleeve bearing Isotropic 00 Anisotropic (500) K K K S.3 S 4.5 S7 5 K S 4.6 DME 37 Holder 7 slots Sintered sleeve bearing Anisotropic K S7.2 K S 9.2 DME 44 Holder slots Ball bearing Anisotropic K S 4.8 DME 60 Holder 2 slots Sint. sleeve/ball bearing Isotropic Anisotropic K S K 26S BRUSH HOLDER BEARING MAGNET Holder:Long-life 2000hours Ball bearing :Long-life Anisotropic :High output FEATURE (00 hours only for DME25, due to its high-speed operation) Spring plate:standard 00hours Sintered sleeve bearing :Standard Isotropic :Standard *Operated in motor alone, and single direction.

8 DME Motors with pulse generators: There are two types of pulse generators that are featured in DME series motors : the magnetic and optical revolution sensor. (Note, the optical revolution sensor is available only in the DME34 model.) Both are incremental revolution sensor. And all the above generators can output Single Phase pulse signal only. When TWO Phase signal is required, contact our sales agent near you or directly to us. We may quote on case by case basis. STANDARD SPECIFICATION OF REVOLUTION SENSOR REVOLUTION SENSOR TYPE MAGNETIC OPTICAL PULSE PER REVOLUTION 2P/rev. 24P/rev. INPUT VOLTAGE DC5V±% DC5V±% CURRENT CONSUMPTION 5mAnominal 25mAnominal DUTY (B/A) 50±20% 50±% OUTPUT WAVEFORM (COMMON) DC5V (GND) A B Magnetic Type Optical Type Magnetic Revolution Sensor : Compared to the optical revolution sensor, the magnetic revolution sensor is more resistant to high temperatures, dust contaminations, vibrations and impact shocks. The design of the magnetic revolution sensor type motor is also more simple. In incremental type revolution sensor, pulse output signals are sent to a counter wherein the incremented value is displayed. Signal noise, here, lead to performance errors. Magnetic type revolution sensors are especially vulnerable to signal noise since the signal levels are usually very low (20mA to 30mA). Thus, make sure magnetic revolution sensor type motors are provided proper magnetic shielding, and signal lines are as short as possible (ideally within 5m). Optical Revolution Sensor: Long-life LED is used as the light emitter, and a phototransistor is used as the light detector. When using optical revolution sensor type motors, special considerations are needed to protect against dust and extreme temperatures. The most frequent causes of trouble in optical revolution sensors are : dust build-ups impairing proper optical properties ; and extreme leading to deterioration in light emission performance. Japan Servo can thus ensure full rated performance only in ambient temperatures between 0 to 40 degrees centigrade, and in dust-free conditions. CONNECTION ( + ) RED YELLOW OUTPUT CW M PG BLUE GND ORANGE INPUT ( ) 5[V] BLACK Handling Precautions: DME Series DC SMALL Motors Handling Precautions DME Series DC motors are compact, high-performance and high-output motors that allow for versatile speed control, and that can be operated with battery or other relatively small power supplies. Practical as they are in countless applications, certain basic precautions are necessary in order to avoid abnormal brush wear and hazardous heat damages. Overloading and locking : Even when operated at the rated voltage, if the motor is overloaded or locked, excessive torque builds up, increasing the current that flows to the motor and causing burn ups. Brush wear caused by power supply ripples : Brush wear is caused either by mechanical abrasion between the brush and the commutator, or by electrical sparks from the commutator. Most of the brush wear is the latter, electrical type, which increases with power supply ripple. It is thus recommended that stable, DC power be used, as possible. However, when using rectified from an AC power supply, make sure that the ripples are minimized with filter or other means. Ambient condition : The DC motor s lifetime depends greatly on the condition of the commutator. Dirt, grease or moisture on the commutator surface impairs normal performance, and in turn, increases brush wear. Operations exceeding rated speeds : When voltages in excess of the rated value is applied, the motor operates at speed exceeding its rated limit. This can cause : heat damages to the shaft ; direct damages to the brush ; or vibrations causing sparks that damage the commutator surface, which in turn leads to mechanical wear on the brush. Gear heads for intermittent drive : This is not suitable for continuous drive. Because the torque is conveyed from fixed shaft to planet gear pieces around the shaft. The duty cycle must be 50% or less. And set ON time at 5 seconds or shorter. (Ex.) Run Stop Designed brush position : When the motor is manufactured, the brush is carefully positioned in relation to the magnet polarity, so that the speed and current are equal in both clockwise and counter-clockwise direction revolutions. Make sure that components such as the brush holder and rear cover are not moved their fixed positions. Changes in the brush magnet position causes electrical performance changes in the forward and reverse direction. Such changes can also impair proper commutations, which in turn lead to unnecessary brush wear. Motor installation position : The motor is designed to be installed, used in shaft horizontal position. To use the motor in the vertical position, special considerations are needed in the bearing and washer designs. Contact Japan Servo, our sales agents or our representatives for details. Supply voltage : Please make sure that the motor is used within the rated supply voltage, and avoid surge voltages. Upon special order, the motor can also be manufactured with built-in protection circuitry against surges and reverse polarity. Contact Japan Servo, our sales agents or our representatives for details. JAPAN SERVO CO.,LTD. International Sales Department 7 Kanda Mitoshiro-cho, Chiyoda-ku, Tokyo JAPAN Phone : Fax : Time a b 0=50% (This is to apply 36G, 43G, 5C and L ) 5 4 a b

9 PC87 Series PC87 Series.. Features. Current transfer ratio 2. High isolation voltage between input and : 5 000V rms ) 3. Compact dual-in-line package High Density Mounting Type Photocoupler Lead forming type ( I type ) and taping reel type ( P type ) are also available. (PC87I/PC87P ) TUV ( VDE0884 ) approved type is also available as an option. ( CTR: MIN. 50% at I F = 5mA,VCE=5V) Applications. Computer terminals 2. System appliances, measuring instruments 3. Registers, copiers, automatic vending output ( Viso machines 4. Electric home appliances, such as fan heaters, etc. PC87 : -channel type PC827 : 2-channel type PC837 : 3-channel type PC847 : 4-channel type 4. Recognized by UL, file No. E Signal transmission between circuits of different potentials and impedances Outline Dimensions ( Unit : mm) PC ± 0.25 PC827 Internal connection diagram Internal connection diagram 2.54 ± PC837 Internal connection diagram θ θ PC847 Internal connection diagram PC87 PC87 PC87 Anode mark PC87 PC87 PC87 PC87 Anode mark PC87 PC87 PC87 CTR rank mark Anode mark ± ± ± 0.5 θ θ = 0 to 3 θ Anode 2 Cathode 3 Emitter 4 Collector Anode mark θ θ θ= 0 to 3 3 Anode 2 4 Cathode 5 7 Emitter 6 8 Collector 3.0 ± ± ± ± ± TYP ± ± ± ± ± ± ± ± ± TYP. 3.0 ± ± ± ± Anode Cathode 7 9 Emitter 8 2 Collector θ = 0 to ± Anode Cathode θ θ θ = 0 to Emitter Collector ± ± ± ± ± TYP. 3.5 ± ± ± ± ± ± ± ± ± ± TYP. 3.5 ± ± ± ± ± In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that occur in equipment using any of SHARP's devices, shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest version of the device specification sheets before using any SHARP's device. PC87 Series Absolute Maximum Ratings Input Output ( Ta= 25 C) Parameter Symbol Rating Unit Forward current IF 50 ma * Peak forward current I FM A Reverse voltage V R 6 V Power dissipation P 70 mw Collector-emitter voltage V CEO 35 V Emitter-collector voltage V ECO 6 V Collector current IC 50 ma Collector power dissipation P C 50 mw Total power dissipation P tot 200 mw *2 Isolation voltage V iso Operating temperature T opr - 30 to + 0 C Storage temperature T stg - 55 to + 25 C *3 Soldering temperature T sol 260 C V rms * Pulse width <=0µs, Duty ratio : 0.00 *2 40 to 60% RH, AC for minute *3 For seconds Electro-optical Characteristics Input *4 Classification table of current transfer ratio is shown below. Model No. CTR ( % ) PC87A PC87B PC87C PC87D Rank mark A B C D A or B B or C C or D A, B or C B, C or D A, B, C or D A, B, C, D or No mark 80 to to to to to to to to to to to 600 Fig. Forward Current vs. Ambient Temperature Ambient temperature Ta ( C) ( Ta= 25 C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Forward voltage V F IF = 20mA V Peak forward voltage V FM IFM = 0.5A V Reverse current IR VR = 4V - - µ A Terminal capacitance Ct V = 0, f = khz pf Output Collector dark current ICEO V CE = 20V A Transfer characteristics *4 Current transfer ratio CTR IF = 5mA, V CE = 5V % Collector-emitter saturation voltage V CE(sat) IF = 20mA, I C= ma V Isolation resistance R ISO DC500V, 40 to 60% RH 5 x - Ω Floating capacitance Cf V = 0, f = MHz pf Cut-off frequency fc V CE = 5V, I C = 2mA, R L = 0 Ω, - 3dB khz Response time Rise time t r Fall time tf V CE = 2V, I C = 2mA, R L = 0 Ω µ s µ s Forward current I F ( ma ) PC8 7AB PC8 7BC PC8 7CD PC8 7AC PC8 7BD PC8 7AD PC8 7 : or 2 or 3 or 4

10 KA78XX/KA78XXA 3-Terminal A Positive Voltage Regulator Features Output Current up to A Output Voltages of 5, 6, 8, 9,, 2, 5, 8, 24V Thermal Overload Protection Short Circuit Protection Output Transistor Safe Operating Area Protection Description The KA78XX/KA78XXA series of three-terminal positive regulator are available in the TO-220/D-PAK package and with several fixed output voltages, making them useful in a wide range of applications. Each type employs internal current limiting, thermal shut down and safe operating area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltages and currents. TO-220 D-PAK. Input 2. GND 3. Output Internal Block Digram Rev Fairchild Semiconductor Corporation KA78XX/KA78XXA Absolute Maximum Ratings Parameter Symbol Value Unit Input Voltage (for VO = 5V to 8V) (for VO = 24V) Thermal Resistance Junction-Cases (TO-220) RθJC 5 Thermal Resistance Junction-Air (TO-220) RθJA 65 C/W Operating Temperature Range (KA78XX/A/R) TOPR 0 ~ +25 C Storage Temperature Range TSTG -65 ~ +50 C VI VI V V C/W Electrical Characteristics (KA7805/KA7805R) (Refer to test circuit,0 C < TJ < 25 C, IO = 500mA, VI =V, CI= 0.33µF, CO=0.µF, unless otherwise specified) Parameter Symbol Conditions Output Voltage VO KA7805 Min. Typ. Max. TJ =+25 o C mA Io.0A, PO 5W VI = 7V to 20V Unit V Line Regulation (Note) Regline TJ=+25 o C Load Regulation (Note) Regload TJ=+25 o C VO = 7V to 25V mv VI = 8V to 2V IO = 5.0mA to.5a mv IO =250mA to 750mA Quiescent Current IQ TJ =+25 o C ma Quiescent Current Change IQ IO = 5mA to.0a VI= 7V to 25V Output Voltage Drift VO/ T IO= 5mA mv/ o C Output Noise Voltage VN f = Hz to 0KHz, TA=+25 o C µv/vo Ripple Rejection RR f = 20Hz VO = 8V to 8V ma db Dropout Voltage VDrop IO = A, TJ =+25 o C V Output Resistance ro f = KHz mω Short Circuit Current ISC VI = 35V, TA =+25 o C ma Peak Current IPK TJ =+25 o C A Note:. Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken into account separately. Pulse testing with low duty is used. 2

11 Typical Applications Input Output Figure 5. DC Parameters Input Output Figure 6. Load Regulation Input Output Figure 7. Ripple Rejection Input Output Figure 8. Fixed Output Regulator KA78XX/KA78XXA 2

12 WITH GEARBOX 36G DME34B36G Gear heads for intermittent drive GEAR RATIO L L2 WEIGHT (mm) (inch) (mm) (inch) g lb ~ ~ ~ ~ DME34K36G GEAR RATIO L L2 WEIGHT (mm) (inch) (mm) (inch) g lb ~ ~ ~ ~ with 36G TYPE GEARBOX Model Gear ratio *8 * *20 *50 *80 Rated speed r/min DME34S36GM Rated torque N m oz in Rated speed r/min DME34B36GM Rated torque N m oz in Rated speed r/min DME34K36GMB Rated torque N m oz in Model Gear ratio *200 *250 * Rated speed r/min DME34S36GM Rated torque N m oz in Rated speed r/min DME34B36GM Rated torque N m oz in Rated speed r/min DME34K36GMB Rated torque N m oz in NOTES : On models marked with asterrisks ( ), the direction of the gearbox shaft rotation is in reverse of the motor rorarion direction. 2: In notation model number : fill the reduction ratio denominator in the position marked with the box sign M ; fill the voltage in the position marked with the star sign. 7

13 Features High-performance, Low-power AVR 8-bit Microcontroller Advanced RISC Architecture 30 Powerful Instructions Most Single-clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 6 MIPS Throughput at 6 MHz On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories 8K Bytes of In-System Self-Programmable Flash Endurance:,000 Write/Erase Cycles Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation 52 Bytes EEPROM Endurance: 0,000 Write/Erase Cycles K Byte Internal SRAM Programming Lock for Software Security Peripheral Features Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode One 6-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Three PWM Channels 8-channel ADC in TQFP and QFN/MLF package Eight Channels -bit Accuracy 6-channel ADC in PDIP package Eight Channels -bit Accuracy Byte-oriented Two-wire Serial Interface Programmable Serial USART Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages 23 Programmable I/O Lines 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF Operating Voltages V (ATmega8L) V (ATmega8) Speed Grades 0-8 MHz (ATmega8L) 0-6 MHz (ATmega8) Power Consumption at 4 Mhz, 3V, 25 C Active: 3.6 ma Idle Mode:.0 ma Power-down Mode: 0.5 µa 8-bit with 8K Bytes In-System Programmable Flash ATmega8 ATmega8L 2486P AVR 02/06 Pin Configurations 2 ATmega8(L) PDIP (RESET) PC6 28 PC5 (ADC5/SCL) (RXD) PD PC4 (ADC4/SDA) (TXD) PD 3 26 PC3 (ADC3) (INT0) PD PC2 (ADC2) (INT) PD PC (ADC) (XCK/T0) PD PC0 (ADC0) VCC 7 22 GND GND 8 2 AREF (XTAL/TOSC) PB AVCC (XTAL2/TOSC2) PB7 9 PB5 (SCK) (T) PD5 8 PB4 (MISO) (AIN0) PD6 2 7 PB3 (MOSI/OC2) (AIN) PD7 3 6 PB2 (SS/OCB) (ICP) PB0 4 5 PB (OCA) TQFP Top View (INT) PD3 24 PC (ADC) (XCK/T0) PD PC0 (ADC0) GND 3 22 ADC7 VCC 4 2 GND GND 5 20 AREF VCC 6 9 ADC6 (XTAL/TOSC) PB6 7 8 AVCC (XTAL2/TOSC2) PB7 8 7 PB5 (SCK) 2486P AVR 02/ (T) PD5 (AIN0) PD6 (AIN) PD7 (ICP) PB0 (OCA) PB (SS/OCB) PB2 (MOSI/OC2) PB3 (MISO) PB PD2 (INT0) PD (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) MLF Top View (INT) PD3 24 PC (ADC) (XCK/T0) PD PC0 (ADC0) GND 3 22 ADC7 VCC 4 2 GND GND 5 20 AREF VCC 6 9 ADC6 (XTAL/TOSC) PB6 7 8 AVCC (XTAL2/TOSC2) PB7 8 7 PB5 (SCK) (T) PD5 (AIN0) PD6 (AIN) PD7 (ICP) PB0 (OCA) PB (SS/OCB) PB2 (MOSI/OC2) PB3 (MISO) PB4 PD2 (INT0) PD (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) NOTE: The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB.

14 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega8 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 52 bytes of EEPROM, K byte of SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with -bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel s high density non-volatile memory technology. The Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self- Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega8 AVR is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 4 ATmega8(L) 2486P AVR 02/06 General Purpose Register File 2 ATmega8(L) The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Bit 0 C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: One 8-bit output operand and one 8-bit result input. Two 8-bit output operands and one 8-bit result input. Two 8-bit output operands and one 6-bit result input. One 6-bit output operand and one 6-bit result input. Figure 3 shows the structure of the 32 general purpose working registers in the CPU. Figure 3. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R 0x0 R2 0x02 R3 0x0D General R4 0x0E Purpose R5 0x0F Working R6 0x Registers R7 0x R26 0xA X-register Low Byte R27 0xB X-register High Byte R28 0xC Y-register Low Byte R29 0xD Y-register High Byte R30 0xE Z-register Low Byte R3 0xF Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 3, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file. 2486P AVR 02/06

15 6-bit Timer/Counter Register Description Timer/Counter Control Register A TCCRA 2486P AVR 02/06 ATmega8(L) Figure 44. Timer/Counter Timing Diagram, with Prescaler (f clk_i/o /8) clk I/O clk Tn (clk I/O /8) TCNTn (CTC and FPWM) TOP - TOP BOTTOM BOTTOM + TCNTn (PC and PFC PWM) TOP - TOP TOP - TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Bit COMA COMA0 COMB COMB0 FOCA FOCB WGM WGM TCCRA Read/Write R/W R/W R/W R/W W W R/W R/W Initial Value Bit 7:6 COMA:0: Compare Output Mode for channel A Bit 5:4 COMB:0: Compare Output Mode for channel B The COMA:0 and COMB:0 control the Output Compare Pins (OCA and OCB respectively) behavior. If one or both of the COMA:0 bits are written to one, the OCA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMB:0 bit are written to one, the OCB output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OCA or OCB pin must be set in order to enable the output driver. When the OCA or OCB is connected to the pin, the function of the COMx:0 bits is dependent of the WGM3:0 bits setting. Table 36 shows the COMx:0 bit functionality when the WGM3:0 bits are set to a normal or a CTC mode (non-pwm). Table 36. Compare Output Mode, Non-PWM COMA/ COMB COMA0/ COMB0 Description 0 0 Normal port operation, OCA/OCB disconnected. 0 Toggle OCA/OCB on Compare Match 0 Clear OCA/OCB on Compare Match (Set output to low level) Set OCA/OCB on Compare Match (Set output to high level) 97 Timer/Counter Control Register B TCCRB 0 ATmega8(L) Bit ICNC ICES WGM3 WGM2 CS2 CS CS TCCRB Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value Bit 7 ICNC: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture Pin (ICP) is filtered. The filter function requires four successive equal valued samples of the ICP pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. Bit 6 ICES: Input Capture Edge Select This bit selects which edge on the Input Capture Pin (ICP) that is used to trigger a capture event. When the ICES bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES setting, the counter value is copied into the Input Capture Register (ICR). The event will also set the Input Capture Flag (ICF), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR is used as TOP value (see description of the WGM3:0 bits located in the TCCRA and the TCCRB Register), the ICP is disconnected and consequently the Input Capture function is disabled. Bit 5 Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRB is written. Bit 4:3 WGM3:2: Waveform Generation Mode See TCCRA Register description. Bit 2:0 CS2:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 4 and Figure 42. Table 40. Clock Select Bit Description CS2 CS CS Description No clock source. (Timer/Counter stopped) 0 0 clk I/O / (No prescaling) 0 0 clk I/O /8 (From prescaler) 0 clk I/O /64 (From prescaler) 0 0 clk I/O /256 (From prescaler) 0 clk I/O /24 (From prescaler) 0 External clock source on T pin. Clock on falling edge. External clock source on T pin. Clock on rising edge. 2486P AVR 02/06

16 8-bit Timer/Counter Register Description Timer/Counter Control Register TCCR2 2486P AVR 02/06 ATmega8(L) Bit FOC2 WGM20 COM2 COM20 WGM2 CS22 CS2 CS20 TCCR2 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit 7 FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-pwm mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare Match is forced on the waveform generation unit. The OC2 output is changed according to its COM2:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM2:0 bits that determines the effect of the forced compare. A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP. The FOC2 bit is always read as zero. Bit 6,3 WGM2:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 42 and Modes of Operation on page. Table 42. Waveform Generation Mode Bit Description Mode WGM2 (CTC2) WGM20 (PWM2) Timer/Counter Mode of Operation () TOP Update of OCR2 TOV2 Flag Set Normal 0xFF Immediate MAX 0 PWM, Phase Correct 0xFF TOP BOTTOM 2 0 CTC OCR2 Immediate MAX 3 Fast PWM 0xFF TOP MAX Note:. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM2:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Bit 5:4 COM2:0: Compare Match Output Mode These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM2:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM2:0 bits depends on the WGM2:0 bit setting. Table 43 shows the COM2:0 bit functionality when the WGM2:0 bits are set to a normal or CTC mode (non-pwm). 7

17 Typical Applications Electric Power Steering (EPS) Anti-lock Braking System (ABS) Wiper Control Climate Control Power Door Benefits Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 75 C Operating Temperature AUTOMOTIVE MOSFET G HEXFET Power MOSFET D S PD-9399C IRF405 IRF405 VDSS = 55V R DS(on) = 5.3m ID = 69A Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions Drain-to-Source Breakdown 55 V = 250µA V(BR)DSS Voltage VGS = 0V, ID V(BR)DSS/ TJ Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, ID = ma RDS(on) Static Drain-to-Source On-Resistance m VGS = V, ID = A VGS(th) Gate Threshold Voltage V VDS = V, ID = 250µA gfs Forward Transconductance 69 S VDS = 25V, ID = A I DSS Drain-to-Source Leakage Current 20 µa VDS = 55V, VGS = 0V 250 VDS = 44V, VGS = 0V, TJ = 50 C Gate-to-Source Forward Leakage 200 VGS = 20V I GSS na Gate-to-Source Reverse Leakage -200 VGS = -20V Qg Total Gate Charge ID = A Qgs Gate-to-Source Charge nc VDS = 44V Fast Switching Repetitive Avalanche Allowed up to Tjmax Description Specifically designed for Automotive applications, this Stripe Planar design of HEXFET Power MOSFETs utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this HEXFET power MOSFET are a 75 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 69 I T C = 0 C Continuous Drain Current, V V 8 A I DM Pulsed Drain Current 680 P C = 25 C Power Dissipation 330 W Linear Derating Factor 2.2 W/ C V GS Gate-to-Source Voltage ± 20 V E AS Single Pulse Avalanche Energy 560 mj I AR Avalanche Current See Fig.2a, 2b, 5, 6 A E AR Repetitive Avalanche Energy mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to + 75 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting Torque, 6-32 or M3 screw lbf in (.N m) Thermal Resistance TO-220AB Parameter Typ. Max. Units R JC Junction-to-Case 0.45 C/W R CS Case-to-Sink, Flat, Greased Surface 0.50 R JA Junction-to-Ambient 62 Qgd Gate-to-Drain ("Miller") Charge VGS = V td(on) Turn-On Delay Time 3 VDD = 38V tr Rise Time 90 ID = A ns td(off) Turn-Off Delay Time 30 RG =. tf Fall Time VGS = V Between lead, L D Internal Drain Inductance 4.5 L S Internal Source Inductance 7.5 6mm (0.25in.) from package and center of die contact Ciss Input Capacitance 5480 VGS = 0V Coss Output Capacitance 2 pf VDS = 25V Crss Reverse Transfer Capacitance 280 ƒ =.0MHz, See Fig. 5 Coss Output Capacitance 52 VGS = 0V, VDS =.0V, ƒ =.0MHz Coss Output Capacitance 900 VGS = 0V, VDS = 44V, ƒ =.0MHz Coss eff. Effective Output Capacitance 500 VGS = 0V, VDS = 0V to 44V Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions IS Continuous Source Current MOSFET symbol (Body Diode) 69 A showing the ISM Pulsed Source Current integral reverse G 680 (Body Diode) p-n junction diode. VSD Diode Forward Voltage.3 V TJ = 25 C, IS = A, VGS = 0V trr Reverse Recovery Time ns TJ = 25 C, IF = A Qrr Reverse RecoveryCharge nc di/dt = 0A/µs ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ). Starting T J = 25 C, L = 0.mH R G = 25, I AS = A. (See Figure 2). ƒ I SD A, di/dt 2A/µs, V DD V (BR)DSS, T J 75 C Pulse width 400µs; duty cycle 2%. 2 nh Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Limited by T Jmax, see Fig.2a, 2b, 5, 6 for typical repetitive avalanche performance. G D 8/26/03 D S S

18 IRF TOP BOTTOM VGS 5V V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 4.5V 00 0 TOP BOTTOM VGS 5V V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 4.5V I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) 20µs PULSE WIDTH T J = 25 C 0. 0 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 00 0 I D, Drain-to-Source Current (A) T = 25 C J T = 75 C V DS = 25V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) J I = D 69A T, Junction Temperature( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3 R DS(on), Drain-to-Source On Resistance (Normalized) J V GS = V IRF I = D A V DS = 44V V DS = 27V V GS, Gate-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 00 0 I SD, Reverse Drain Current (A) T = 75 C J T = 25 C J V GS = 0 V V SD,Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 I D, Drain-to-Source Current (A) C, Capacitance(pF) V GS = 0V, f = MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd Ciss Coss Crss Tc = 25 C Tj = 75 C Single Pulse OPERATION IN THIS AREA LIMITED BY R DS (on) 0µsec msec msec V DS, Drain-toSource Voltage (V)

19 PD-9279E IRF3205 HEXFET Power MOSFET l Advanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 75 C Operating Temperature l Fast Switching l Fully Avalanche Rated Description Advanced HEXFET Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. G D S VDSS = 55V R DS(on) = 8.0mΩ ID = A The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry. Absolute Maximum Ratings TO-220AB Parameter Max. Units I T C = 25 C Continuous Drain Current, V V I T C = 0 C Continuous Drain Current, V V 80 A I DM Pulsed Drain Current 390 P C = 25 C Power Dissipation 200 W Linear Derating Factor.3 W/ C V GS Gate-to-Source Voltage ± 20 V I AR Avalanche Current 62 A E AR Repetitive Avalanche Energy 20 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to + 75 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torque, 6-32 or M3 srew lbf in (.N m) Thermal Resistance Parameter Typ. Max. Units RθJC Junction-to-Case 0.75 RθCS Case-to-Sink, Flat, Greased Surface 0.50 C/W RθJA Junction-to-Ambient 62 0/25/0 IRF3205 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V(BR)DSS Drain-to-Source Breakdown Voltage 55 V VGS = 0V, ID = 250µA V(BR)DSS/ TJ Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, ID = ma RDS(on) Static Drain-to-Source On-Resistance 8.0 mω VGS = V, ID = 62A VGS(th) Gate Threshold Voltage V VDS = VGS, ID = 250µA gfs Forward Transconductance 44 S VDS = 25V, ID = 62A I DSS Drain-to-Source Leakage Current 25 µa VDS = 55V, VGS = 0V I GSS 250 VDS = 44V, VGS = 0V, TJ = 50 C Gate-to-Source Forward Leakage 0 VGS = 20V Gate-to-Source Reverse Leakage -0 na VGS = -20V Qg Total Gate Charge 46 ID = 62A Qgs Gate-to-Source Charge 35 nc VDS = 44V Qgd Gate-to-Drain ("Miller") Charge 54 VGS = V, See Fig. 6 and 3 td(on) Turn-On Delay Time 4 VDD = 28V tr Rise Time ID = 62A ns td(off) Turn-Off Delay Time 50 RG = 4.5Ω tf Fall Time 65 VGS = V, See Fig. Between lead, L D Internal Drain Inductance 4.5 L S Internal Source Inductance 7.5 nh 6mm (0.25in.) from package and center of die contact G D Ciss Input Capacitance 3247 VGS = 0V Coss Output Capacitance 78 VDS = 25V Crss Reverse Transfer Capacitance 2 pf ƒ =.0MHz, See Fig. 5 E AS Single Pulse Avalanche Energy mj I AS = 62A, L = 38µH Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions IS Continuous Source Current MOSFET symbol (Body Diode) A showing the ISM Pulsed Source Current integral reverse 390 (Body Diode) p-n junction diode. G VSD Diode Forward Voltage.3 V TJ = 25 C, IS = 62A, VGS = 0V trr Reverse Recovery Time 69 4 ns TJ = 25 C, IF = 62A Qrr Reverse Recovery Charge nc di/dt = 0A/µs ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 38µH R G = 25Ω, I AS = 62A. (See Figure 2) ƒ I SD 62A, di/dt 207A/µs, V DD V (BR)DSS, T J 75 C Pulse width 400µs; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. This is a typical value at device destruction and represents operation outside rated limits. This is a calculated value limited to TJ = 75 C. 2 D S S

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