TL03x, TL03xA, TL03xY ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS

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1 Direct Upgrades for the TL6x Low-Power BiFETs Low Power Consumption mw/channel Typ On-Chip Offset-Voltage Trimming for Improved DC Performance (1.5 mv, TL31A) Higher Slew Rate and Bandwidth Without Increased Power Consumption Available in TSSOP for Small Form-Facr Designs description The TL3x series of JFET-input operational amplifiers offer improved dc and ac characteristics over the TL6x family of low-power BiFET operational amplifiers. On-chip zener trimming of offset voltage yields precision grades as low as 1.5 mv (TL31A) for greater accuracy in dc-coupled applications. Texas Instruments improved BiFET process and optimized designs also yield improved bandwidths and slew rates without increased power consumption. The TL3x devices are pin-compatible with the TL6x and can be used upgrade existing circuits or for optimal performance in new designs. BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transisrs without sacrificing the output drive associated with bipolar amplifiers. This higher input impedance makes the TL3x amplifiers better suited for interfacing with high-impedance sensors or very low-level ac signals. These devices also feature inherently better ac response than bipolar or CMOS devices having comparable power consumption. The TL3x family has been optimized for micropower operation, while improving on the performance of the TL6x series. Designers requiring significantly faster ac response should consider the Excalibur TLE26x family of low-power BiFET operational amplifiers. Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken observe common-mode input-voltage limits and output swing when operating from a single supply. DC biasing of the input signal is required and loads should be terminated a virtual-ground node at midsupply. Texas Instruments TLE226 integrated virtual-ground generar is useful when operating BiFET amplifiers from single supplies. The TL3x devices are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply systems, Texas Instruments LinCMOS families of operational amplifiers (TLC-prefix) are recommended. When moving from BiFET CMOS amplifiers, particular attention should be paid slew rate, bandwidth requirements, and output loading. The C-suffix devices are characterized for operation from C 7 C. The I-suffix devices are characterized for operation from C 85 C. The M-suffix devices are characterized for operation over the full military temperature range of 55 C 125 C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconducr products and disclaimers there appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1999, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 OFFSET N1 IN IN+ V CC IN IN+ TL31x, TL31Ax D, JG, OR P PACKAGE (TOP VIEW) OFFSET N TL31M, TL31AM FK PACKAGE (TOP VIEW) V CC OFFSET N No internal connection V CC+ OUT OFFSET N2 V CC+ OUT 1IN 1IN+ TL32x, TL32Ax D, JG, OR P PACKAGE (TOP VIEW) 1OUT 1IN 1IN+ V CC OUT TL32M, TL32AM FK PACKAGE (TOP VIEW) VCC VCC 2IN+ V CC+ 2OUT 2IN 2IN+ 2OUT 2IN 1IN+ V CC+ 2IN+ TL3x, TL3Ax D, J, N, OR PW PACKAGE (TOP VIEW) 1OUT 1IN 1IN+ V CC+ 2IN+ 2IN 2OUT IN 1OUT IN 2OUT TL3M, TL3AM FK PACKAGE (TOP VIEW) 3OUT OUT OUT IN IN+ V CC 3IN+ 3IN 3OUT IN 3IN IN+ V CC 3IN+ 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 TA C 7 C C 85 C VIOMAX AT 25 C.8 mv 1.5 mv SMALL OUTLINE (D) CHIP CARRIER (FK) AVAILABLE OPTIONS CERAMIC DIP (J) PACKAGED DEVICES CERAMIC DIP (JG) PLASTIC DIP (N) PLASTIC DIP (P) TL31ACD TL32ACD TL31ACP TL32ACP TL31CD TL32CD TL3ACD TL3ACN TL31CP TL32CP TSSOP (PW) mv TL3CD TL3CN TL3CPW.8 mv 1.5 mv TL31AID TL32AID TL31ID TL32ID TL3AID TL3AIN TL31AIP TL32AIP TL31IP TL32IP mv TL3ID TL3IN TL31AMD.8 mv TL32AMD TL31MD 55 C 125 C 1.5 mv TL32MD TL3AMD TL31AMFK TL32AMFK TL31AMJG TL32AMJG TL31AMP TL32AMP TL31MFK TL32MFK TL3AMFK TL3AMJ TL31MJG TL32MJG TL3AMN TL31MP TL32MP mv TL3MD TL3MFK TL3MJ TL3MN CHIP FORM (Y) TL31Y TL32Y TL3Y The D and PW packages are available taped and reeled and are indicated by adding an R suffix device type (e.g., TL3CDR or TL3CPWR). Chip forms are tested at 25 C. POST OFFICE BOX DALLAS, TEXAS

4 symbol (each amplifier) IN IN+ + OUT equivalent schematic (each amplifier) VCC+ Q5 Q1 Q2 Q3 D1 IN+ IN JF1 JF2 R3 Q6 R Q8 Q1 R6 Q11 R7 Q15 Q17 OUT Q1 Q C1 Q9 Q12 JF3 JF (see Note A) OFFSET N1 OFFSET N2 R1 R2 Q7 R5 R8 Q13 Q16 VCC NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL31. POST OFFICE BOX DALLAS, TEXAS 75265

5 TL31Y chip information This chip, when properly assembled, has characteristics similar the TL31C. Thermal compression or ultrasonic bonding can be used on the doped-aluminum bonding pads. These chips can be mounted with conductive epoxy or a gold-silicon preform. Bonding-Pad Assignments (6) (5) () (3) IN+ IN (3) (2) VCC+ (7) + (6) OUT 2 (7) OFFSET N1 OFFSET N2 (1) () VCC (5) (8) (1) (2) Chip Thickness: 15 MIls Typical Bonding Pads: Mils Minimum TJ(max) = 15 C Tolerances Are ±1%. All Dimensions Are in Mils. Pin () is Internally Connected Backside of the Chip. 5 POST OFFICE BOX DALLAS, TEXAS

6 TL32Y chip information This chip, when properly assembled, has characteristics similar the TL32C. Thermal compression or ultrasonic bonding can be used on the doped-aluminum bonding pads. These chips can be mounted with conductive epoxy or a gold-silicon preform. Bonding-Pad Assignments (7) (6) (5) 67 (8) () 1IN+ 1IN 2OUT VCC+ (8) (3) + (1) (2) 1OUT (5) + (7) 2IN+ (6) 2IN () VCC (1) 51 (2) (3) Chip Thickness: 15 Mils Typical Bonding Pads: Mils Minimum TJ(max) = 15 C Tolerances Are ±1%. All Dimensions Are in Mils. Pin () is Internally Connected Backside of Chip. 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 TL3Y chip information This chip, when properly assembled, has characteristics similar the TL3C. Thermal compression or ultrasonic bonding can be used on the doped-aluminum bonding pads. These chips can be mounted with conductive epoxy or a gold-silicon preform. 66 Bonding-Pad Assignments (13) (12) (11) (1) (9) (1) (8) (1) (7) (5) (1) (2) (3) () (5) (6) (6) (7) (8) (9) 93 1IN+ 1IN 2OUT 3IN+ 3IN OUT VCC+ () (3) + (1) (2) 1OUT (5) + (7) 2IN+ (1) (9) (1) + + (11) VCC (6) (8) (12) (13) 2IN 3OUT IN+ IN Chip Thickness: 15 Mils Typical Bonding Pads: Mils Minimum TJ(max) = 15 C Tolerances Are ±1%. All Dimensions Are in Mils. Pin (11) is Internally Connected Backside of the Chip. POST OFFICE BOX DALLAS, TEXAS

8 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC+ (see Note 1) V Supply voltage, V CC (see Note 1) V Differential input voltage, V ID (see Note 2) ±3 V Input voltage, V I (any input) (see Notes 1 and 3) ±15 V Input current, I I (each input) ±1 ma Output current, I O (each output) ± ma Total current in V CC ma Total current out of V CC ma Duration of short-circuit current at (or below) 25 C (see Note ) Unlimited Continuous tal power dissipation See Dissipation Rating Table Srage temperature range,t stg C 15 C Case temperature for 6 seconds: FK package C Lead temperature 1,6 mm (1 /16 inch) from case for 1 seconds: D, N, P, or PW package C Lead temperature 1,6 mm (1 /16 inch) from case for 6 seconds: J or JG package C Stresses beyond those listed under absolute maximum ratings may cause permanent damage the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect the midpoint between VCC+ and VCC. 2. Differential voltages are at IN+ with respect IN. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.. The output may be shorted either supply. Temperature and/or supply voltages must be limited ensure that the maximum dissipation rating is not exceeded. PACKAGE TA 25 C POWER RATING DISSIPATION RATING TABLE DERATING FACTOR ABOVE TA = 7 C POWER RATING TA = 85 C POWER RATING TA = 125 C POWER RATING D 95 mw 7.6 mw/ C 68 mw 9 mw 19 mw FK 1375 mw 11. mw/ C 88 mw 715 mw 275 mw J 1375 mw 11. mw/ C 88 mw 715 mw 275 mw JG 15 mw 8. mw/ C 672 mw 56 mw 21 mw N 115 mw 9.2 mw/ C 736 mw 598 mw 23 mw P 11 mw 8. mw/ C 6 mw 52 mw 2 mw PW 7 mw 5.6 mw/ C 8 mw N/A N/A recommended operating conditions C SUFFIX I SUFFIX M SUFFIX UNIT MIN MAX MIN MAX MIN MAX Supply voltage, VCC± ±5 ±15 ±5 ±15 ±5 ±15 V VCC± = ±5 V Common-mode mode input voltage, VIC V Operating free-air temperature, TA C 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 TL31C and TL31AC electrical characteristics at specified free-air temperature VIO αvio TL31C, TL31AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Input offset voltage Temperature coefficient of input offset voltage Input offset voltage long-term drift VO =, VIC =, RS = 5 Ω TL31C TL31AC TL31C TL31AC 25 C Full range C Full range C 7 C 25 C 7 C mv µv/ C 25 C.. µv/mo VO =, VIC =, 25 C IIO Input offset current See Figure 5 7 C VO =, VIC =, 25 C IIB Input bias current See Figure 5 7 C 5 8 VICR VOM+ VOM AVD Common-mode input voltage range Maximum positive peak output voltage swing Maximum negative peak output voltage swing Large-signal differential voltage amplification 25 C Full range C RL = 1 kω C V 7 C C RL = 1 kω C V 7 C C RL = 1 kω C V/mV 7 C ri Input resistance 25 C Ω ci Input capacitance 25 C 5 pf CMRR ksvr Common-mode VIC = VICRmin, rejection ratio VO =, RS =5Ω Ω 25 C pa pa C db 7 C Supply-voltage 25 C rejection ratio VO =, RS = 5 Ω C db ( VCC±/ VIO) 7 C Full range is C 7 C. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated using the Arrhenius equation and assuming an activation energy of.96 ev. At VCC± = ±5 V, VO = ±2.3 V; at, VO = ±1 V. V POST OFFICE BOX DALLAS, TEXAS

10 TL31C and TL31AC electrical characteristics at specified free-air temperature (continued) TL31C, TL31AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A 25 C PD Total power dissipation VO =, No load C mw 7 C C ICC Supply current VO =, No load C µa 7 C TL31C and TL31AC operating characteristics at specified free-air temperature SR+ SR TL31C, TL31AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Positive slew rate at unity gain Negative slew rate at unity gain 25 C C V/µs RL = 1 kω, CL = 1 pf, 7 C See Figure 1 25 C C V/µs 7 C VI(PP) = ±1 mv, 25 C tr Rise time RL = 1 kω, CL = 1 pf, C ns See Figures 1 and 2 7 C VI(PP) = ±1 mv, 25 C tf Fall time RL = 1 kω, CL = 1 pf, C ns Vn In B1 φm See Figure 1 7 C VI(PP) = ±1 mv, 25 C 11% 5% Overshoot facr CL = 1 pf, CL = 1 pf, C 1% % Equivalent input noise voltage Equivalent input noise current Unity-gain bandwidth TL31C TL31AC Phase margin at unity gain See Figures 1 and 2 7 C 12% 6% RS = 2 Ω,, See Figure 3 f = 1 Hz f = 1 khz f = 1 Hz f = 1 khz 25 C 25 C nv/ Hz f = 1 khz 25 C.3.3 pa/ Hz VI = 1 mv, RL = 1 kω, CL =25pF F, See Figure VI = 1 mv, RL = 1 kω, CL = 25 pf, See Figure For VCC± = ±5 V, VI(PP) = ±1 V; for, VI(PP) = ±5 V. 25 C C MHz 7 C C C C POST OFFICE BOX DALLAS, TEXAS 75265

11 TL31I and TL31AI electrical characteristics at specified free-air temperature VIO αvio IIO IIB VICR VOM+ VOM AVD TL31I, TL31AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Input offset voltage Temperature coefficient of input offset voltage Input offset voltage long-term drift Input offset current Input bias current Common-mode input voltage range Maximum positive peak output voltage swing Maximum negative peak output voltage swing Large-signal differential voltage amplification VO =, VIC =, RS = 5 Ω TL31I TL31AI TL31I TL31AI 25 C Full range C Full range C 85 C 25 C 85 C mv µv/ C 25 C.. µv/mo VO =, VIC =, 25 C pa See Figure 5 85 C na VO =, VIC =, 25 C pa See Figure 5 85 C na 25 C Full range C RL = 1 kω C V 85 C C RL = 1 kω C V 85 C C RL = 1 kω C V/mV 85 C ri Input resistance 25 C Ω ci Input capacitance 25 C 5 pf CMRR ksvr 25 C Common-mode VIC = VICRmin, C db rejection ratio VO =, RS = 5 Ω 85 C Supply-voltage 25 C rejection ratio VO =, RS = 5 Ω C db ( VCC±/ VIO) 85 C Full range is C 85 C. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated using the Arrhenius equation and assuming an activation energy of.96 ev. At VCC± = ±5 V, VO = ±2.3 V; at, VO = ±1 V. V POST OFFICE BOX DALLAS, TEXAS

12 TL31I and TL31AI electrical characteristics at specified free-air temperature (continued) TL31I, TL31AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A 25 C PD Total power dissipation VO =, No load C mw 85 C C ICC Supply current VO =, No load C µa 85 C TL31I and TL31AI operating characteristics at specified free-air temperature SR+ SR TL31I, TL31AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT 25 C Positive slew rate at unity gain C V/µs RL = 1 kω CL = 1 pf, 85 C See Figure 1 25 C Negative slew rate at unity gain C V/µs 85 C VI(PP) = ±1 mv, 25 C tr Rise time RL = 1 kω, CL = 1 pf, C ns See Figures 1 and 2 85 C VI(PP) = ±1 mv, 25 C tf Fall time RL = 1 kω, CL = 1 pf, C ns Vn In B1 φm See Figure 1 85 C VI(PP) = ±1 mv, 25 C 11% 5% Overshoot facr RL = 1 kω, CL = 1 pf, C 12% 5% Equivalent input noise voltage TL31I Equivalent input noise current Unity-gain bandwidth TL31AI Phase margin at unity gain See Figures 1 and 2 85 C 13% 7% RS = 2 Ω,, See Figure 3 f = 1 Hz f = 1 khz f = 1 Hz f = 1 khz 25 C 25 C nv/ Hz f = 1 khz 25 C pa/ Hz VI = 1 mv RL = 1 kω, CL =25pF F, See Figure VI = 1 mv, RL = 1 kω, CL = 25 pf See Figure For VCC± = ±5 V, VI(PP) = ±1 V; for, VI(PP) = ±5 V. 25 C C MHz 85 C C C C POST OFFICE BOX DALLAS, TEXAS 75265

13 TL31M and TL31AM electrical characteristics at specified free-air temperature VIO αvio IIO IIB VICR VOM+ VOM AVD TL31M, TL31AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Input offset voltage Temperature coefficient of input offset voltage Input offset voltage long-term drift Input offset current Input bias current Common-mode input voltage range Maximum positive peak output voltage swing Maximum negative peak output voltage swing Large-signal differential voltage amplification TL31M 25 C Full range C TL31AM Full range VO =, VIC =, = TL31M 25 C C RS 5 Ω 25 C TL31AM C mv µv/ C 25 C.. µv/mo VO =, VIC =, 25 C pa See Figure C na VO =, VIC =, 25 C pa See Figure C na 25 C Full range C RL = 1 kω 55 C V 125 C C RL = 1 kω 55 C V 125 C C RL = 1 kω 55 C V/mV 125 C ri Input resistance 25 C Ω ci Input capacitance 25 C 5 pf CMR Common-mode VIC = VICRmin, R rejection ratio VO =, RS =5Ω Ω ksvr 25 C C db 125 C Supply-voltage 25 C rejection ratio VO =, RS = 5 Ω 55 C db ( VCC±/ VIO) 125 C C PD Total power dissipation VO =, No load 55 C mw 125 C Full range is 55 C 125 C. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated using the Arrhenius equation and assuming an activation energy of.96 ev. At VCC± = ±5 V, VO = ±2.3 V; at, VO = ±1 V. V POST OFFICE BOX DALLAS, TEXAS

14 TL31M and TL31AM electrical characteristics at specified free-air temperature (continued) TL31M, TL31AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A 25 C ICC Supply current VO =, No load 55 C µa 125 C TL31M and TL31AM operating characteristics at specified free-air temperature TL31M, TL31AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT 25 C SR+ Positive slew rate at unity gain 55 C V/µs RL L = 1 kω, CL L = 1 pf, 125 C See Figure 1 25 C SR Negative slew rate at unity gain 55 C V/µs 125 C VI(PP) = ±1 mv, 25 C tr Rise time RL = 1 kω, CL = 1 pf, 55 C ns See Figures 1 and C VI(PP) = ±1 mv, 25 C tf Fall time RL = 1 kω, CL = 1 pf, 55 C ns See Figure C VI(PP) = ±1 mv, 25 C 11% 5% Overshoot facr RL = 1 kω, CL = 1 pf, 55 C 16% 6% See Figures 1 and C 1% 8% Vn f = 1 Hz TL31M 25 C Equivalent input RS = 2 Ω,, f = 1 khz 1 1 noise voltage See Figure 3 f = 1 Hz TL31AM 25 C f = 1 khz 1 1 nv/ Hz In Equivalent input noise current f = 1 khz 25 C pa/ Hz 25 C B1 Unity-gain bandwidth VI = 1 mv, RL = 1 kω, 55 C MHz CL =25pF F, See Figure 125 C.9.9 φm Phase margin at unity gain 25 C VI = 1 mv, RL = 1 kω, 55 C 57 6 CL =25pF F, See Figure 125 C For VCC± = ±5 V, VI(PP) = ±1 V; for, VI(PP) = ±5 V. 1 POST OFFICE BOX DALLAS, TEXAS 75265

15 TL31Y electrical characteristics, T A = 25 C VIO αvio TL31Y PARAMETER TEST CONDITIONS VCC± = ±5 V UNIT Input offset voltage Temperature coefficient of input offset voltage.5.5 mv VO =, VIC =, RS = 5 Ω µv/ C IIO Input offset current VO =, VIC =, 1 1 pa IIB Input bias current See Figure pa VICR VOM+ VOM AVD Common-mode input voltage range Maximum positive peak output voltage swing Maximum negative peak output voltage swing Large-signal differential voltage amplification RL = 1 kω.3 1 V RL = 1 kω V RL = 1 kω V/mV ri Input resistance Ω ci Input capacitance 5 pf CMRR ksvr Common-mode rejection ratio Supply-voltage rejection ratio ( VCC±/ VIO) VIC = VICRmin, RS = 5 Ω PD Total power dissipation VO =, ICC Supply current At VCC± = ±5 V, VO = ±2.3 V; at, VO = ±1 V. TL31Y operating characteristics, T A = 25 C VO =, 87 9 db VO =, RS = 5 Ω db No load mw µa TL31Y PARAMETER TEST CONDITIONS VCC± = ±5 V UNIT SR+ Positive slew rate at unity gain RL = 1 kω, CL = 1 pf, SR Negative slew rate at unity gain See Figure 1 RL = 1 kω, V/µs CL = 1 pf, See Figure V/µs tr Rise time VI(PP) = ±1 mv, ns tf Fall time RL = 1 kω, CL = 1 pf, ns Overshoot facr See Figures 1 and 2 11% 5% Vn Equivalent input noise voltage RS = 2 Ω,, f = 1 Hz See Figure 3 f = 1 khz 1 1 V nv/ Hz In Equivalent input noise current f = 1 khz.3.3 pa/ Hz B1 φm Unity-gain bandwidth Phase margin at unity gain VI = 1 mv, CL = 25 pf, VI = 1 mv, CL = 25 pf, For VCC± = ±5 V, VI(PP) = ±1 V; for, VI(PP) = ±5 V. RL = 1 kω, See Figure RL = 1 kω, See Figure MHz POST OFFICE BOX DALLAS, TEXAS

16 TL32C and TL32AC electrical characteristics at specified free-air temperature VIO αvio TL32C, TL32AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Input offset voltage Temperature coefficient of input offset voltage Input offset voltage long-term drift VO =, VIC =, RS = 5 Ω TL32C TL32AC TL32C TL32AC 25 C Full range C Full range C 7 C 25 C 7 C mv µv/ C 25 C.. µv/mo VO =, VIC =, 25 C IIO Input offset current O See Figure 5 7 C VO =, VIC =, 25 C IIB Input bias current See Figure 5 7 C 5 8 VICR VOM+ VOM AVD Common-mode input voltage range Maximum positive peak output voltage swing 25 C Full range C RL = 1 kω C V 7 C Maximum negative 25 C peak output voltage RL = 1 kω C V swing 7 C Large-signal differential voltage amplification 25 C RL = 1 kω C V/mV 7 C ri Input resistance 25 C Ω ci Input capacitance 25 C 5 1 pf CMRR ksvr Common-mode VIC = VICRmin, rejection ratio VO =, RS =5Ω Ω Supply-voltage rejection ratio ( VCC±/ VIO) VCC± = ±5 V ±15 V, VO =, RS = 5 Ω 25 C pa pa C db 7 C C C db 7 C Full range is C 7 C. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated using the Arrhenius equation and assuming an activation energy of.96 ev. At VCC± = ±5 V, VO = 2.3 V; at, VO = ±1 V. V 16 POST OFFICE BOX DALLAS, TEXAS 75265

17 TL32C and TL32AC electrical characteristics at specified free-air temperature (continued) PD ICC TL32C, TL32AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Ttl Total power dissipationi (two amplifiers) Supply current (two amplifiers) 25 C VO =, No load C mw VO =, No load 7 C C C VO1/VO2 Crosstalk attenuation AVD = 1 db 25 C db TL32C and TL32AC operating characteristics at specified free-air temperature SR+ SR TL32C, TL32AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT Positive slew rate at unity gain Negative slew rate at unity gain 25 C µa C V/µs RL = 1 kω, CL L = 1 pf, 7 C See Figure 1 25 C C V/µs 7 C C tr Rise time C ns tf Vn Fall time 7 C C VI(PP) = ±1 V, RL = 1 kω, CL = 1 pf, C ns See Figures 1 and 2 7 C C 11% 5% Overshoot facr C 1% % Equivalent input noise voltage TL32C TL32AC RS = 2 Ω,, See Figure 3 f = 1 Hz f = 1 khz f = 1 Hz f = 1 khz 7 C 12% 6% 25 C 25 C nv/ Hz In Equivalent input noise current f = 1 khz 25 C.3.3 pa/ Hz B1 φm Unity-gain bandwidth Phase margin at unity gain VI = 1 mv, RL = 1 kω, CL =25pF F, See Figure VI = 1 mv, RL = 1 kω, CL = 25 pf, See Figure For VCC± = ±5 V, VI(PP) = ±1 V; for, VI(PP) = ±5 V. 25 C C MHz 7 C C C C 6 6 POST OFFICE BOX DALLAS, TEXAS

18 TL32I and TL32AI electrical characteristics at specified free-air temperature VIO αvio TL32I, TL32AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Input offset voltage Temperature coefficient of input offset voltage Input offset voltage long-term drift VO =, VIC =, RS = 5 Ω TL32I TL32AI TL32I TL32AI 25 C Full range C Full range C 85 C 25 C 85 C mv µv/ C 25 C.. µv/mo VO =, VIC =, 25 C pa IIO Input offset current See Figure 5 85 C na VO =, VIC =, 25 C pa IIB Input bias current See Figure 5 85 C na VICR VOM+ VOM AVD Common-mode input voltage range Maximum positive peak output voltage swing 25 C Full range C RL = 1 kω C V 85 C Maximum negative 25 C peak output voltage RL = 1 kω C V swing 85 C Large-signal g differential voltage amplification RL =1kΩ C C ri Input resistance 25 C Ω ci Input capacitance 25 C 5 pf CMRR ksvr Common-mode VIC = VICRmin, rejection ratio VO =, RS =5Ω Ω Supply-voltage rejection ratio ( VCC±/ VIO) VCC± = ±5 V±15 V, 25 C V V/mV C db 85 C C C db VO =, RS = 5 Ω 85 C Full range is C 85 C. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated using the Arrhenius equation and assuming an activation energy of.96 ev. At VCC± = ±5 V, VO = 2.3 V; at, VO = ±1 V. 18 POST OFFICE BOX DALLAS, TEXAS 75265

19 TL32I and TL32AI electrical characteristics at specified free-air temperature (continued) PD ICC TL32I, TL32AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Ttl Total power dissipation i (two amplifiers) Supply current (two amplifiers) 25 C VO =, No load C mw 85 C C VO =, No load C µa 85 C VO1/VO2 Crosstalk attenuation AVD = 1 db 25 C db TL32I and TL32AI operating characteristics at specified free-air temperature SR+ SR tr TL32I, TL32AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT Positive slew rate at unity gain Negative slew rate at unity gain Rise time RL =1kΩ kω, CL = 1 pf 25 C C V/µs 85 C C C V/µs 85 C C VI(PP) = ±1 V, RL = 1 kω, CL = 1 pf, C ns See Figures 1 and 2 85 C tf Fall time Overshoot facr 25 C VI(PP) = ±1 V, RL = 1 kω, CL = 1 pf, C ns See Figure 1 85 C C 11% 5% VI(PP) = ±1 V, RL = 1 kω, CL = 1 pf, C 12% 5% See Figures 1 and 2 85 C 13% 7% Vn In B1 φm Equivalent input noise voltage Equivalent input noise current Unity-gain bandwidth TL32I TL32AI Phase margin at unity gain RS = 2 Ω,, See Figure 3 f = 1 Hz f = 1 khz f = 1 Hz f = 1 khz 25 C 25 C nv/ Hz f = 1 khz 25 C.3.3 pa/ Hz VI = 1 mv, RL = 1 kω, CL =25pF F, See Figure VI = 1 mv, RL = 1 kω, CL = 25 pf, See Figure For VCC± = ±5 V, VI(PP) = ±1 V; for, VI(PP) = ±5 V. 25 C C MHz 85 C C C C 6 6 POST OFFICE BOX DALLAS, TEXAS

20 TL32M and TL32AM electrical characteristics at specified free-air temperature VIO αvio TL32M, TL32AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Input offset voltage Temperature coefficient of input offset voltage Input offset voltage long-term drift VO =, VIC =, RS = 5 Ω TL32M TL32AM TL32M TL32AM 25 C Full range C Full range C 125 C 25 C 125 C mv µv/ C 25 C.. µv/mo VO =, VIC =, 25 C pa IIO Input offset current See Figure C na VO =, VIC =, 25 C pa IIB Input bias current See Figure C na VICR VOM+ VOM AVD Common-mode input voltage range Maximum positive peak output voltage swing Maximum negative peak output voltage swing Large-signal differential voltage amplification 25 C Full range C RL = 1 kω 55 C V 125 C C RL = 1 kω 55 C V 125 C C RL = 1 kω 55 C V/mV 125 C ri Input resistance 25 C Ω ci Input capacitance 25 C 5 pf CMRR ksvr Common-mode rejection VIC = VICRmin, ratio VO =, RS =5Ω Ω Supply-voltage rejection ratio ( VCC±/ VIO) VCC± = ±5 V ±15 V, VO =, RS = 5 Ω 25 C C db 125 C C C db 125 C Full range is 55 C 125 C. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated using the Arrhenius equation and assuming an activation energy of.96 ev. At VCC± = ±5 V, VO = 2.3 V; at, VO = ±1 V. V 2 POST OFFICE BOX DALLAS, TEXAS 75265

21 TL32M and TL32AM electrical characteristics at specified free-air temperature (continued) PD ICC TL32M, TL32AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Ttl Total power dissipationi (two amplifiers) Supply current (two amplifiers) 25 C VO =, No load 55 C mw 125 C C VO =, No load 55 C µa 125 C VO1/VO2 Crosstalk attenuation AVD = 1 db 25 C db TL32M and TL32AM operating characteristics at specified free-air temperature SR+ SR tr tf Vn In B1 φm TL32M, TL32AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT Positive slew rate at unity gain Negative slew rate at unity gain Rise time Fall time Overshoot facr Equivalent input noise voltage TL32M TL32AM Equivalent input noise current Unity-gain bandwidth Phase margin at unity gain RL = 1 kω, CL = 1 pf, See and Figure 1 25 C C V/µs 125 C C C V/µs 125 C VI(PP) = ±1 V, 25 C RL = 1 kω, Ω 55 C ns CL = 1 pf, See Figures 1 and C VI(PP) = ±1 V, 25 C RL = 1 kω, Ω 55 C ns CL = 1 pf, See Figure C VI(PP) = ±1 V, 25 C 11% 5% RL = 1 kω, Ω 55 C 16% 6% CL = 1 pf, See Figures 1 and C 1% 8% RS = 2 Ω,, See Figure 3 f = 1 Hz f = 1 khz f = 1 Hz f = 1 khz 25 C 25 C nv/ Hz f = 1 khz 25 C.3.3 pa/ Hz VI = 1 mv, RL = 1 kω, CL =25pF F, See Figure VI = 1 mv, RL = 1 kω, CL = 25 pf, See Figure For VCC± = ±5 V, VI(PP) = ±1 V; for, VI(PP) = ±5 V. 25 C C MHz 125 C C C C POST OFFICE BOX DALLAS, TEXAS

22 TL32Y electrical characteristics, T A = 25 C VIO αvio IIO IIB VICR VOM+ VOM AVD TL32Y PARAMETER TEST CONDITIONS VCC± = ±5 V UNIT Input offset voltage Temperature coefficient of input offset voltage Input offset current Input bias current Common-mode input voltage range Maximum positive peak output voltage swing Maximum negative peak output voltage swing Large-signal differential voltage amplification VO =, VIC =, RS = 5 Ω VO =, See Figure 5 VO =, See Figure 5 VIC =, VIC =, mv µv/ C pa 2 2 pa RL = 1 kω.3 1 V RL = 1 kω V RL = 1 kω V/mV ri Input resistance Ω ci Input capacitance 5 1 pf CMRR ksvr PD Common-mode rejection ratio Supply-voltage rejection ratio ( VCC±/ VIO) Total power dissipation (two amplifiers) VIC = VICRmin, VO =, RS = 5 Ω VCC± = ±5 V ±15 V, VO =, RS = 5 Ω 87 9 db db VO =, No load mw VO1/VO2 Crosstalk attenuation AVD = 1 db db At VCC± = ±5 V, VO = 2.3 V; at, VO = ±1 V. TL32Y operating characteristics, T A = 25 C TL32Y PARAMETER TEST CONDITIONS VCC± = ±5 V UNIT SR+ Positive slew rate at unity gain RL = 1 kω, CL = 1 pf, V/µs SR Negative slew rate at unity gain See Figure 1 and Note V/µs tr Rise time VI(PP) = ±1 V, ns tf Fall time RL = 1 kω,, CL = 1 pf, ns Overshoot facr See Figures 1 and 2 11% 5% RS = 2 Ω, f = 1 Hz 9 9 Vn Equivalent input noise voltage, See Figure 3 f = 1 khz 1 1 V nv/ Hz In Equivalent input noise current f = 1 khz.3.3 pa/ Hz B1 φm Unity-gain bandwidth Phase margin at unity gain VI = 1 mv, CL = 25 pf, VI = 1 mv, CL = 25 pf, For VCC± = ±5 V, VI(PP) = ±1 V; for, VI(PP) = ±5 V. RL = 1 kω, See Figure RL = 1 kω, See Figure MHz POST OFFICE BOX DALLAS, TEXAS 75265

23 TL3C and TL3AC electrical characteristics at specified free-air temperature VIO αvio TL3C, TL3AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Input offset voltage Temperature coefficient of input offset voltage TL3C VO =, TL3AC VIC =, RS = 5 Ω TL3C TL3AC 25 C Full range C Full range C 7 C 25 C 7 C mv µv/ C Input offset voltage long-term drift 25 C.. µv/mo VO =, VIC =, 25 C IIO Input offset current O See Figure 5 7 C VO =, VIC =, 25 C IIB Input bias current See Figure 5 7 C 5 8 VICR VOM+ VOM AVD Common-mode input voltage range Maximum positive peak output voltage swing Maximum negative peak output voltage swing Large-signal differential voltage amplification 25 C Full range C RL = 1 kω C V 7 C C RL = 1 kω C V 7 C C RL = 1 kω C V/mV 7 C ri Input resistance 25 C Ω ci Input capacitance 25 C 5 1 pf CMRR ksvr Common-mode rejection ratio 25 C VIC = VICRmin, VO =, C db RS = 5 Ω 7 C Supply-voltage 25 C rejection ratio VO =, RS = 5 Ω C db ( VCC±/ VIO) 7 C Full range is C 7 C. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated using the Arrhenius equation and assuming an activation energy of.96 ev. At VCC± = ±5 V, VO = ±2.3 V; at, VO = ±1 V. pa pa V POST OFFICE BOX DALLAS, TEXAS

24 TL3C and TL3AC electrical characteristics at specified free-air temperature (continued) PD TL3C, TL3AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Ttl Total power dissipationi (two amplifiers) 25 C VO =, No load C mw 7 C C ICC Supply current (four amplifiers) VO =, No load C ma 7 C VO1/VO2 Crosstalk attenuation AVD = 1 25 C db TL3C and TL3AC operating characteristics at specified free-air temperature SR+ SR tr tf Vn TL3C, TL3AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT Positive slew rate at unity gain Negative slew rate at unity gain Rise time Fall time Overshoot facr Equivalent input noise voltage TL3C TL3AC RL = 1 kω, CL = 1 pf, See Figure 1 25 C C V/µs 7 C C C V/µs 7 C VI(PP) = ±1 V, 25 C RL = 1 kω, Ω C ns CL = 1 pf, See Figures 1 and 2 7 C VI(PP) = ±1 V, 25 C RL = 1 kω, Ω C ns CL = 1 pf, See Figure 1 7 C VI(PP) = ±1 V, 25 C 11% 5% RL = 1 kω, Ω C 1% % CL = 1 pf, See Figures 1 and 2 7 C 12% 6% RS = 2 Ω,, See Figure 3 f = 1 Hz f = 1 khz f = 1 Hz f = 1 khz 25 C 25 C nv/ Hz In Equivalent input noise current f = 1 khz 25 C.3.3 pa/ Hz B1 φm Unity-gain bandwidth Phase margin at unity gain VI = 1 mv, RL = 1 kω, CL =25pF F, See Figure VI = 1 mv, RL = 1 kω, CL =25pF F, See Figure For VCC± = ±5 V, VI(PP) = ±1 V; for, VI(PP) = ±5 V. 25 C C MHz 7 C C C C POST OFFICE BOX DALLAS, TEXAS 75265

25 TL3I and TL3AI electrical characteristics at specified free-air temperature VIO αvio TL3I, TL3AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Input offset voltage Temperature coefficient of input offset voltage Input offset voltage long-term drift TL3I VO =, TL3AI VIC =, RS = 5 Ω TL3I TL3AI 25 C Full range C Full range C 85 C 25 C 85 C mv µv/ C 25 C.. µv/mo VO =, VIC =, 25 C pa IIO Input offset current O See Figure 5 85 C na VO =, VIC =, 25 C pa IIB Input bias current See Figure 5 85 C na VICR VOM+ VOM AVD Common-mode input voltage range Maximum positive peak output voltage swing Maximum negative peak output voltage swing Large-signal g differential voltage amplification 25 C Full range C RL = 1 kω C V 85 C C RL = 1 kω C V RL =1kΩ 85 C C C ri Input resistance 25 C Ω ci Input capacitance 25 C 5 pf CMRR ksvr Common-mode rejection ratio V V/mV 25 C VIC = VICRmin, VO =, C db RS = 5 Ω 85 C Supply-voltage 25 C rejection ratio VO =, RS = 5 Ω C db ( VCC±/ VIO) 85 C Full range is C 85 C. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated using the Arrhenius equation and assuming an activation energy of.96 ev. At VCC± = ±5 V, VO = ±2.3 V; at, VO = ±1 V. POST OFFICE BOX DALLAS, TEXAS

26 TL3I and TL3AI electrical characteristics at specified free-air temperature (continued) PD TL3I, TL3AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Ttl Total power dissipationi (four amplifiers) 25 C VO =, No load C mw 85 C C ICC Supply current (four amplifiers) VO =, No load C ma 85 C VO1/VO2 Crosstalk attenuation AVD = 1 25 C db TL3I and TL3AI operating characteristics SR+ SR TL3I, TL3AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT Positive slew rate at unity gain Negative slew rate at unity gain 25 C C V/µs RL = 1 kω, CL = 1 pf, 85 C See Figure 1 25 C C V/µs 85 C C tr Rise time C ns tf Vn In B1 φm Fall time 85 C VI(PP) = ±1 V, 25 C RL = 1 kω, Ω C ns CL = 1 pf, See Figures 1 and 2 85 C C 11% 5% Overshoot facr C 12% 5% Equivalent input noise voltage Equivalent input noise current Unity-gain bandwidth TL3I TL3AI Phase margin at unity gain RS S = 2 Ω,, See Figure 3 f = 1 Hz f = 1 khz f = 1 Hz f = 1 khz 85 C 13% 7% 25 C 25 C nv/ Hz f = 1 khz 25 C.3.3 pa/ Hz VI = 1 mv, RL = 1 kω, CL =25pF F, See Figure VI = 1 mv, RL = 1 kω, CL =25pF F, See Figure For VCC± = ±5 V, VI(PP) = ±1 V; for, VI(PP) = ±5 V. 25 C C MHz 85 C C C C POST OFFICE BOX DALLAS, TEXAS 75265

27 TL3M and TL3AM electrical characteristics at specified free-air temperature VIO αvio TL3M, TL3AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Input offset voltage Temperature coefficient of input offset voltage Input offset voltage long-term drift TL3M 25 C Full range C VO =, TL3AM Full range VIC =, RS = 5 Ω 25 C TL3M C TL3AM 25 C 125 C mv µv/ C 25 C.. µv/mo VO =, VIC =, 25 C pa IIO Input offset current O See Figure C na VO =, VIC =, 25 C pa IIB Input bias current See Figure C na VICR VOM+ VOM AVD Common-mode input voltage range Maximum positive peak output voltage swing Maximum negative peak output voltage swing Large-signal differential voltage amplification 25 C Full range C RL = 1 kω 55 C V 125 C C RL = 1 kω 55 C V 125 C C RL = 1 kω 55 C V/mV 125 C ri Input resistance 25 C Ω ci Input capacitance 25 C 5 pf CMRR ksvr Common-mode VIC = VICRmin, rejection ratio VO =, RS =5Ω Ω 25 C C db 125 C Supply-voltage 25 C rejection ratio VO =, RS = 5 Ω 55 C db ( VCC±/ VIO) 125 C Full range is 55 C 125 C. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated TA = 25 C using the Arrhenius equation and assuming an activation energy of.96 ev. At VCC± = ±5 V, VO = ±2.3 V; at, VO = ±1 V. V POST OFFICE BOX DALLAS, TEXAS

28 TL3M and TL3AM electrical characteristics at specified free-air temperature (continued) PD TL3M, TL3AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT A Ttl Total power dissipationi (two amplifiers) 25 C VO =, No load 55 C mw 125 C C ICC Supply current (two amplifiers) VO =, No load 55 C ma 125 C VO1/VO2 Crosstalk attenuation AVD = 1 25 C db TL3M and TL3AM operating characteristics at specified free-air temperature SR+ SR tr tf Vn In B1 φm TL3M, TL3AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V UNIT Positive slew rate at unity gain Negative slew rate at unity gain Rise time Fall time Overshoot facr Equivalent input noise voltage Equivalent input noise current Unity-gain bandwidth TL3M TL3AM Phase margin at unity gain RL = 1 kω, CL = 1 pf, See Figure 1 25 C C V/µs 125 C C C V/µs 125 C VI(PP) = ±1 V, 25 C RL = 1 kω, Ω 55 C ns CL = 1 pf, See Figures 1 and C VI(PP) = ±1 V, 25 C RL = 1 kω, Ω 55 C ns CL = 1 pf, See Figure C VI(PP) = ±1 V, 25 C 11% 5% RL = 1 kω, Ω 55 C 16% 6% CL = 1 pf, See Figures 1 and C 1% 8% RS = 2 Ω,, See Figure 3 f = 1 Hz f = 1 khz f = 1 Hz f = 1 khz 25 C 25 C nv/ Hz f = 1 khz 25 C.3.3 pa/ Hz VI = 1 mv, RL = 1 kω, CL =25pF F, See Figure VI = 1 mv, RL = 1 kω, CL =25pF F, See Figure For VCC± = ±5 V, VI(PP) = ±1 V; for, VI(PP) = ±5 V. 25 C C MHz 125 C C C C POST OFFICE BOX DALLAS, TEXAS 75265

29 TL3Y electrical characteristics, T A = 25 C VIO αvio TL3Y PARAMETER TEST CONDITIONS VCC± = ±5 V UNIT Input offset voltage Temperature coefficient of input offset voltage VO =, VIC =, RS = 5 Ω mv µv/ C VO =, VIC =, 1 1 IIO Input offset current See Figure VO =, VIC =, 2 2 pa IIB Input bias current See Figure na VICR VOM+ VOM AVD Common-mode input voltage range Maximum positive peak output voltage swing Maximum negative peak output voltage swing RL = 1 kω.3 1 V RL = 1 kω V Large-signal differential voltage amplification RL = 1 kω V/mV ri Input resistance Ω ci Input capacitance 5 pf CMRR ksvr PD Common-mode rejection ratio Supply-voltage rejection ratio ( VCC±/ VIO) Total power dissipation (four amplifiers) VIC = VICRmin, VO =, RS = 5 Ω pa 87 9 db VO =, RS = 5 Ω db VO =, No load mw ICC Supply current (four amplifiers) VO =, No load ma VO1/VO2 Crosstalk attenuation AVD = db At VCC± = ±5 V, VO = ±2.3 V; at, VO = ±1 V. TL3Y operating characteristics, T A = 25 C TL3Y PARAMETER TEST CONDITIONS VCC± = ±5 V UNIT SR+ Positive slew rate at unity gain RL = 1 kω, CL = 1 pf, V/µs SR Negative slew rate at unity gain See Figure V/µs tr Rise time VI(PP) = ±1 V, ns tf Fall time RL = 1 kω, CL = 1 pf, ns Overshoot facr See Figures 1 and 2 11% 5% Vn Equivalent input noise voltage RS S = 2 Ω,, f = 1 khz See Figure 3 f = 1 khz 3 3 V nv/ Hz In Equivalent input noise current f = 1 khz.3.3 pa/ Hz B1 φm Unity-gain bandwidth Phase margin at unity gain VI = 1 mv, CL = 25 pf, VI = 1 mv, CL = 25 pf, RL = 1 kω, See Figure RL = 1 kω, See Figure MHz POST OFFICE BOX DALLAS, TEXAS

30 PARAMETER MEASUREMENT INFORMATION VCC+ VI + VO Overshoot 9% VCC CL (see Note A) RL 1% NOTE A: CL includes fixture capacitance. Figure 1. Slew-Rate and Overshoot Test Circuit tr Figure 2. Rise Time and Overshoot Waveform 1 kω 1 kω VCC+ VI 1 Ω VCC+ + VO VCC VO VCC CL (see Note A) RL RS RS NOTE A: CL includes fixture capacitance. Figure 3. Noise-Voltage Test Circuit Figure. Unity-Gain Bandwidth and Phase-Margin Test Circuit Ground Shield VCC+ + VCC Picoammeters Figure 5. Input-Bias and Offset-Current Test Circuit 3 POST OFFICE BOX DALLAS, TEXAS 75265

31 PARAMETER MEASUREMENT INFORMATION typical values Typical values presented in this data sheet represent the median (5% point) of device parametric performance. input bias and offset current noise At the picoampere bias current level typical of the TL3x and TL3xA, accurate measurement of the bias current becomes difficult. Not only does this measurement require a picoammeter, but test-socket leakages easily can exceed the actual device bias currents. To accurately measure these small currents, Texas Instruments uses a two-step process. The socket leakage is measured using picoammeters with bias voltages applied but with no device in the socket. The device is then inserted in the socket and a second test that measures both the socket leakage and the device input bias current is performed. The two measurements are then subtracted algebraically determine the bias current of the device. With the increasing emphasis on low noise levels in many of day s applications, the input noise voltage density is performed at f = 1 khz, unless otherwise noted. POST OFFICE BOX DALLAS, TEXAS

32 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Distribution of TL3x input offset voltages 6 11 Distribution of TL3x input offset-voltage temperature coefficients 12, 13, 1 Input bias current Common-mode input voltage 15 Input bias current and Input offset current Free-air temperature 16 Common-mode input voltage range Supply voltage 17 Common-mode input voltage range Free-air temperature 18 Output voltage Differential input voltage 19, 2 Maximum peak output voltage Supply voltage 21 Maximum peak--peak output voltage Frequency 22 Maximum peak output voltage Output current 23, 2 Maximum peak output voltage Free-air temperature 25, 26 Large-signal differential voltage amplification Load resistance 27 Large-signal differential voltage amplification and Phase shift Frequency 28 Large-signal differential voltage amplification and Phase shift Free-air temperature 29 Output impedance Frequency with VCC = 15 V 3 Common-mode rejection ratio Frequency 31, 32 Common-mode rejection ratio Free-air temperature 33 Supply-voltage rejection ratio Free-air temperature 3 Short-circuit output current Supply voltage 35 Short-circuit output current Time 36 Short-circuit output current Free-air temperature 37 Equivalent input noise voltage Frequency (for TL31 and TL31A) 38 Equivalent input noise voltage Frequency (for TL32 and TL32A) 39 Equivalent input noise voltage Frequency (for TL3 and TL3A) Supply current Supply voltage (for TL31 and TL31A) 1 Supply current Supply voltage (for TL32 and TL32A) 2 Supply current Supply voltage (for TL3 and TL3A) 3 Supply current Free-air temperature (for TL31 and TL31A) Supply current Free-air temperature (for TL32 and TL32A) 5 Supply current Free-air temperature (for TL3 and TL3A) 6 Slew rate Load resistance 7, 8 Slew rate Free-air temperature 9, 5 Overshoot facr Load capacitance 51 Total harmonic disrtion Frequency 52 Unity-gain bandwidth Supply voltage 53 Unity-gain bandwidth Free-air temperature 5 Phase margin Supply voltage 55 Phase margin Load capacitance 56 Phase margin Free-air temperature 57 Voltage-follower small-signal pulse response Time 58 Voltage-follower large-signal pulse response Time 59, 6 32 POST OFFICE BOX DALLAS, TEXAS 75265

33 TYPICAL CHARACTERISTICS Percentage of Units % DISTRIBUTION OF TL31 INPUT OFFSET VOLTAGE 1681 Units Tested From 1 Wafer Lot ÎÎÎÎ P Package Percentage of Units % DISTRIBUTION OF TL31A INPUT OFFSET VOLTAGE 133 Units Tested From 1 Wafer Lot P Package VIO Input Offset Voltage mv Figure VIO Input Offset Voltage µv Figure 7 Percentage of Amplification % DISTRIBUTION OF TL32 INPUT OFFSET VOLTAGE ÎÎ 1681 Amplifiers Tested From 1 Wafer Lot P Package Percentage of Amplifiers % DISTRIBUTION OF TL32A INPUT OFFSET VOLTAGE 1321 Amplifiers Tested From 1 Wafer Lot P Package VIO Input Offset Voltage mv Figure 8 VIO Input Offset Voltage µv Figure 9 POST OFFICE BOX DALLAS, TEXAS

34 TYPICAL CHARACTERISTICS Percentage of Amplifiers % DISTRIBUTION OF TL3 INPUT OFFSET VOLTAGE 1681 Amplifiers Tested From 1 Wafer Lot D Package Percentage of Amplifiers % DISTRIBUTION OF TL3A INPUT OFFSET VOLTAGE ÎÎ 1716 Amplifiers Tested From 3 Wafer Lots Î 15 N Package VIO Input Offset Voltage mv Figure 1 VIO Input Offset Voltage mv Figure 11 Percentage of Units % DISTRIBUTION OF TL31 INPUT OFFSET-VOLTAGE TEMPERATURE COEFFICIENT 76 Units Tested From 1 Wafer Lot 125 C P Package Percentage of Amplifiers % DISTRIBUTION OF TL32 INPUT OFFSET-VOLTAGE TEMPERATURE COEFFICIENT ÎÎÎ 16 Amplifiers Tested From 2 Wafer Lots 125 C P Package ÎÎ αvio Input Offset-Voltage Temperature Coefficient µv/ C Figure αvio Temperature Coefficient µv/ C Figure 13 3 POST OFFICE BOX DALLAS, TEXAS 75265

35 TYPICAL CHARACTERISTICS Percentage of Amplifiers % DISTRIBUTION OF TL3 INPUT OFFSET-VOLTAGE TEMPERATURE COEFFICIENT ÎÎ 16 Amplifiers Tested From 2 Wafer Lots 125 C D Package IIB Input Bias Current na INPUT BIAS CURRENT COMMON-MODE INPUT VOLTAGE αvio Temperature Coefficient µv/ C Figure VIC Common-Mode Input Voltage V Figure 15 IIB I IB and IIO Input Bias and Input Offset Currents na INPUT BIAS CURRENT AND INPUT OFFSET CURRENT FREE-AIR TEMPERATURE ÁÁÁÁÁ ÁÁÁÁÁ VO = VIC = ÎÎÎ I IB ÎÎ I IO TA Free-Air Temperature C Figure 16 V VIC IC Common-Mode Input Voltage V ÁÁ ÁÁ COMMON-MODE INPUT VOLTAGE SUPPLY VOLTAGE Positive Limit Negative Limit VCC± Supply Voltage V Figure 17 Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS