TLE2227, TLE2227Y, TLE2237, TLE2237Y EXCALIBUR LOW-NOISE HIGH-SPEED PRECISION DUAL OPERATIONAL AMPLIFIERS

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1 Outstanding Combination of DC Precision and AC Performance: Unity-Gain Bandwidth MHz Typ V n nv/ Hz at f = 1 Hz Typ,.5 nv/ Hz at f = 1 khz Typ V IO... 1 µv Typ A VD... 5 V/µV Typ With R L = kω 38 V/µV Typ With R L = 1 kω Available in 16-Pin Small-Outline Wide-Body Package Macromodels and Statistical Information Included Output Features Saturation Recovery Circuitry description The TLEx7C combines innovative circuit design expertise and high-quality process control techniques to produce a level of ac performance and dc precision previously unavailable in dual operational amplifiers. This device allows upgrades to systems that use lower-precision devices and is manufactured using Texas Instruments state-of-the-art Excalibur process. TLE7, TLE7Y, TLE37, TLE37Y In the area of dc precision, the TLEx7C offers a typical offset voltage of 1 µv, a common-mode rejection ratio of 115 db (typ), a supply voltage rejection ratio of 1 db (typ), and a dc gain of 5 V/µV (typ). The ac performance is highlighted by a typical unity-gain bandwidth specification of 15 MHz, 55 of phase margin, and noise voltage specifications of 3.3 nv/ Hz and.5 nv/ Hz at frequencies of 1 Hz and 1 khz, respectively. The TLEx7C is available in a wide variety of packages, including the industry standard 16-pin small-outline wide-body version for high-density system applications. This device is characterized for operation from C to 7 C. TA VIOtyp AT 5 C AVAILABLE OPTIONS SMALL OUTLINE (DW) PACKAGED DEVICES PLASTIC DIP (P) 1OUT 1IN 1IN V CC NC NC 1OUT 1IN 1IN V CC NC NC P PACKAGE (TOP VIEW) CHIP FORM (Y) 1 µv TLE7CDW TLE7CP TLE7Y C to7 C 1 µv TLE37CDW TLE37CP TLE37Y The DW package is available taped and reeled. Add R suffix to device type (e.g., TLE7CDWR). Chip forms are tested at 5 C only DW PACKAGE (TOP VIEW) V CC OUT IN IN NC NC V CC OUT IN IN NC NC NC No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1997, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 symbol (each amplifier) IN IN OUT TLE7Y chip information This chip, properly assembled, displays characteristics similar to the TLE7C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips my be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS 116 (7) (8) (6) (5) () 1IN 1IN OUT VCC (8) (3) (1) () 1OUT (5) (7) IN (6) IN () VCC CHIP THICKNESS: 15 TYPICAL BONDING PADS: MINIMUM (1) () (3) 1 TJmax = 15 C TOLERANCES ARE ±1%. ALL DIMENSIONS ARE IN MILS. POST OFFICE BOX DALLAS, TEXAS 7565

3 TLE37Y chip information ThIs chip, when properly assembled, displays characteristics similar to TLE37. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. The chip may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS 116 (7) (8) (6) (5) () 1IN 1IN OUT VCC (8) (3) (1) () 1OUT (5) (7) IN () (6) IN VCC CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: MILS MINIMUM TJmax = 15 C (1) () (3) TOLERANCES ARE ±1%. ALL DIMENSIONS ARE IN MILS. 1 POST OFFICE BOX DALLAS, TEXAS

4 POST OFFICE BOX DALLAS, TEXAS 7565 equivalent schematic (each amplifier) Q5 R1 R Q Q1 R R5 Q9 Q13 Q6 Q3 Q11 Q1 IN Q1 Q17 Q Q8 Q1 Q7 IN Q18 Q15 Q16 R3 C1 Q19 Q3 Q Q1 Q R6 V CC R9 R15 R Q Q7 Q36 Q6 Q3 R1 R8 R11 R16 Q38 Q3 Q39 R17 Q5 Q8 Q37 C3 Q R C R13 Q3 C Q7 Q Q3 Q1 Q33 Q6 Q9 Q5 Q31 Q35 Q R7 R1 R1 R1 R18 R19 V CC ACTUAL DEVICE COMPONENT COUNT R5 Q9 Q61 Q58 Q55 Q56 Q59 Q57 OUT Q5 Q8 Q5 Q6 Q53 Q5 Q51 Q6 R3 R R6 TLE7, TLE7Y, TLE37, TLE37Y Template Release Date: 7119 COMPONENT TLE7 TLE37 Transistors 6 6 Resistors Diodes Capacitors

5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note 1) V Supply voltage, V CC V Differential input voltage, V ID (see Note ) ±1. V Input voltage range, V I (any input) V CC± Input current, I I (each input) ±1 ma Output current, I O ±5 ma Total current into V CC ma Total current out of V CC ma Duration of short-circuit current at (or below) 5 C (see Note 3) unlimited Continuous total dissipation See Dissipation Rating Table Operating free-air temperature range, T A C to 7 C Lead temperature 1,6 mm (1/16 inch) from case for 1 seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC and VCC.. Differential voltages are at IN with respect to IN. Excessive current flows if a differential input voltage in excess of approximately ±1. V is applied between the inputs unless some limiting resistance is used. 3. The output can be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. PACKAGE DISSIPATION RATING TABLE TA 5 C POWER RATING DERATING FACTOR ABOVE TA = 7 C POWER RATING DW 15 mw 8. mw/ C 656 mw P 1 mw 8. mw/ C 6 mw recommended operating conditions MIN MAX UNIT Supply voltage, VCC ± ± ±19 V Common-mode mode input voltage, VIC ±11 TA = Full range ±1.5 V Operating free-air temperature, TA 7 C Full range is C to 7 C. POST OFFICE BOX DALLAS, TEXAS

6 electrical characteristics at specified free-air temperature, V CC± = ±15 V (unless otherwise noted) TLE7C PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VIO αvio IIO IIB Input offset voltage Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note ) Input offset current Input bias current VICR Common-mode mode input voltage range RS =5Ω Ω VOM VOM AVD Maximum positive peak output voltage swing Maximum negative peak output voltage swing 5 C 1 35 Full range 5 µv Full range. 1 µv/ C VIC =, RS = 5 Ω 5 C.6 1 µv/mo RL = 1 kω RL = kω RL =1kΩ RL =kω 5 C Full range 15 5 C 15 9 Full range 15 5 C 11 to Full range to C 1.5 Full range 1 5 C 1 Full range to 13 5 C Full range 1 5 C Full range 11 VO = ±11 V, 5 C.5 5 Large-signal differential voltage VO = ±1 V, Full range amplification 5 C VO = ±1 V, RL =1kΩ Full range 1 ci Input capacitance 5 C 8 pf zo Open-loop output impedance IO = 5 C 5 Ω CMRR Common-mode mode rejection ratio VIC = VICRmin, RS = 5 Ω 5 C Full range 95 Supply-voltage rejection VCC ± = ± V to ±18 V, RS = 5 Ω 5 C 9 1 ksvr ratio ( VCC ±/ VIO) VCC ± = ± V to ±18 V, RS = 5 Ω Full range 9 ICC Supply current VO =, No load 5 C Full range 11. Full range is C to 7 C. NOTE : Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated to using the Arrhenius equation and assuming an activation energy of.96 ev. na na V V V V/µV db db ma 6 POST OFFICE BOX DALLAS, TEXAS 7565

7 operating characteristics at specified free-air temperature, V CC± = ±15 V TLE7C PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT SR Slew rate, CL = 1 pf Vn Equivalent input noise voltage RS = Ω, RS = Ω, f = 1 Hz f = 1 khz 5 C Full range 1. 5 C V/µs nv/ HZ VN(PP) Peak-to-peak equivalent input noise voltage f=1hzto1hz C 5 5 nv In THD Equivalent input noise current Total harmonic distortion f = 1 Hz f = 1 khz VO = ±1 V, See Note 5 AVD = 1, 5 C 5 C <.% pa/ HZ B1 Unity-gain bandwidth, CL = 1 pf 5 C 7 13 MHz BOM Maximum output-swing bandwidth 5 C 3 khz φm Phase margin CL = 1 pf 5 C Full range is C to 7 C. NOTE 5: Measured distortion of the source used in the analysis is.%. POST OFFICE BOX DALLAS, TEXAS

8 electrical characteristics at specified free-air temperature, V CC± = ±15 V (unless otherwise noted) TLE37C PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VIO Input offset voltage 5 C 1 35 µv Full range 5 αvio Temperature coefficient of input offset voltage Full range. 1 IIO IIB Input offset voltage long-term drift (see Note ) Input offset current Input bias current VICR Common-mode mode input voltage range RS =5Ω Ω VOM VOM AVD Maximum positive peak output voltage swing Maximum negative peak output voltage swing Large-signal differential voltage amplification VIC =, RS =5Ω Ω RL =1kΩ RL =kω RL =1kΩ RL =kω µv/ C 5 C.6 1 µv/mo 5 C Full range 15 5 C 15 9 Full range 15 5 C 11 to Full range to C 1.5 Full range 1 5 C 1 Full range to 13 5 C Full range 1 5 C Full range 11 VO = ±11V, 5 C.5 5 VO = ±1 V, Full range 5 C VO = ±1 V, RL =1kΩ Full range 1 Ci Input capacitance 5 C 8 pf zo Open-loop output impedance IO = 5 C 5 Ω mode VIC = VICRmin, 5 C CMRR Common-mode rejection ratio db RS = 5 Ω Full range 95 ksvr Supply-voltage rejection ratio ( VCC ±/ VIO) VCC ± = ± V to ±18 V, RS = 5 Ω VCC ± = ± V to ±18 V, RS = 5 Ω ICC Supply current VO =, No load 5 C 9 1 Full range 9 5 C Full range 11. Full range is C to 7 C. NOTE. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated to using the Arrhenius equation and assuming an activation energy of.96 ev. na na V V V V/µV db ma 8 POST OFFICE BOX DALLAS, TEXAS 7565

9 operating characteristics at specified free-air temperature, V CC± = ±15 V TLE37C PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT AVD = 5,, 5 C 5 SR Slew rate, CL = 1 pf Full range 3 Vn Equivalent input noise voltage RS = Ω, RS = Ω, f = 1 Hz f = 1 khz 5 C V/µs nv/ Hz Vn(PP) Peak-to-peak equivalent input noise voltage f =.1 Hz to 1 Hz 5 C 5 5 nv In Equivalent input noise current f = 1 Hz f = 1 khz VO = ±1 V, AVD = 5 V, THD Total harmonic distortion See Note 5 GBP Gain-bandwidth product f = 1 khz, CL = 1 pf, 5 C 5 C <.% % pa/ Hz 5 C 35 5 MHz BOM Maximum output-swing bandwidth 5 C 8 khz φm Phase margin, CL = 1 pf 5 C Full range is C to 7 C. NOTE 5. Measured distortion of the source used in the analysis was.%. POST OFFICE BOX DALLAS, TEXAS

10 electrical characteristics, V CC± = ±15 V, T A = 5 C (unless otherwise noted) PARAMETER TEST CONDITIONS TLE7Y MIN TYP MAX VIO Input offset voltage 1 35 µv Input offset voltage long-term drift (see Note ).6 1 µv/mo VIC =, RS =5Ω Ω IIO Input offset current na IIB Input bias current 15 9 na VICR Common-mode input voltage range RS = 5 Ω 11 to 11 VOM Maximum positive peak output voltage swing RL = 1 kω VOM AVD Maximum negative peak output voltage swing Large-signal differential voltage amplification 13 to 13 RL = 1 kω VO = ±11 V,.5 5 VO = ±1 V, RL = 1 kω ci Input capacitance 8 pf zo Open-loop output impedance IO = 5 Ω CMRR Common-mode rejection ratio VIC = VICRmin, RS = 5 Ω db ksvr Supply-voltage rejection ratio ( VCC ±/ VIO) VCC ± = ± V to ±18 V, RS = 5 Ω 9 1 db ICC Supply current VO =, No load ma UNIT V V V V/µV NOTE. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated to using the Arrhenius equation and assuming an activation energy of.96 ev. operating characteristics, V CC± = ±15 V, T A = 5 C TLE7Y PARAMETER TEST CONDITIONS UNIT MIN TYP MAX SR Slew rate, CL = 1 pf V/µs Vn Equivalent input noise voltage RS = Ω, f = 1 Hz RS = Ω, f = 1 khz.5.5 nv/ HZ VN(PP) Peak-to-peak equivalent input noise voltage f=1hzto1hz nv In THD Equivalent input noise current Total harmonic distortion f = 1 Hz 1.5 f = 1 khz..6 pa/ HZ VO = ±1 V, See Note 5 AVD = 1, <.% B1 Unity-gain bandwidth, CL = 1 pf 7 13 MHz BOM Maximum output-swing bandwidth 3 khz φm Phase margin CL = 1 pf NOTE 5 Measured distortion of the source used in the analysis is.%. 1 POST OFFICE BOX DALLAS, TEXAS 7565

11 electrical characteristics at specified free-air temperature V CC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS TLE37Y MIN TYP MAX VIO Input offset voltage 1 35 µv Input offset voltage long-term drift (see Note ).6 1 µv/mo VIC =, RS =5Ω Ω IIO Input offset current na IIB Input bias current 15 9 na VICR Common-mode input voltage range RS = 5 Ω 11 to 11 VOM Maximum positive peak output voltage swing RL = 1 kω VOM AVD Maximum negative peak output voltage swing Large-signal differential voltage amplification 13 to 13 RL = 1 kω VO = ±11 V,.5 5 VO = ±1 V, RL = 1 kω Ci Input capacitance 8 pf zo Open-loop output impedance IO = 5 Ω CMRR Common-mode rejection ratio VIC = VICRmin, RS = 5 Ω db ksvr Supply-voltage rejection ratio ( VCC ±/ VIO) VCC ± = ± V to ±18 V, RS = 5 Ω 9 1 db ICC Supply current VO =, No load ma NOTE. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 15 C extrapolated to using the Arrhenius equation and assuming an activation energy of.96 ev. operating characteristics at specified free-air temperature V CC± = ±15 V PARAMETER TEST CONDITIONS TLE37Y MIN TYP MAX SR Slew rate, CL = 1 pf 5 V/µs Vn Equivalent input noise voltage UNIT V V V V/µV UNIT RS = Ω, f = 1 Hz RS = Ω, f = 1 khz.5.5 nv/ Hz Vn(PP) Peak-to-peak equivalent input noise voltage f =.1 Hz to 1 Hz 5 5 nv In Equivalent input noise current f = 1 Hz 1.5 f = 1 khz..6 pa/ Hz THD Total harmonic distortion VO = ±1 V, AVD = 1, See Note 5 <.% B1 Unity-gain bandwidth, CL = 1 pf 35 5 MHz BOM Maximum output-swing bandwidth 8 khz φm Phase margin, CL = 1 pf NOTE 5. Measured distortion of the source used in the analysis is.%. POST OFFICE BOX DALLAS, TEXAS

12 PARAMETER MEASUREMENT INFORMATION kω kω VI 15 V 15 V CL = 1 pf (see Note A) VO kω Ω 15 V 15 V Ω VO NOTE A: CL includes fixture capacitance. Figure 1. Slew-Rate Test Circuit Figure. Noise-Voltage Test Circuit 1 kω VI 1 Ω 15 V 15 V VO VO 15 V CL = 1 pf (see Note A) kω VI 15 V CL = 1 pf (see Note A) kω NOTE A: CL includes fixture capacitance. Figure 3. Unity-Gain Bandwidth and Phase-Margin Test Circuit NOTE A: CL includes fixture capacitance. Figure. Small-Signal Pulse- Response Test Circuit 1 POST OFFICE BOX DALLAS, TEXAS 7565

13 TYPICAL CHARACTERISTICS Table of Graphs VIO Input offset voltage Distribution 5 FIGURE VIO Input offset voltage change Time after power on 6, 7 IIO Input offset current Free-air temperature 8 IIB Input bias current Common-mode input voltage Free-air temperature II Input current Differential input voltage 11 VO(PP) Maximum peak-to-peak output voltage Frequency 1 VOM VOM AVD Maximum peak positive output voltage Maximum peak negative output voltage Large-signal differential voltage amplification Load resistance Free-air temperature Load resistance Free-air temperature Supply voltage Load resistance Frequency Free-air temperature ,, 1 zo Output impedance Frequency 3 CMRR Common-mode rejection ratio Frequency ksvr Supply-voltage rejection ratio Frequency 5 IOS ICC Short-circuit output current Supply current Supply voltage Elasped time Free-air temperature Supply voltage Free-air temperature 6, 7 8, 9 3, Voltage-follower small-signal pulse response Time 3, 35 Voltage-follower large-signal pulse response Time 36, 37 Vn Equivalent input noise voltage Frequency 38 B1 Noise voltage (referred to input) Over 1-second interval 39 Unity-gain bandwidth Supply voltage Load capacitance, 1, 3 SR Slew rate Free-air temperature, 5 φm Phase margin Supply voltage Load capacitance 6 7, 8 Phase shift Frequency 18,, 1 POST OFFICE BOX DALLAS, TEXAS

14 TYPICAL CHARACTERISTICS Percentage of Amplifiers % DISTRIBUTION OF INPUT OFFSET VOLTAGE ÎÎ 1568 Amplifiers Tested From Wafer Lots DW Package XVIO V IO Change In Input Offset Voltage uv µ V INPUT OFFSET VOLTAGE CHANGE TIME AFTER POWER ON VCC ± = ± 15 V ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ DW Package Sample Size = 5 Units VIO Input Offset Voltage µv t Time After Power On s 6 Figure 5 Figure 6 INPUT OFFSET VOLTAGE CHANGE TIME AFTER POWER ON INPUT OFFSET CURRENT FREE-AIR TEMPERATURE XVIO V Change In Input Offset Voltage µ uv IO ÎÎ ÎÎ P Package ÎÎ Sample Size = 5 Units ÎÎ From Wafer Lots t Time After Power On s IIO Input Offset Current na Î VIC = TA Free-Air Temperature C Figure 7 Figure 8 1 POST OFFICE BOX DALLAS, TEXAS 7565

15 TYPICAL CHARACTERISTICS 35 INPUT BIAS CURRENT COMMON-MODE INPUT VOLTAGE Î VIC = 16 INPUT BIAS CURRENT FREE-AIR TEMPERATURE IIB Input Bias Current na IIB Input Bias Current na VIC Common-Mode Input Voltage V TA Free-Air Temperature C Figure 9 Figure 1 II Input Current ma INPUT CURRENT DIFFERENTIAL INPUT VOLTAGE VIC = 1..6 Figure VID Differential Input Voltage V 1.8 V VO(PP) Maximum Peak-to-Peak Output Voltage V k MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE FREQUENCY 1 k Figure 1 1 M f Frequency Hz Î VCC ± = ± 15 V Î 1 M POST OFFICE BOX DALLAS, TEXAS

16 TYPICAL CHARACTERISTICS V VOM Maximum Positive Peak Output Voltage V MAXIMUM POSITIVE PEAK OUTPUT VOLTAGE LOAD RESISTANCE 1 k RL Load Resistance Ω 1 k V VOM Maximum Negative Peak Output Voltage V MAXIMUM NEGATIVE PEAK OUTPUT VOLTAGE LOAD RESISTANCE 1 k RL Load Resistance Ω 1 k Figure 13 Figure 1 VOM Maximum Positive Peak Output Voltage V V OM MAXIMUM POSITIVE PEAK OUTPUT VOLTAGE FREE-AIR TEMPERATURE 3 5 TA Free-Air Temperature C 6 7 VOM Maximum Negative Peak Output Voltage V V OM MAXIMUM NEGATIVE PEAK OUTPUT VOLTAGE FREE-AIR TEMPERATURE 3 5 TA Free-Air Temperature C 6 7 Figure 15 Figure POST OFFICE BOX DALLAS, TEXAS 7565

17 TYPICAL CHARACTERISTICS AVD A VD Large-Signal differential Voltage Amplification V/µ V ÁÁ ÁÁ LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION SUPPLY VOLTAGE RL = 1 kω VCC± Supply Voltage V Figure LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT FREQUENCY 75 1 Phase Shift 1 AVD A VD Large-Signal Differential Voltage Amplification db Á Á ÎÎÎ A VD CL = 1 pf 1 1 k f Frequency Hz M Phase Shift Figure 18 POST OFFICE BOX DALLAS, TEXAS

18 5 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION LOAD RESISTANCE ÁÁAVD Large-Signal differential Voltage Amplification V/µ V ÁÁ k k RL Load Resistance Ω Figure 19 1 k 6 TLE7 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT FREQUENCY AVD A VD Large-Signal Differential Voltage Amplification db ÁÁ Phase Shift CL = 1 pf ÎÎ A VD f Frequency MHz Phase Shift Figure 18 POST OFFICE BOX DALLAS, TEXAS 7565

19 TYPICAL CHARACTERISTICS 3 TLE37 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT FREQUENCY AVD Large-Signal Differential ÁÁAVD Voltage Amplification db CL = 1 pf Phase Shift ÎÎÎ AVD 1 f Frequency MHz Figure Phase Shift 6 LARGE-SCALE DIFFERENTIAL VOLTAGE AMPLIFICATION FREE-AIR TEMPERATURE 1 OUTPUT IMPEDANCE FREQUENCY AVD A VD Large-Signal Differential Voltage Amplification V/µ V ÁÁ ÁÁ RL = 1 kω zo Output Impedance O Ω AVD = 1 AVD = 1 AVD = TA Free-Air Temperature C k 1 k 1 k 1 M f Frequency Hz 1 M 1 M Figure Figure 3 POST OFFICE BOX DALLAS, TEXAS

20 TYPICAL CHARACTERISTICS CMRR Common-Mode Rejection Ratio db COMMON-MODE REJECTION RATIO FREQUENCY k XXXX SVR Supply-Voltage Rejection Ratio db SUPPLY-VOLTAGE REJECTION RATIO FREQUENCY ÎÎÎ ksvr ksvr Î Î k 1 k 1 k 1 M f Frequency Hz 1 M 1 M k 1 k 1 k 1 M f Frequency Hz 1 M 1 M Figure Figure 5 I IOS OS Short-Circuit Output Current ma SHORT-CIRCUIT OUTPUT CURRENT SUPPLY VOLTAGE Î VID = 1 mv VO = Î Î P Package VCC ± Supply Voltage V I IOS OS Short-Circuit Output Current ma SHORT-CIRCUIT OUTPUT CURRENT SUPPLY VOLTAGE Î VID = 1 mv VO = P Package VCC ± Supply Voltage V Figure 6 Figure 7 POST OFFICE BOX DALLAS, TEXAS 7565

21 TYPICAL CHARACTERISTICS I IOS OS Short-Circuit Output Current ma SHORT-CIRCUIT OUTPUT CURRENT ELAPSED TIME Î VID = 1 mv VO = P Package I IOS OS Short-Circuit Output Current ma SHORT-CIRCUIT OUTPUT CURRENT ELAPSED TIME VID = 1 mv VO = P Package t Time s Figure t Time s Figure I IOS Short-Circuit Output Current ma SHORT-CIRCUIT OUTPUT CURRENT FREE-AIR TEMPERATURE Î VID = 1 mv VO = P Package I IOS Short-Circuit Output Current ma SHORT-CIRCUIT OUTPUT CURRENT FREE-AIR TEMPERATURE VID = 1 mv VO = P Package TA Free-Air Temperature C TA Free-Air Temperature C 7 Figure 3 Figure 31 POST OFFICE BOX DALLAS, TEXAS

22 TYPICAL CHARACTERISTICS VO = No Load 1 8 SUPPLY CURRENT SUPPLY VOLTAGE TA = 7 C 8 Î VO = 7.8 No Load SUPPLY CURRENT FREE-AIR TEMPERATURE ICC Supply Current ma 6 ICC Supply Current ma VCC ± Supply Voltage V TA Free-Air Temperature C 7 Figure 3 Figure 33 V) Output Voltage mv V O TLE7 VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE 6 t Time ns Figure 3 Î Î CL = 1 pf Î See Figure 8 1 V) Output Voltage mv V O TLE37 VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE AVD = 5 CL = 1 pf 1 3 t Time ns Figure 35 POST OFFICE BOX DALLAS, TEXAS 7565

23 TYPICAL CHARACTERISTICS V) Output Voltage V V O Î Î CL = 1 pf Î Î See Figure TLE7 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE V) Output Voltage V V O Î AVD = 5 Î Î CL = 1 pf Î See Figure TLE37 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE t Time µs Figure t Time µs Figure 37 1 V Vn n Equivalent Input Noise Voltage nv/hz Hz EQUIVALENT INPUT NOISE VOLTAGE FREQUENCY RS = Ω See Figure Noise Voltage nv NOISE VOLTAGE (REFERRED TO INPUT) OVER A 1-SECOND INTERVAL f =.1 to 1 Hz k f Frequency Hz 1 k 1 k 5 6 t Time s 8 1 Figure 38 Figure 39 POST OFFICE BOX DALLAS, TEXAS

24 TYPICAL CHARACTERISTICS B1 B 1 Unity-Gain Bandwidth MHz CL = 1 pf See Figure 3 TLE7 UNITY-GAIN BANDWIDTH SUPPLY VOLTAGE B1 B 1 Unity-Gain Bandwidth MHz f = 1 khz CL = 1 pf TLE37 UNITY-GAIN BANDWIDTH SUPPLY VOLTAGE VCC ± Supply Voltage V Figure VCC ± Supply Voltage V Figure 1 18 B1 B 1 Unity-Gain Bandwidth MHz TLE7 UNITY-GAIN BANDWIDTH LOAD CAPACITANCE See Figure 3 B1 B 1 Unity-Gain Bandwidth MHz TLE37 UNITY-GAIN BANDWIDTH LOAD CAPACITANCE 1 1 CL Load Capacitance pf Figure CL Load Capacitance pf Figure 3 POST OFFICE BOX DALLAS, TEXAS 7565

25 TYPICAL CHARACTERISTICS SR Slew Rate V/us µ s AVD = 5 CL = 1 pf See Figure 1 TLE7 SLEW RATE FREE-AIR TEMPERATURE SR Slew Rate V/us µ s 8 Î Î AVD = 5 Î 7 CL = 1 pf Î See Figure TLE37 SLEW RATE FREE-AIR TEMPERATURE TA Free-Air Temperature C Figure TA Free-Air Temperature C Figure 5 7 om φ m Phase Margin CL = 1 pf See Figure 3 PHASE MARGIN SUPPLY VOLTAGE φ om m Phase Margin TLE7 PHASE MARGIN LOAD CAPACITANCE See Figure VCC ± Supply Voltage V Figure CL Load Capacitance pf Figure 7 POST OFFICE BOX DALLAS, TEXAS

26 TYPICAL CHARACTERISTICS 7 6 TLE37 PHASE MARGIN LOAD CAPACITANCE φ om m Phase Margin ÁÁ φ m CL Load Capacitance pf Figure 8 TLE7 macromodel information APPLICATION INFORMATION Macromodel information provided was derived using Microsim Parts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 6) and subcircuit in Figure 9 and Figure 5 are generated using the TLE7C typical electrical and operating characteristics at 5 C. Using this information, output simulations of the following key parameters can be generated to a tolerance of % (in most cases): Maximum positive output voltage swing Unity-gain bandwidth Maximum negative output voltage swing Common-mode rejection ratio Slew rate Phase margin Quiescent power dissipation DC output resistance Input bias current AC output resistance Open-loop voltage amplification Short-circuit output current limit NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, SC-9, 353 (197). PSpice and Parts are trademarks of MicroSim Corporation. Macromodels, simulation models, or other models provided by TI, directly or indirectly, are not warranted by TI as fully representing all of the specification and operating characteristics of the semiconductor product to which the model relates. 6 POST OFFICE BOX DALLAS, TEXAS 7565

27 TLE7 macromodel information (continued) TLE7, TLE7Y, TLE37, TLE37Y APPLICATION INFORMATION VCC IN IN VCC 1 rp dp rc1 11 Q1 13 re1 lee c1 3 rc 1 Q 1 re 1 ree ve 5 vc cee dc de r 53 egnd 9 vb 6 gcm 99 fb C ga ro 9 hlim 7 vlim 8 ro1 5 OUT dip dln 91 vip 9 vin Figure 9. Boyle Macromodel.subckt TLE * c E-1 c 6 7.E-1 dc 5 53 dx de 5 5 dx dlp 9 91 dx dln 9 9 dx dp 3 dx egnd 99 poly() (3,) (,).5.5 fb 7 99 poly(5) vb vc ve vlp vln 95.8E6 1E9 1E9 1E9 1E9 ga E-3 gcm E-1 iee 1 dc 56.1E-6 hlim 9 vlim 1K q qx q qx r E3 rc rc re re ree E6 ro ro rp E3 vb 9 dc vc 3 53 dc. ve 5 dc.1 vlim 7 8 dc vlp 91 dc vln 9 dc.model dx D(Is=8.E-18).model qx NPN(Is=8.E-18 Bf=7.E3).ends Figure 5. TLE7 Macromodel Subcircuit POST OFFICE BOX DALLAS, TEXAS

28 TLE37 macromodel information Macromodel information provided is derived using PSpice Parts model generation software. The Boyle macromodel (see Note 6) and subcircuit in Figure 51 and Figure 5 are generated using the TLE37C typical electrical and operating characteristics at 5 C. Using this information, output simulations of the following key parameters can be generated to a tolerance of % (in most cases): Maximum positive output voltage swing Unity-gain bandwidth Maximum negative output voltage swing Common-mode rejection ratio Slew rate Phase margin Quiescent power dissipation DC output resistance Input bias current AC output resistance Open-loop voltage amplification Short-circuit output current limit NOTE 6. G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, SC-9, 353 (197). VCC IN IN VCC 1 rp dp rc1 11 Q1 13 re1 lee c1 3 rc 1 Q 1 re 1 ree ve 5 vc cee dc de r 53 egnd 9 vb 6 gcm 99 fb C ga ro 9 hlim 7 vlim 8 ro1 5 OUT dlp dln 91 vlp 9 vln Figure 51. Boyle Macromodel Macromodels, simulation models, or other models provided by TI, directly or indirectly, are not warranted by TI as fully representing all of the specification and operating characteristics of the semiconductor product to which the model relates. 8 POST OFFICE BOX DALLAS, TEXAS 7565

29 TLE37 macromodel information (continued) TLE7, TLE7Y, TLE37, TLE37Y APPLICATION INFORMATION.subckt TLE * c E-1 c 6 7.E-1 dc 5 53 dx de 5 5 dx dlp 9 91 dx dln 9 9 dx dp 3 dx egnd 99 poly() (3,) (,).5.5 fb 7 99 poly(5) vb vc ve vlp vln 95.8E6 1E9 1E9 1E9 1E9 ga E-3 gcm E-1 iee 1 dc 56.1E-6 hlim 9 vlim 1K q qx q qx r E3 rc rc re re ree E6 ro ro rp E3 vb 9 dc vc 3 53 dc. ve 5 dc.1 vlim 7 8 dc vlp 91 dc vln 9 dc.model dx D(Is=8.E-18).model qx NPN(Is=8.E-18 Bf=7.E3).ends Figure 5. TLE37 Macromodel Subcircuit POST OFFICE BOX DALLAS, TEXAS

30 voltage-follower applications APPLICATION INFORMATION The TLEx7C circuitry includes input-protection diodes to limit the voltage across the input transistors; however, no provision is made in the circuit to limit the current if these diodes are forward biased. This condition can occur when the device is operated in the voltage-follower configuration and driven with a fast, large-signal pulse. A feedback resistor is recommended to limit the current to a maximum of 1 ma to prevent degradation of the device. Also, this feedback resistor forms a pole with the input capacitance of the device. For feedback resistor values greater than 1 kω, this pole degrades the amplifier s phase margin. This problem can be alleviated by adding a capacitor ( pf to 5 pf) in parallel with the feedback resistor (see Figure 53). CF = to 5 pf IF 1 ma RF VCC VO VI VCC Figure 53. Voltage-Follower Circuit 3 POST OFFICE BOX DALLAS, TEXAS 7565

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