AVAILABLE OPTIONS PACKAGED DEVICES CHIP CARRIER (FK) 100 µv TLC4502IDR. 50 µv TLC4502AIDR

Transcription

1 Power On Calibration of Input Offset Voltage Low Input Offset Voltage...< 5 µv Max (TLC5A) Low Input Offset Voltage Drift...< µv/ C Low Input Bias Current High Output Drive Capability C L < nf and R L > kω High Open Loop Gain...> db Rail-To-Rail Output Voltage Swing Low Distortion...<.% at khz Low Noise... nv/ Hz at khz High Slew Rate...5 V/µs Low Power Consumption... <.5 ma (Typical) Per Amplifier Short Calibration Time... ms Typ description The TLC5 self-calibrating operational amplifier utilizes the recent availability of on-chip digital and analog signal processing to automatically null the input offset voltage at power-up. This self-calibrating feature requires typically ms to complete and is repeatable to within ± µv on successive calibrations. The technique involves the extraction and digital storage of the key offset-nulling information. This information is retained without degradation as long as the circuit is powered. This eliminates the need for continuous chopping of the input signal to refresh the offset information. Once the process is complete, the bulk of the calibration circuitry drops out of the signal path and shuts down. This minimizes or eliminates any effect the calibration circuitry might have on the desired signal path. It also allows the TLC5 to be used exactly like any other operational amplifier after the calibration cycle is complete. The TLC5 is a high-performance operational amplifier fabricated in a -µm 5-V digital CMOS technology. It achieves very high dc gain, as well as excellent power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR). It uses a mixed-mode (analog/digital) internal compensation loop with digital storage of the offset information and a current-mode output to reduce its input offset to < 5 µv. The TLC5 also features a rail-to-rail output structure capable of driving loads to kω and nf. Unlike existing commercially available low-offset high-precision amplifiers, the TLC5 needs only a single 5-V supply, requires no trimming, and uses no bipolar transistors or JFETs. To achieve high dc gain, large bandwidth, high CMRR and PSRR, as well as good output drive capability, the TLC5 is built around a -stage topology: two gain stages, one rail-to-rail, and a class-ab output stage. A nested Miller topology is used for frequency compensation. TA VIOmax AT 5 C SMALL OUT- LINE (D) C to7 C C to85 C 55 C to5 C The D package is also available taped and reeled. AVAILABLE OPTIONS PACKAGED DEVICES CHIP CARRIER (FK) CERAMIC DIP (JG) CERAMIC FLAT PACK (U) 5 µv TLC5ACDR µv TLC5CDR 5 µv TLC5AIDR µv TLC5IDR 5 µv TLC5AMFKB TLC5AMJGB TLC5AMUB µv TLC5MFKB TLC5MJGB TLC5MUB CHIP FORM (Y) TLC5Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinEPIC and Self-Cal are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 997, Texas Instruments Incorporated POST OFFICE BOX 655 DALLAS, TEXAS 7565

2 D OR JG PACKAGE (TOP VIEW) FK PACKAGE (TOP VIEW) OUT IN IN V DD /GND NC OUT IN IN V DD /GND U PACKAGE (TOP VIEW) V DD OUT IN IN NC V DD OUT IN IN NC IN NC IN NC NC NC V DD /GND OUT NC NC IN V DD NC NC NC OUT NC IN NC NC No internal connection functional block diagram (during calibration) VDD POWER-ON RESET S R Q Q ENABLE RC OSCILLATOR COUNTER RCO CLOCK RESET SAR CAL DAC CORE AMPLIFIER LPF RCO POST OFFICE BOX 655 DALLAS, TEXAS 7565

3 description (continued) During the calibration procedure, the operational amplifier is removed from the signal path and both inputs are tied to GND. The class AB output stage features rail-to-rail voltage swing and incorporates additional switches to put the output node into a high-impedance mode during the calibration cycle. Small-replica output transistors (matched to the main output transistors) provide the amplifier output signal for the calibration circuit. The TLC5 also features built-in output short-circuit protection. The output current flowing through the main output transistors is continuously being sensed. If the current through either of these transistors exceeds the preset limit (6 ma 7 ma) for more than about µs, the output transistors are shut down to essentially their quiescent operating point for approximately 5 ms. The device is then returned to normal operation. If the short circuit is still in place, it is detected in less than µs and the device is shutdown for another 5 ms. The offset cancellation uses a current-mode digital-to-analog converter (DAC), whose full-scale current allows for an adjustment of approximately ± 5 mv to the input offset voltage. The digital code producing the cancellation current is stored in the successive-approximation register (SAR). During power up, when the offset cancellation procedure is initiated, an on-chip RC oscillator is activated to provide the timing of the successive-approximation algorithm. To prevent wide-band noise from interfering with the calibration procedure, an analog low-pass filter followed by a Schmidt trigger is used in the decision chain to implement an averaging process. Once the calibration procedure is complete, the RC oscillator is deactivated to reduce supply current and the associated noise. The key operational-amplifier parameters CMRR, PSRR, and offset drift were optimized to achieve superior offset performance. The TLC5 calibration DAC is implemented by a binary-weighted current array using a pseudo-r-r MOSFET ladder architecture, which minimizes the silicon area required for the calibration circuitry, and thereby reduces the cost of the TLC5. Due to the performance (precision, PSRR, CMRR, gain, output drive, and ac performance) of the TLC5, it is ideal for applications like: Data acquisition systems Medical equipment Portable digital scales Strain gauges Automotive sensors Digital audio circuits Industrial control applications It is also ideal in circuits like: A precision buffer for current-to-voltage converters, a/d buffers, or bridge applications High-impedance buffers or preamplifiers Long term integration Sample-and-hold circuits Peak detectors The TLC5 self-calibrating operational amplifier is manufactured using Texas instruments LinEPIC process technology and is available in an 8-pin SOIC (D) Package. The C-suffix devices are characterized for operation from C to 7 C. The I-suffix devices are characterized for operation from C to 85 C.The M-suffix devices are characterized for operation from 55 C to 5 C. POST OFFICE BOX 655 DALLAS, TEXAS 7565

4 TLC5Y chip information This chip, when properly assembled, display characteristics similar to the TLC5C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. This chip can be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS () () (8) (7) IN IN OUT VDD (8) () () () OUT (5) (7) IN (6) IN () 9 VDD /GND () (6) CHIP THICKNESS: 5 MILS TYPICAL BONDING PADS: MILS MINIMUM TJmax = 5 C TOLERANCES ARE ±%. () (5) 8 ALL DIMENSIONS ARE IN MILS. PIN () IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. POST OFFICE BOX 655 DALLAS, TEXAS 7565

5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V DD (see Note ) V Differential input voltage, V ID (see Note ) ±7 V Input voltage range, V I (any input, see Note ) V to 7 V Input current, I I (each input) ±5 ma Output current, I O (each output) ± ma Total current into V DD ± ma Total current out of V DD /GND ± ma Electrostatic discharge (ESD) > kv Duration of short-circuit current at (or below) 5 C (see Note ) unlimited Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, T A : TLC5C C to 7 C TLC5I C to 85 C TLC5M C to 5 C Storage temperature range, T stg C to 5 C Case temperature for 6 seconds, T C : FK package C Lead temperature,6 mm (/6 inch) from case for seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values, except differential voltages, are with respect to VDD /GND.. Differential voltages are at IN with respect to IN. Excessive current flows when an input is brought below VDD. V.. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. PACKAGE DISSIPATION RATING TABLE TA A 5 C DERATING FACTOR TA A = 7 C TA A = 85 C TA A = 5 C POWER RATING ABOVE TA = 5 C POWER RATING POWER RATING POWER RATING D FK 75 mw 75 mw 5.8 mw/ C. mw/ C JG 5 mw 8. mw/ C U 675 mw 5. mw/ C recommended operating conditions 6 mw 77 mw 88 mw 75 mw 75 mw 67 mw 56 mw mw mw 5 mw 5 mw TLC5C TLC5I TLC5M MIN MAX MIN MAX MIN MAX Supply voltage, VDD V Input voltage range, VI VDD VDD. VDD VDD. VDD VDD. V Common-mode input voltage, VIC VDD VDD. VDD VDD. VDD VDD. V Operating free-air temperature, TA C UNIT POST OFFICE BOX 655 DALLAS, TEXAS

6 electrical characteristics at specified free-air temperature, V DD = 5 V, GND = (unless otherwise noted) TLC5C TLC5AC PARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX Input offset 5 C 5 5 VIO voltage Full range 5 5 UNIT µv Temperature αvio coefficient of input Full range µv/ C offset voltage VDD = ±.5 V, VO =, VIC =, RS = 5 Ω Input offset 5 C IIO pa current Full range 5 5 IIB VOH VOL AVD RI(D) Input bias current 5 C Full range 5 5 IOH = 5 µa 5 C High-level l output t 5 C.9.9 V voltage IOH = 5 ma Full range.7.7 VIC =.5 V, IOL = 5 µa 5 C.. Low-level loutput t 5 C.. V voltage VIC =.5 V, IOL = 5 ma Full range.. Large-signal differential voltage amplification Differential input resistance VIC =.5 V, VO = V to V, RL = kω, See Note 5 C Full range pa V/mV 5 C kω RL Input resistance See Note 5 C Ω CL zo CMRR ksvr Common-mode input capacitance Closed-loop output impedance Common-mode rejection ratio Supply-voltage rejection ratio ( VDD ±/ VIO) IDD Supply current VO =5V.5 V, No load VIT(CAL) Calibration input threshold voltage Full range is C to 7 C. NOTE : RL and CL values are referenced to.5 V. f = khz, P package 5 C 8 8 pf AV =, f = khz 5 C Ω VIC = to.7 V, 5 C 9 9 VO = 5V.5 V, RS = kω Full range VDD = V to 6 V, 5 C 9 9 VIC =, No load Full range C Full range db db ma Full range V 6 POST OFFICE BOX 655 DALLAS, TEXAS 7565

7 electrical characteristics at specified free-air temperature, V DD = 5 V, GND = (unless otherwise noted) TLC5I TLC5AI PARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX Input offset 5 C 5 5 VIO voltage Full range 5 5 UNIT µv Temperature αvio coefficient of input Full range µv/ C offset voltage VDD = ±.5 V, VO =, VIC =, RS = 5 Ω Input offset 5 C IIO pa current Full range 5 5 IIB VOH VOL AVD RI(D) Input bias current 5 C Full range 5 5 IOH = 5 µa 5 C High-level l output t 5 C.9.9 V voltage IOH = 5 ma Full range.7.7 VIC =.5 V, IOL = 5 µa 5 C.. Low-level loutput t 5 C.. V voltage VIC =.5 V, IOL = 5 ma Full range.. Large-signal differential voltage amplification Differential input resistance VIC =.5 V, VO = V to V, RL = kω, See Note 5 C Full range pa V/mV 5 C kω RL Input resistance See Note 5 C Ω CL zo CMRR ksvr Common-mode input capacitance Closed-loop output impedance Common-mode rejection ratio Supply-voltage rejection ratio ( VDD ±/ VIO) IDD Supply current VO =5V.5 V, No load VIT(CAL) Calibration input threshold voltage Full range is C to 85 C. NOTE : RL and CL values are referenced to.5 V. f = khz, P package 5 C 8 8 pf AV =, f = khz 5 C Ω VIC = to.7 V, 5 C 9 9 VO = 5V.5 V, RS = kω Full range VDD = V to 6 V, 5 C 9 9 VIC =, No load Full range C Full range db db ma Full range V POST OFFICE BOX 655 DALLAS, TEXAS

8 electrical characteristics at specified free-air temperature, V DD = 5 V, GND = (unless otherwise noted) TLC5M TLC5AM PARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX Input offset 5 C 5 5 VIO voltage Full range 5 5 UNIT µv Temperature αvio coefficient of input Full range µv/ C offset voltage VDD = ±.5 V, VO =, VIC =, RS = 5 Ω Input offset 5 C IIO na current 5 C 5 5 IIB VOH VOL AVD RI(D) Input bias current 5 C 5 C IOH = 5 µa 5 C High-level l output t 5 C.9.9 V voltage IOH = 5 ma Full range.7.7 VIC =.5 V, IOL = 5 µa 5 C.. Low-level loutput t 5 C.. V voltage VIC =.5 V, IOL = 5 ma Full range.. Large-signal differential voltage amplification Differential input resistance VIC =.5 V, VO = V to V, RL = kω, See Note 5 C Full range na V/mV 5 C kω RL Input resistance See Note 5 C Ω CL zo CMRR ksvr Common-mode input capacitance Closed-loop output impedance Common-mode rejection ratio Supply-voltage rejection ratio ( VDD ±/ VIO) IDD Supply current VO =5V.5 V, No load VIT(CAL) Calibration input threshold voltage Full range is 55 C to 5 C. NOTE : RL and CL values are referenced to.5 V. f = khz, P package 5 C 8 8 pf AV =, f = khz 5 C Ω VIC = to.7 V, 5 C 9 9 VO = 5V.5 V, RS = kω Full range VDD = V to 6 V, 5 C 9 9 VIC = VDD /, No load Full range C Full range db db ma Full range V 8 POST OFFICE BOX 655 DALLAS, TEXAS 7565

9 operating characteristics, V DD = 5 V TLC5C, TLC5AC PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT SR Slew rate at unity gain VO =5Vto5V.5.5 V, CL = pf Vn VN(PP) Equivalent input noise voltage 5 C.5.5 V/µs Full range V/µs f = Hz 5 C 7 f = khz 5 C Peak-to-peak equivalent input noise f =. to Hz 5 C voltage f =. to Hz 5 C.5 nv/ Hz In Equivalent input noise current 5 C.6 fa/ Hz THD N BOM ts Total harmonic distortion plus noise Gain-bandwidth product Maximum output swing bandwidth Settling time VO =.5 V to.5 V, AV = 5 C.% f = khz, = AV = 5 C.8% RL kω, CL = pf AV = 5 C.55% f = khz, CL = pf VO(PP) = V, RL = kω, AV =, Step =.5 V to.5 V, RL = kω, CL = pf RL = kω, AV =, CL = pf µv 5 C.7 MHz 5 C MHz to.% 5 C.6 to.% 5 C. φm Phase margin at unity gain RL = kω, CL = pf 5 C 7 Calibration time 5 C ms Full range is C to 7 C. NOTE : RL and CL values are referenced to.5 V. µs POST OFFICE BOX 655 DALLAS, TEXAS

10 operating characteristics, V DD = 5 V TLC5I, TLC5AI PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT SR Slew rate at unity gain VO =5Vto5V.5.5 V, CL = pf Vn VN(PP) Equivalent input noise voltage 5 C.5.5 V/µs Full range V/µs f = Hz 5 C 7 f = khz 5 C Peak-to-peak equivalent input noise f =. to Hz 5 C voltage f =. to Hz 5 C.5 nv/ Hz In Equivalent input noise current 5 C.6 fa/ Hz THD N BOM ts Total harmonic distortion plus noise Gain-bandwidth product Maximum output swing bandwidth Settling time VO =.5 V to.5 V, AV = 5 C.% f = khz, = AV = 5 C.8% RL kω, CL = pf AV = 5 C.55% f = khz, CL = pf VO(PP) = V, RL = kω, AV =, Step =.5 V to.5 V, RL = kω, CL = pf RL = kω, AV =, CL = pf µv 5 C.7 MHz 5 C MHz to.% 5 C.6 to.% 5 C. φm Phase margin at unity gain RL = kω, CL = pf 5 C 7 Calibration time 5 C ms Full range is C to 85 C. NOTE : RL and CL values are referenced to.5 V. µs POST OFFICE BOX 655 DALLAS, TEXAS 7565

11 operating characteristics, V DD = 5 V TLC5M, PARAMETER TEST CONDITIONS TA TLC5AM UNIT MIN TYP MAX VO =.5 V to.5 V, CL = pf 5 C.5.5 V/µs SR Slew rate at unity gain See Note Full range V/µs Vn VN(PP) Equivalent input noise voltage f = Hz 5 C 7 f = khz 5 C Peak-to-peak equivalent input noise f =. to Hz 5 C voltage f =. to Hz 5 C.5 nv/ Hz In Equivalent input noise current 5 C.6 fa/ Hz THD N BOM ts Total harmonic distortion plus noise Gain-bandwidth product Maximum output swing bandwidth Settling time VO =.5 V to.5 V, AV = 5 C.% f = khz, = AV = 5 C.8% RL kω, CL = pf AV = 5 C.55% f = khz, CL = pf VO(PP) = V, RL = kω, AV =, Step =.5 V to.5 V, RL = kω, CL = pf RL = kω, AV =, CL = pf µv 5 C.7 MHz 5 C MHz to.% 5 C.6 to.% 5 C. φm Phase margin at unity gain RL = kω, CL = pf 5 C 7 Calibration time 5 C ms Full range is 55 C to 5 C. NOTE : RL and CL values are referenced to.5 V. µs POST OFFICE BOX 655 DALLAS, TEXAS 7565

12 electrical characteristics at specified free-air temperature, V DD = 5 V, GND =, T A = 5 C (unless otherwise noted) VIO IIO IIB VOH VOL AVD Input offset voltage Input offset current Input bias current PARAMETER High-level output voltage Low-level output voltage Large-signal differential voltage amplification TEST CONDITIONS VDD = ±.5 5V, VO =, VIC =, RS = 5 Ω TLC5Y MIN TYP MAX IOH = 5 µa.99 IOH = 5 ma.9 VIC =.5 V, IOL = 5 µa. VIC =.5 V, IOL = 5 ma. VIC =.5 V, RL = kω, VO = V to V, See Note UNIT µv pa pa V V V/mV RI(D) Differential input resistance kω RL Input resistance See Note Ω CL Common-mode input capacitance f = khz, P package 8 pf zo Closed-loop output impedance AV =, f = khz Ω CMRR ksvr Common-mode rejection ratio Supply-voltage rejection ratio ( VDD ±/ VIO) VIC = to.7 V, RS = kω VDD = ± V to ± V, No load VO =.5 V, VIC =, db db IDD Supply current VO =.5 V, No load.5 ma NOTE : RL and CL values are referenced to.5 V. operating characteristics, V DD = 5 V, T A = 5 C PARAMETER TEST CONDITIONS TLC5Y MIN TYP MAX SR Slew rate at unity gain VO =.5 V to.5 V, CL = pf.5 V/µs Vn VN(PP) Equivalent input noise voltage Peak-to-peak equivalent input noise voltage f = Hz 7 f = khz f =. to Hz f =. to Hz.5 UNIT nv/ Hz In Equivalent input noise current.6 fa/ Hz THD N BOM ts Total harmonic distortion plus noise Gain-bandwidth product Maximum output swing bandwidth Settling time VO =.5 V to.5 V, AV =.% f = khz, = AV =.8% RL kω, CL = pf AV =.55% f = khz, CL = pf VO(PP) = V, RL = kω, AV =, Step =.5 V to.5 V, RL = kω, CL = pf RL = kω, AV =, CL = pf to.%.6 to.%. φm Phase margin at unity gain RL = kω, CL = pf 7 µv.7 MHz MHz Calibration time ms NOTE : RL and CL values are referenced to.5 V. µs POST OFFICE BOX 655 DALLAS, TEXAS 7565

13 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution,, Common-mode input voltage αvio Input offset voltage temperature coefficient Distribution 5, 6 VOH High-level output voltage High-level output current 7 VOL Low-level output voltage Low-level output current 8 VO(PP) Maximum peak-to-peak output voltage Frequency 9 IOS Short-circuit output current Free-air temperature VO Output voltage Differential input voltage AVD Large-signal differential voltage amplification Free-air temperature Frequency zo Output impedance Frequency CMRR Common-mode mode rejection ratio Frequency 5 Free-air temperature 6 SR Slew rate Load capacitance 7 Free-air temperature 8 Inverting large-signal pulse response Time 9 Voltage-follower large-signal pulse response Time Inverting small-signal pulse response Time Voltage-follower small-signal pulse response Time Vn Equivalent input noise voltage Frequency Input noise voltage Over a -second period THD N Total harmonic distortion plus noise Frequency 5 Gain-bandwidth product Free-air temperature 6 φm Phase margin Load capacitance 7 Frequency Gain margin Load capacitance 8 PSRR Power-supply rejection ratio Free-air temperature 9 Calibration time at C Time Calibration time at 5 C Time Calibration time at 85 C Time Calibration time at 5 C Time POST OFFICE BOX 655 DALLAS, TEXAS 7565

14 TYPICAL CHARACTERISTICS Percentage Of Amplification % DISTRIBUTION OF TLC5 INPUT OFFSET VOLTAGE 9 Amplifier From Wafer Lot VDD = ±.5 V TA = C Percentage of Amplifiers % 8 6 DISTRIBUTION OF TLC5 INPUT OFFSET VOLTAGE 86 Amplifier From 8 Wafer Lot VDD = ±.5 V TA = 5 C VIO Input Offset Voltage µv 6 5 VIO Input Offset Voltage µv 5 6 Figure Figure Percentage Of Amplification % DISTRIBUTION OF TLC5 INPUT OFFSET VOLTAGE 96 Amplifier From Wafer Lot VDD = ±.5 V TA = 85 C V IO Input Offset Voltage µ V INPUT OFFSET VOLTAGE COMMON-MODE INPUT VOLTAGE VDD = ±.5 V RS = 5 Ω TA = 5 C 5 5 VIO Input Offset Voltage µv VIC Common-Mode Input Voltage v Figure Figure 5 POST OFFICE BOX 655 DALLAS, TEXAS 7565

15 TYPICAL CHARACTERISTICS Percentage Of Amplifiers % DISTRIBUTION OF TLC5 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT Amplifiers From Wafer Lot VDD = ±.5 V P PACKAGE TA = 5 C To C Percentage Of Amplifiers % DISTRIBUTION OF TLC5 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT Amplifiers From Wafer Lot VDD = ±.5 V P PACKAGE TA = 5 C To 85 C α VIO Temperature Coefficient µv/ C Figure Figure α VIO Temperature Coefficient µv/ C V VOH High-Level Output Voltage V ÁÁ HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT TA = 5 C TA = C TA = 5 C IOH High-Level Output Current ma Figure 7 TA = 85 C VDD = 5 V VIC =.5 V Low-Level Output Voltage V V OL LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT VDD = 5 V VIC =.5 V TA = 85 C TA = 5 C TA = 5 C 5 IOL Low-Level Output Current ma Figure 8 TA = C POST OFFICE BOX 655 DALLAS, TEXAS

16 TYPICAL CHARACTERISTICS Maximum Peak-To-Peak Output Voltage V V O(PP) 8 6 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE FREQUENCY VDD = 5 V k k k M M f Frequency Hz Short-Circuit Output Current ma I OS SHORT-CIRCUIT OUTPUT CURRENT FREE-AIR TEMPERATURE IOS IOS TA Free-Air Temperature C 5 75 Figure 9 Figure V O Output Voltage V OUTPUT VOLTAGE DIFFERENTIAL INPUT VOLTAGE VDD = 5 V VIC =.5 V RL = kω TA = 5 C A VD Large-Signal Differential Voltage Amplification V/mV LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION FREE-AIR TEMPERATURE RL = kω VID Differential Input Voltage mv Figure TA Free-Air Temperature C Figure 6 POST OFFICE BOX 655 DALLAS, TEXAS 7565

17 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE MARGIN FREQUENCY Large-Signal Differential A VD Voltage Amplification db 8 6 VDD = 5 V RL = kω CL = pf TA = 5 C Phase Margin k 9 k k M M M f Frequency Hz Figure OUTPUT IMPEDANCE FREQUENCY z O Output Impedance Ω... AV = AV = AV = k k k M f Frequency Hz Figure POST OFFICE BOX 655 DALLAS, TEXAS

18 TYPICAL CHARACTERISTICS CMRR Common-Mode Rejection Ratio db COMMON-MODE REJECTION RATIO FREQUENCY VDD = 5 V VIC =.5 V TA = 5 C CMRR Common-Mode Rejection Ratio db COMMON-MODE REJECTION RATIO FREE-AIR TEMPERATURE VDD = 5 V k k k M M f Frequency Hz TA Free-Air Temperature C Figure 5 Figure 6 µ s SR Slew Rate V/ 6 5 SLEW RATE LOAD CAPACITANCE SR SR V/µ s SR Slew Rate 8 6 VDD = 5 V RL = kω CL = pf AV = SLEW RATE FREE-AIR TEMPERATURE SR SR k k k CL Load Capacitance pf Figure TA Free-Air Temperature C Figure POST OFFICE BOX 655 DALLAS, TEXAS 7565

19 TYPICAL CHARACTERISTICS.5 INVERTING LARGE-SIGNAL PULSE RESPONSE.5 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE V O Output Voltage V.5.5 VDD = 5 V.5 RL = kω CL = pf AV = TA = 5 C t Time µs 5 75 V O Output Voltage V VDD = 5 V RL = kω CL = pf AV = TA = 5 C t Time µs 5 75 Figure 9 Figure INVERTING SMALL-SIGNAL PULSE RESPONSE VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE V O Output Voltage V VDD = 5 V RL = kω CL = pf AV = TA 5 C V O Output Voltage V VDD = 5 V RL = kω CL = pf AV = TA = 5 C t Time µs t Time µs 5 Figure Figure POST OFFICE BOX 655 DALLAS, TEXAS

20 TYPICAL CHARACTERISTICS VN Vn Equivalent Input Noise Voltage nv/ nv//hz Hz EQUIVALENT INPUT NOISE VOLTAGE FREQUENCY VDD = 5 V RS = Ω TA = 5 C k f Frequency Hz Figure k k Input Noise Voltage nv INPUT NOISE VOLTAGE OVER A -SECOND PERIOD VDD = 5 V f =. Hz To Hz TA = 5 C 5 6 t Time s Figure THDN Total Harmonic Distortion Plus Noise %. TOTAL HARMONIC DISTORTION PLUS NOISE FREQUENCY VDD = 5 V RL = kω TIED.5 V AV = AV = AV =. k k k f Frequency Hz Gain-Bandwidth Product MHz GAIN-BANDWIDTH PRODUCT FREE-AIR TEMPERATURE VDD = 5 V F = khz RL = kω CL = pf TA Free-Air Temperature C Figure 5 Figure 6 POST OFFICE BOX 655 DALLAS, TEXAS 7565

21 TYPICAL CHARACTERISTICS 9 PHASE MARGIN LOAD CAPACITANCE TA 5 C GAIN MARGIN LOAD CAPACITANCE 75 Rnull = 5 Ω 5 Phase Margin kω Rnull = Rnull = Ω Gain Margin db 5 Rnull = 5 Ω Rnull = Ω 5 VI 5 kω VDD R null CL 5 Rnull = VDD k k k CL Load Capacitance pf k k k CL Load Capacitance pf Figure 7 Figure 8 POWER SUPPLY REJECTION RATIO FREE-AIR TEMPERATURE CALIBRATION TIME AT C PSRR Power Supply Rejection Ratio db VDD = V To 6 V VIC = VO = VDD/ TA Free-Air Temperature C V O Output Voltage V t Time ms VDD =.5 V GND =.5 V RL = kω to GND AV = VI = Figure 9 Figure POST OFFICE BOX 655 DALLAS, TEXAS 7565

22 TYPICAL CHARACTERISTICS.5 CALIBRATION TIME AT 5 C.5 CALIBRATION TIME AT 85 C V O Output Voltage V VDD =.5 V GND =.5 V RL = kω to GND AV = VI = V O Output Voltage V VDD =.5 V GND =.5 V RL = kω to GND AV = VI = 5 6 t Time ms t Time ms Figure Figure.5 CALIBRATION TIME AT 5 C V O Output Voltage V t Time ms VDD =.5 V GND =.5 V RL = kω to GND AV = VI = Figure POST OFFICE BOX 655 DALLAS, TEXAS 7565

23 APPLICATION INFORMATION The TLC5 is designed to operate with only a single 5-V power supply, have true differential inputs, and remain in the linear mode with an input common-mode voltage of. The TLC5 has a standard dual-amplifier pinout allowing for easy design upgrades. Large differential input voltages can be easily accommodated and, as input differential-voltage protection diodes are not needed, no large input currents result from large differential input voltage. Protection should be provided to prevent the input voltages from going negative more than. V at 5 C. An input clamp diode with a resistor to the device input terminal can be used for this purpose. For ac applications, where the load is capacitively coupled to the output of the amplifier, a resistor can be used from the output of the amplifier to ground. This increases the class-a bias current and prevents crossover distortion. Where the load is directly coupled, for example dc applications, there is no crossover distortion. Capacitive loads, which are applied directly to the output of the amplifier, reduce the loop stability margin. Values of 5 pf can be accommodated using the worst-case noninverting unity-gain connection. Resistive isolation should be considered when larger load capacitance must be driven by the amplifier. The following typical application circuits emphasize operation on only a single power supply. When complementary power supplies are available, the TLC5 can be used in all of the standard operational amplifier circuits. In general, introducing a pseudo-ground (a bias voltage of V I / like that generated by the TLE6) allows operation above and below this value in a single-supply system. Many application circuits are shown which take advantage of the wide common-mode input-voltage range of the TLC5, which includes ground. In most cases, input biasing is not required and input voltages that range to ground can easily be accommodated. POST OFFICE BOX 655 DALLAS, TEXAS 7565

24 APPLICATION INFORMATION V(REF) V(REF) R 9 kω R 9 kω R kω R kω R5 9 kω R6 9 kω Gain = Gain = Gain = Gain = VDD 8. pf 6 VI RP kω / TLC5 5 / TLC5 7 VO VO RP VI kω (Gain ) V O. VI V I.. R6 R R5. V (REF) Where R R6, R R5, and R R (Gain ) V O. VI V I.. R5 R6. V R (REF) Where R R6, R R5, and R R RP < kω Figure. Single-Supply Programmable Instrumentation Amplifier Circuit VI RP < kω / TLC5 R 5 6 / TLC5 R 7 VO R RG V(REF) R V O V I *. R R..R R G.* V (REF) Where : R R and R R Figure 5. Two Operational-Amplifier Instrumentation Amplifier Circuit POST OFFICE BOX 655 DALLAS, TEXAS 7565

25 APPLICATION INFORMATION / TLC5 R R5 R VI RG R / TLC5 VO 6 5 / TLC5 7 R R6 V(REF) V O V I. R5 R..R R G. V (REF) Where : R R, R R, and R5 R6 Figure 6. Three Operational-Amplifier Instrumentation Amplifier Circuit VI R R R / TLC5 R5 I I R Figure 7. Fixed Current-Source Circuit POST OFFICE BOX 655 DALLAS, TEXAS

26 APPLICATION INFORMATION / TLC5 VO VI V I V O Figure 8. Voltage-Follower Circuit VI / TLC5 ma Ω β 6 ma Figure 9. Lamp-Driver Circuit / TLC5 RL Ω Figure. TTL-Driver Circuit 6 POST OFFICE BOX 655 DALLAS, TEXAS 7565

27 APPLICATION INFORMATION IO VI / TLC5 I O V I R E RE Figure. High-Compliance Current-Sink Circuit VI V(REF) R kω / TLC5 VO R MΩ Figure. Comparator With Hysteresis Circuit IB 6 / TLC5 IB 5 / TLC5 7 ZO VO VI ZI C µf Figure. Low-Drift Detector Circuit POST OFFICE BOX 655 DALLAS, TEXAS

28 D (R-PDSO-G**) PIN SHOWN MECHANICAL INFORMATION PLASTIC SMALL-OUTLINE PACKAGE.5 (,7). (,5). (,5) 8. (,5) M PINS ** DIM A MAX A MIN 8.97 (5,).89 (,8). (8,75).7 (8,55) 6.9 (,).86 (9,8).57 (,).5 (,8). (6,).8 (5,8).8 (,) NOM 7 Gage Plane A. (,5) 8. (,).6 (,) Seating Plane.69 (,75) MAX. (,5). (,). (,) 7/ D /96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed.6 (,5). D. Falls within JEDEC MS- 8 POST OFFICE BOX 655 DALLAS, TEXAS 7565

29 FK (S-CQCC-N**) 8 TERMINAL SHOWN MECHANICAL INFORMATION LEADLESS CERAMIC CHIP CARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX 9. (8,69).58 (9,9).7 (7,8).58 (9,9) A SQ B SQ (,).6 (6,6).79 (8,78).98 (,8). (8,99).58 (,6).66 (6,76).76 (9,).96 (,).65 (9,59).6 (,).95 (,58).95 (,58).85 (,6).7 (6,6).58 (,6).56 (,).56 (,).858 (,8).6 (7,). (,5). (,5).8 (,).6 (,6). (,5). (,5).55 (,).5 (,).5 (,).5 (,89).8 (,7). (,5).5 (,7).5 (,).5 (,89) / D /96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS- POST OFFICE BOX 655 DALLAS, TEXAS

30 JG (R-GDIP-T8) MECHANICAL INFORMATION CERAMIC DUAL-IN-LINE PACKAGE. (,).55 (9,) (7,).5 (6,).65 (,65).5 (,). (,5) MIN. (7,87).9 (7,7). (5,8) MAX Seating Plane. (,) MIN.6 (,6).5 (,8). (,5). (,58).5 (,8). (,6).8 (,) 5 7/C 8/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. E. Falls within MIL-STD-85 GDIP-T8 POST OFFICE BOX 655 DALLAS, TEXAS 7565

31 U (S-GDFP-F) MECHANICAL INFORMATION CERAMIC DUAL FLATPACK.5 (6,5).6 (6,).8 (,).5 (,7).6 (,5). (,).5 (,).6 (,66).5 (8,89).5 (6,5). (7,6).5 (8,89).5 (6,5).9 (,8).5 (,8).5 (,7).5 (6,5) 5 6. (5,).75 (9,5).5 (,6).5 (,) 79/ B /95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only. E. Falls within MIL STD 85 GDFP-F and JEDEC MO-9AA POST OFFICE BOX 655 DALLAS, TEXAS 7565

32 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ( Critical Applications ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 997, Texas Instruments Incorporated