TLC254, TLC254A, TLC254B, TLC254Y, TLC25L4, TLC25L4A, TLC25L4B TLC25L4Y, TLC25M4, TLC25M4A, TLC25M4B, TLC25M4Y LinCMOS QUAD OPERATIONAL AMPLIFIERS

Transcription

1 A-Suffix ersions Offer 5-m IO TLC254, TLC254A, TLC254B, TLC254Y, TLC25L4, TLC25L4A, TLC25L4B B-Suffix ersions Offer 2-m IO Wide Range of Supply oltages True Single-Supply Operation Common-Mode Input oltage Includes the Negative Rail Low Noise n/ Hz Typ at f = 1 khz (High-Bias ersion) description The TLC254, TLC254A, TLC254B, TLC25L4, symbol (each amplifier) TLC254L4A, TLC254L4B, TLC25M4, TLC25M4A and TL25M4B are low-cost, low-power quad IN + + operational amplifiers designed operate with OUT single or dual supplies. These devices utilize the IN Texas Instruments silicon gate LinCMOS process, giving them stable input-offset voltages that are available in selected grades of 2, 5, or 10 m maximum, very high input impedances, and extremely low input offset and bias currents. Because the input common-mode range extends the negative rail and the power consumption is extremely low, this series is ideally suited for battery-powered or energy-conserving applications. The series offers operation down a 1.4- supply, is stable at unity gain, and has excellent noise characteristics. These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures at voltages up 2000 as tested under MIL-STD-883C, Method However, care should be exercised in handling these devices as exposure ESD may result in degradation of the device parametric performance. Because of the extremely high input impedance and low input bias and offset currents, applications for these devices include many areas that have previously been limited BIFET and NFET product types. Any circuit using high-impedance elements and requiring small offset errors is a good candidate for cost-effective use of these devices. Many features associated with bipolar technology are available with LinCMOS operational amplifiers without the power penalties of traditional bipolar devices. TA IOmax AT 25 C SMALL OUTLINE (D) Available options PACKAGED DEICES PLASTIC DIP (N) D, N, OR PW PACKAGE (TOP IEW) 1OUT 1IN 1IN+ DD 2IN+ 2IN 2OUT TSSOP (PW) CHIP FORM (Y) 10 m TLC254CD TLC254CN TLC254CPW TLC254Y 5 m TLC254ACD TLC254ACN 2 m TLC254BCD TLC254BCN 10 m TLC25L4CD TLC25L4CN TLC25L4CPW TLC25L4Y 0 C 70 C 5 m TLC25L4ACD TLC25L4ACN 2 m TLC25L2BCD TLC25L4BCN 10 m TLC25M4CD TLC25M4CN TLC25M4CPW TLC25M4Y 5 m TLC25M4ACD TLC25M4ACN 2 m TLC25M4BCD TLC25M4BCN The D package is available taped and reeled. Add the suffix R the device type (e.g., TLC254CDR). Chips are tested at 25 C OUT 4IN 4IN+ DD /GND 3IN+ 2IN 3OUT LinCMOS is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1994, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 description (continued) General applications such as transducer interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are all easily designed with these devices. Remote and inaccessible equipment applications are possible using their low-voltage and low-power capabilities. These devices are well suited solve the difficult problems associated with single-battery and solar-cell-powered applications. This series includes devices that are characterized for the commercial temperature range and are available in 14-pin plastic dip and the small-outline packages. The device is also available in chip form. These devices are characterized for operation from 0 C 70 C. DEICE FEATURES PARAMETER TLC25L4_C (LOW BIAS) TLC25M4_C (MEDIUM BIAS) TLC254_C (HIGH BIAS) Supply current (Typ) 40 µa 600 µa 4000 µa Slew rate (Typ) 0.04 /µa 0.6 /µa 4.5 /µa Input offset voltage (Max) TLC254C, TLC25L4C, TLC25M4C TLC254AC, TLC25L4AC, TLC25M4AC TLC254BC, TLC25L4BC, TLC25M4BC 10 m 5 m 2 m 10 m 5 m 2 m 10 m 5 m 2 m Offset voltage drift (Typ) 0.1 µ/month 0.1 µ/month 0.1 µ/month Offset voltage temperature coefficient (Typ) 0.7 µ/ C 2 µ/ C 5 µ/ C Input bias current (Typ) Input offset current (Typ) The long-term drift value applies after the first month. equivalent schematic (each amplifier) DD IN + ESD- Protective Network IN ESD- Protective Network OUT DD /GND 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 chip information These chips, when properly assembled, display characteristics similar the TLC25_4C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS 68 (14) (13) (12) (11) (10) (9) (8) 1IN+ 1IN 2OUT 3IN+ 3IN 4OUT DD (4) (3) + (1) (2) 1OUT (5) + (7) 2IN+ (10) (9) (14) + + (6) (8) (12) (13) (11) 2IN 3OUT 4IN+ 4IN DD /GND (1) (2) (3) (4) (5) (6) (7) CHIP THICKNESS: 15 TYPICAL 108 BONDING PADS: 4 4 MINIMUM TJmax = 150 C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. PIN (11) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. POST OFFICE BOX DALLAS, TEXAS

4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, DD (see Note 1) Differential input voltage (see Note 2) ± 18 Input voltage range (any input) Duration of short-circuit at (or below) 25 C free-air temperature (see Note 3) unlimited Continuous tal dissipation See Dissipation Rating Table Operating free-air temperature range C 70 C Srage temperature range C 150 C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect DD /GND. 2. Differential voltages are at IN+, with respect IN. 3. The output may be shorted either supply. Temperature and/or supply voltages must be limited ensure the maximum dissipation rating is not exceeded. PACKAGE DISSIPATION RATING TABLE TA 25 C DERATING FACTOR TA = 70 C POWER RATING ABOE TA = 25 C POWER RATING D 725 mw 5.8 mw/ C 464 mw N 1050 mw 9.2 mw/ C 736 mw PW 700 mw 5.6 mw/ C 448 mw recommended operating conditions MIN MAX Supply voltage, DD DD = Common-mode mode input voltage, IC DD = 5 4 DD = 10 9 DD = Operating free-air temperature, TA 0 70 C 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 electrical characteristics at specified free-air temperature, DD = 1.4 (unless otherwise noted) POST OFFICE BOX DALLAS, TEXAS PARAMETER TEST CONDITIONS TA TLC25_4C IO Input offset voltage TLC25_4AC O =02 0.2, RS =50Ω Ω aio TLC25_4BC Average temperature coefficient of 25 C input offset voltage 70 C IIO Input offset current O = 0.2 IIB Input bias current O = 0.2 ICR Common-mode input voltage range 25 C TLC254_C TLC25L4_C TLC25M4_C 25 C C 70 C C C 70 C C C 70 C m µ/ C 25 C C 70 C C C 70 C OM Peak output voltage swing ID = 100 m 25 C m AD CMRR Large-signal differential voltage amplification Common-mode rejection ratio O = m, RS = 50 Ω O = 0.2, IC = ICRmin C /m 25 C db IDD Supply current O = 0.2, No load 25 C µa All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Unless otherwise noted, an output load resisr is connected from the output ground and has the following value: for low bias, RL = 1 MΩ, for medium bias RL = 100 kω, and for high bias RL = 10 kω. The output swings the potential of DD /GND. operating characteristics, DD = 1.4, T A = 25 C PARAMETER TEST CONDITIONS TLC254_C TLC25L4_C TLC25M4_C SR Slew rate at unity gain /µs B1 Unity-gain bandwidth A = 40 db, RS = 50 Ω, CL = 10 pf, khz Overshoot facr 30% 35% 35% TLC254, TLC254A, TLC254B, TLC254Y, TLC25L4, TLC25L4A, TLC25L4B TM LinCMOS QUAD OPERATIONAL AMPLIFIERS

6 electrical characteristics at specified free-air temperature, DD = 5 (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC254BC TLC254, TLC254AC, O = 1.4, IC = 0, 25 C TLC254C RS = 50 Ω, RL = 10 kω Full range 12 = 1.4, IC = 0, 25 C IO Input offset voltage TLC254AC O RS = 50 Ω, RL = 10 kω Full range 6.5 = 1.4, IC = 0, 25 C TLC254BC O RS = 50 Ω, RL = 10 kω Full range 3 m αio Average temperature coefficient of input 25 C offset voltage 70 C IIO Input offset current (see Note 4) O = 2.5, IC = 2.5 IIB Input bias current (see Note 4) O =25 2.5, IC = 2.5 ICR Common-mode input voltage range (see Note 5) 25 C µ/ C 70 C C C C Full range C OH High-level output voltage ID = 100 m, RL = 10 kω 25 C C C 0 50 OL Low-level output voltage ID = 100 m, IOL = 0 25 C 0 50 m AD Large-signal differential voltage amplification 70 C C 4 27 O = , RL = 10 kω 25 C 5 23 /m 70 C C CMRR Common-mode rejection ratio IC = ICRmin 25 C db 70 C C ksr Supply-voltage rejection ratio ( DD/ IO) DD = 5 10, O = C db IDD Supply current (four amplifiers) O = 2.5, IC = 2.5, No load 70 C C C ma 70 C Full range is 0 C 70 C. NOTES: 4. The typical values of input bias current and input offset current below 5 were determined mathematically. 5. This range also applies each input individually. POST OFFICE BOX DALLAS, TEXAS

7 electrical characteristics at specified free-air temperature, DD = 10 (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC254BC TLC254C, TLC254AC, O = 1.4, IC = 0, 25 C TLC254C RS = 50 Ω, RL = 10 kω Full range 12 O = 1.4, IC = 0, 25 C IO Input offset voltage TLC254AC O RS = 50 Ω, RL = 10 kω Full range 6.5 IO O = 1.4, IC = 0, 25 C TLC254BC RS = 50 Ω, RL = 10 kω Full range 3 Average temperature coefficient of input 25 C offset voltage 70 C IIO Input offset current (see Note 4) O = 5, IC = 5 IIB Input bias current (see Note 4) O =5, IC =5 ICR Common-mode input voltage range (see Note 5) 25 C 0.1 m 2 µ/ C 70 C C C C Full range C OH High-level output voltage ID = 100 m, RL = 10 kω 25 C C C 0 50 OL Low-level output voltage ID = 100 m, IOL = 0 25 C 0 50 m AD Large-signal differential voltage amplification 70 C C O = 1 6, RL = 10 kω 25 C /m 70 C C CMRR Common-mode rejection ratio IC = ICRmin 25 C db ksr IDD Supply-voltage lt rejection ratio ( DD/ IO) Supply current (four amplifiers) 70 C C DD = 5 10, O = C db O = 5, IC = 5, No load 70 C C C ma 70 C Full range is 0 C 70 C. NOTES: 4. The typical values of input bias current and input offset current below 5 were determined mathematically. 5. This range also applies each input individually. 8 POST OFFICE BOX DALLAS, TEXAS 75265

8 operating characteristics, DD = 5 TLC254, TLC254A, TLC254B, TLC254Y, TLC25L4, TLC25L4A, TLC25L4B PARAMETER TEST CONDITIONS TA I(PP) =1 TLC254C, TLC254AC, TLC254BC 0 C 4 25 C 3.6 RL = 10 kω, I(PP) = 1 70 C 3 SR Slew rate at unity gain L, L 0 C 3.1 I(PP) = C C 2.5 n Equivalent input noise voltage f = 1 khz, RS = 20 Ω, See Figure 2 25 C 25 n/ Hz BOM Maximum output-swing bandwidth O = OH, RL = 10 kω, 0 C 340 /µs 25 C 320 khz 70 C C 2 B1 Unity-gain bandwidth I = 10 m, 25 C 1.7 MHz φm Phase margin I = 10 m, f = B1, See Figure 3 70 C C C C 43 operating characteristics, DD = 10 PARAMETER TEST CONDITIONS TA RL = 10 kω, SR Slew rate at unity gain, TLC254C, TLC254AC, TLC254BC 0 C 5.9 I(PP) ( = 1 25 C C C 5.1 I(PP) ( = C C 3.8 n Equivalent input noise voltage f = 1 khz, RS = 20 Ω, See Figure 2 25 C 25 n/ Hz BOM Maximum output-swing bandwidth O = OH, RL = 10 kω, 0 C 220 /µs 25 C 200 khz 70 C C 2.5 B1 Unity-gain bandwidth I = 10 m, 25 C 2.2 MHz φm Phase margin I = 10 m, f = B1, See Figure 3 70 C C C C 46 POST OFFICE BOX DALLAS, TEXAS

9 electrical characteristics at specified free-air temperature, DD = 5 (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC25L4C TLC25L4AC TLC25L4BC O = 1.4, IC = 0, 25 C TLC25L4C O RS = 50 Ω, RL = 1 MΩ Full range 12 = 1.4, IC = 0, 25 C IO Input offset voltage TLC25L4AC O RS = 50 Ω, RL = 1 MΩ Full range 6.5 = 1.4, IC = 0, 25 C TLC25L4BC O RS = 50 Ω, RL = 1 MΩ Full range 3 m IO Average temperature coefficient of input 25 C offset voltage 70 C IIO Input offset current (see Note 4) O = 2.5, IC = 2.5 IIB Input bias current (see Note 4) O =25 2.5, IC = ICR Common-mode input voltage range (see Note 5) 25 C µ/ C 70 C C C C Full range C OH High-level output voltage ID = 100 m, RL = 1 MΩ 25 C C C 0 50 OL Low-level output voltage ID = 100 m, IOL = 0 25 C 0 50 m AD Large-signal differential voltage amplification 70 C C O = , RL = 1 MΩ 25 C /m 70 C C CMRR Common-mode rejection ratio IC = ICRmin 25 C db ksr IDD Supply-voltage lt rejection ratio ( DD/ IO) Supply current (four amplifiers) 70 C C DD = 5 10, O = C db O = 2.5, IC = 2.5, No load 70 C C C µa 70 C Full range is 0 C 70 C. NOTES: 4. The typical values of input bias current and input offset current below 5 were determined mathematically. 5. This range also applies each input individually. 10 POST OFFICE BOX DALLAS, TEXAS 75265

10 electrical characteristics at specified free-air temperature, DD = 10 (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC25L4C TLC25L4AC TLC25L4BC O = 1.4, IC = 0, 25 C TLC25L4C O RS = 50 Ω, RL = 1 MΩ Full range 12 = 1.4, IC = 0, 25 C IO Input offset voltage TLC25L4AC O RS = 50 Ω, RL = 1 MΩ Full range 6.5 αio = 1.4, IC = 0, 25 C TLC25L4BC O RS = 50 Ω, RL = 1 MΩ Full range 3 Average temperature coefficient of 25 C input offset voltage 70 C IIO Input offset current (see Note 4) O = 5, IC = 5 IIB Input bias current (see Note 4) O =5, IC =5 =.5 ICR Common-mode input voltage range (see Note 5) 25 C 0.1 m 1 µ/ C 70 C C C C Full range C OH High-level output voltage ID = 100 m, RL = 1 MΩ 25 C C C 0 50 OL Low-level output voltage ID = 100 m, IOL = 0 25 C 0 50 m AD Large-signal differential voltage amplification 70 C C O = 1 6, RL = 1 MΩ 25 C /m 70 C C CMRR Common-mode rejection ratio IC = ICRmin 25 C db ksr IDD Supply-voltage lt rejection ratio ( DD/ IO) Supply current (four amplifiers) 70 C C DD = 5 10, O = C db O = 5, IC = 5, No load 70 C C C µa 70 C Full range is 0 C 70 C. NOTES: 4. The typical values of input bias current and input offset current below 5 were determined mathematically. 5. This range also applies each input individually. POST OFFICE BOX DALLAS, TEXAS

11 operating characteristics, DD = 5 PARAMETER TEST CONDITIONS TA TLC25L4C TLC25L4AC TLC25L4BC 0 C 0.04 RL = 1 MΩ, SR Slew rate at unity gain, I(PP) = 1 25 C C C 0.03 I(PP) ( = C C 0.02 n Equivalent input noise voltage f = 1 khz, RS = 20 Ω, See Figure 2 25 C 70 n/ Hz BOM Maximum output-swing bandwidth O = OH, RL = 1 MΩ, 0 C 6 /µs 25 C 5 khz 70 C C 100 B1 Unity-gain bandwidth I = 10 m, 25 C 85 khz φm Phase margin I = 10 m, f = B1, See Figure 3 70 C 65 0 C C C 30 operating characteristics, DD = 10 PARAMETER TEST CONDITIONS TA TLC25L4C TLC25L4AC TLC25L4BC 0 C 0.05 RL = 1 MΩ, SR Slew rate at unity gain, I(PP) = 1 25 C C C 0.05 I(PP) ( = C C 0.04 n Equivalent input noise voltage f = 1 khz, RS = 20 Ω, See Figure 2 25 C 70 n/ Hz BOM Maximum output-swing bandwidth O = OH, RL = 1 MΩ, 0 C 1.3 /µs 25 C 1 khz 70 C C 125 B1 Unity-gain bandwidth I = 10 m, 25 C 110 khz φm Phase margin I = 10 m, f = B1, See Figure 3 70 C 90 0 C C C POST OFFICE BOX DALLAS, TEXAS 75265

12 electrical characteristics at specified free-air temperature, DD = 5 (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC25M4C TLC25M4AC TLC25M4BC O = 1.4, IC = 0, 25 C TLC25M4C O RS = 50 Ω, RL = 100 kω Full range 12 O = 1.4, IC = 0, 25 C IO Input offset voltage TLC25M4AC RS = 50 Ω, RL = 100 kω Full range 6.5 IO O = 1.4, IC = 0, 25 C TLC25M4BC RS = 50 Ω, RL = 100 kω Full range 3 Average temperature coefficient of 25 C input offset voltage 70 C IIO Input offset current (see Note 4) O = 2.5, IC = 2.5 IIB Input bias current (see Note 4) O =25 2.5, IC = ICR Common-mode input voltage range (see Note 5) 25 C 0.1 m µ/ C 70 C C C C Full range t C OH High-level output voltage ID = 100 m, RL = 100 kω 25 C C C 0 50 OL Low-level output voltage ID = 100 m, IOL = 0 25 C 0 50 m AD Large-signal differential voltage amplification 70 C C O = , RL = 100 kω 25 C /m 70 C C CMRR Common-mode rejection ratio IC = ICRmin 25 C db ksr IDD Supply-voltage lt rejection ratio ( DD/ IO) Supply current (four amplifiers) 70 C C DD = 5 10, O = C db O = 2.5, IC = 2.5, No load 70 C C C µa 70 C Full range is 0 C 70 C. NOTES: 4. The typical values of input bias current and input offset current below 5 were determined mathematically. 5. This range also applies each input individually. POST OFFICE BOX DALLAS, TEXAS

13 electrical characteristics at specified free-air temperature, DD = 10 (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC25M4C TLC25M4AC TLC25M4BC O = 1.4, IC = 0, 25 C TLC25M4C O RS = 50 Ω, RL = 100 kω Full range 12 = 1.4, IC = 0, 25 C IO Input offset voltage TLC25M4AC O RS = 50 Ω, RL = 100 kω Full range 6.5 αio = 1.4, IC = 0, 25 C TLC25M4BC O RS = 50 Ω, RL = 100 kω Full range 3 Average temperature coefficient of input 25 C offset voltage 70 C IIO Input offset current (see Note 4) O = 5, IC = 5 IIB Input bias current (see Note 4) O =5, IC =5 ICR Common-mode input voltage range (see Note 5) 25 C 0.1 m µ/ C 70 C C C C Full range C OH High-level output voltage ID = 100 m, RL = 100 kω 25 C C C 0 50 OL Low-level output voltage ID = 100 m, IOL = 0 25 C 0 50 m AD Large-signal differential voltage amplification 70 C C O = 1 6, RL = 100 kω 25 C /m 70 C C CMRR Common-mode rejection ratio IC = ICRmin 25 C db 70 C C ksr Supply-voltage rejection ratio ( DD/ IO) DD = 5 10, O = C db IDD Supply current (four amplifiers) O = 5, IC = 5, No load 70 C C C µa 70 C Full range is 0 C 70 C. NOTES: 4. The typical values of input bias current and input offset current below 5 were determined mathematically. 5. This range also applies each input individually. 14 POST OFFICE BOX DALLAS, TEXAS 75265

14 operating characteristics, DD = 5 TLC254, TLC254A, TLC254B, TLC254Y, TLC25L4, TLC25L4A, TLC25L4B PARAMETER TEST CONDITIONS TA TLC25M4C TLC25M4AC TLC25M4BC 0 C 0.46 /µs I(PP) = 1 25 C 0.43 /µs RL = 100 kω, 70 C 0.36 SR Slew rate at unity gain, 0 C 0.43 I(PP) ( = C C 0.34 n Equivalent input noise voltage f = 1 khz, RS = 20 Ω, See Figure 2 25 C 32 n/ Hz BOM Maximum output-swing bandwidth O = OH, RL = 100 kω, 0 C 60 /µs 25 C 55 khz 70 C 50 0 C 610 B1 Unity-gain bandwidth I = 10 m, 25 C 525 khz φm Phase margin I = 10 m, f = B1, See Figure 3 70 C C C C 39 operating characteristics, DD = 10 PARAMETER TEST CONDITIONS TA TLC25M4C TLC25M4AC TLC25M4BC 0 C 0.67 RL = 100 kω, SR Slew rate at unity gain, I(PP) = 1 25 C C C 0.61 I(PP) ( = C C 0.46 n Equivalent input noise voltage f = 1 khz, RS = 20 Ω, See Figure 2 25 C 32 n/ Hz BOM Maximum output-swing bandwidth O = OH, RL = 100 kω, 0 C 40 /µs 25 C 35 khz 70 C 30 0 C 710 B1 Unity-gain bandwidth I = 10 m, 25 C 635 khz φm Phase margin I = 10 m, f = B1, See Figure 3 70 C C C C 42 POST OFFICE BOX DALLAS, TEXAS

15 electrical characteristics, DD = 5, T A = 25 C (unless otherwise noted) IO αio IIO IIB ICR OH OL AD CMRR ksr IDD NOTES: PARAMETER Input offset voltage Average temperature coefficient of input offset voltage Input offset current (see Note 4) Input bias current (see Note 4) Common-mode input voltage range (see Note 5) High-level output voltage Low-level output voltage Large-signal differential voltage amplification Common-mode rejection ratio Supply-voltage rejection ratio ( DD/ IO) TEST TLC254Y TLC25L4Y TLC25M4Y CONDITIONS O = 1.4, IC = 0, RS = 50 Ω, See Note 6 O = DD/2, IC = DD/2 O = DD/2, IC = DD/2 ID = 100 m, RL = 100 kω ID = 100 m, IOL = 0 O = 0.25, See Note m µ/ C m /m IC = ICRmin db DD = 5 10, O = db Supply current O = DD/2, IC = DD/2, No load ma 4. The typical values of input bias current and input offset current below 5 were determined mathematically. 5. This range also applies each input individually. 6. For low-bias mode, RL = 1 MΩ, for medium-bias mode, RL = 100 kω, and for high-bias mode, RL = 10 kω. operating characteristics, DD = 5, T A = 25 C SR n BOM B1 φm NOTE 6: PARAMETER TEST CONDITIONS TLC254Y TLC25L4Y TLC25M4Y Slew rate at CL L = 20 pf, I(PP) = unity gain See Note 6 I(PP) = Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth Phase margin /µs f = 1 khz, RS = 20 Ω n/ Hz O = OH, RL = 10 kω khz I = 10 m, CL = 20 pf MHz f = B1, CL = 20 pf I = 10 m, For low-bias mode, RL = 1 MΩ, for medium-bias mode, RL = 100 kω, and for high-bias mode, RL = 10 kω. 16 POST OFFICE BOX DALLAS, TEXAS 75265

16 PARAMETER MEASUREMENT INFORMATION single-supply versus split-supply test circuits Because the TLC25_4, TLC25_4A, and TLC25_4B are optimized for single-supply operation, circuit configurations used for the various tests often present some inconvenience since the input signal, in many cases, must be offset from ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives the same result. DD DD + I + O I + O CL RL CL RL (a) SINGLE-SUPPLY DD (b) SPLIT-SUPPLY Figure 1. Unity-Gain Amplifier 2 kω 2 kω DD DD + 1/2 DD 20 Ω 20 Ω + O + O 20 Ω 20 Ω DD (a) SINGLE-SUPPLY (b) SPLIT-SUPPLY Figure 2. Noise-Test Circuit 10 kω 10 kω DD DD + I 1/2 DD 100Ω + CL O I 100Ω + CL O DD (a) SINGLE-SUPPLY (b) SPLIT-SUPPLY Figure 3. Gain-of-100 Inverting Amplifier POST OFFICE BOX DALLAS, TEXAS

17 TYPICAL CHARACTERISTICS Table of Graphs FIGURE IDD Supply current vs Supply voltage 4 vs Free-air temperature 5 Low bias vs Frequency 6 AD Large-signal differential voltage amplification Medium bias vs Frequency 7 High bias vs Frequency 8 Low bias vs Frequency 6 Phase shift Medium bias vs Frequency 7 High bias vs Frequency 8 SUPPLY CURRENT vs SUPPLY OLTAGE SUPPLY CURRENT vs FREE-AIR TEMPERATURE I ICC DD Supply Current µ xa A O = IC = 0.2 DD No Load TA = 25 C High-Bias ersions Medium-Bias ersions Low-Bias ersions I ICC DD Supply Current µ xa A High-Bias ersions Medium-Bias ersions Low-Bias ersions DD = 10 IC = 0 O = 2 No Load DD Supply oltage TA Free-Air Temperature C Figure 4 Figure 5 18 POST OFFICE BOX DALLAS, TEXAS 75265

18 AD A D Low-Bias Large-Signal Differential oltage Amplification ÁÁ ÁÁ AD Medium-Bias Large-Signal Differential oltage Amplification ÁÁ TYPICAL CHARACTERISTICS LOW-BIAS LARGE-SIGNAL DIFFERENTIAL OLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY Phase Shift (right scale) AD (left scale) DD = 10 RL = 1 MΩ TA = 25 C k 10 k 100 k Frequency Hz Figure 6 MEDIUM-BIAS LARGE-SIGNAL DIFFERENTIAL OLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY Phase Shift (right scale) AD (left scale) k 10 k 100 k 1 M Frequency Hz Figure 7 DD = 10 RL = 100 kω TA = 25 C Phase Shift Phase Shift POST OFFICE BOX DALLAS, TEXAS

19 TYPICAL CHARACTERISTICS AD High-Bias Large-Signal Differential oltage Amplification ÁÁ HIGH-BIAS LARGE-SIGNAL DIFFERENTIAL OLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY AD (left scale) DD = 10 RL = 10 kω TA = 25 C Phase Shift (right scale) Phase Shift k 10 k 100 k 1 M 10 M Frequency Hz Figure 8 20 POST OFFICE BOX DALLAS, TEXAS 75265

20 APPLICATION INFORMATION latch-up avoidance Junction-isolated CMOS circuits have an inherent parasitic PNPN structure that can function as an SCR. Under certain conditions, this SCR may be triggered in a low-impedance state, resulting in excessive supply current. To avoid such conditions, no voltage greater than 0.3 beyond the supply rails should be applied any pin. In general, the operational amplifiers supplies should be established simultaneously with, or before, application of any input signals. output stage considerations The amplifier s output stage consists of a source-follower-connected pullup transisr and an open-drain pulldown transisr. The high-level output voltage ( OH ) is virtually independent of the I DD selection and increases with higher values of DD and reduced output loading. The low-level output voltage ( OL ) decreases with reduced output current and higher input common-mode voltage. With no load, OL is essentially equal the potential of DD /GND. supply configurations Even though the TLC25_4C series is are characterized for single-supply operation, they can be used effectively in a split-supply configuration if the input common-mode voltage ( ICR ), output swing ( OL and OH ), and supply voltage limits are not exceeded. circuit layout precautions Whenever extremely high circuit impedances are used, care must be exercised in layout, construction, board cleanliness, and supply filtering avoid hum and noise pickup as well as excessive dc leakages. POST OFFICE BOX DALLAS, TEXAS

21 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right make changes their products or discontinue any product or service without notice, and advise cusmers obtain the latest version of relevant information verify, before placing orders, that information being relied on is current and complete. All products are sold subject the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconducr products the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized the extent TI deems necessary support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INOLE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEERE PROPERTY OR ENIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order minimize risks associated with the cusmer s applications, adequate design and operating safeguards must be provided by the cusmer minimize inherent or procedural hazards. TI assumes no liability for applications assistance or cusmer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating any combination, machine, or process in which such semiconducr products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated