TLC274, TLC274A, TLC274B, TLC274Y, TLC279 LinCMOS PRECISION QUAD OPERATIONAL AMPLIFIERS

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1 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 Trimmed Offset Voltage: TLC µv Max at 25 C, V DD = 5 V Input Offset Voltage Drift...Typically. µv/month, Including the First 3 Days Wide Range of Supply Voltages Over Specified Temperature Range: C 7 C...3 V 6 V 4 C 85 C...4 V 6 V 55 C 25 C...4 V 6 V Single-Supply Operation Common-Mode Input Voltage Range Extends Below the Negative Rail (C-Suffix and I-Suffix Versions) Low Noise...Typically 25 nv/ Hz at f = khz Output Voltage Range Includes Negative Rail High Input Impedance... 2 Ω Typ ESD-Protection Circuitry Small-Outline Package Option Also Available in Tape and Reel Designed-In Latch-Up Immunity description The TLC274 and TLC279 quad operational amplifiers combine a wide range of input offset voltage grades with low offset voltage drift, high input impedance, low noise, and speeds approaching that of general-purpose BiFET devices. These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset voltage stability far exceeding the stability available with conventional metal-gate processes. The extremely high input impedance, low bias currents, and high slew rates make these cost-effective devices ideal for applications which have previously been reserved for BiFET and NFET products. Four offset voltage grades are available (C-suffix and I-suffix types), ranging from the low-cost TLC274 ( µv) the highprecision TLC279 (9 µv). These advantages, in combination with good common-mode rejection and supply voltage rejection, make these devices a good choice for new state-of-the-art designs as well as for upgrading existing designs. LinCMOS is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Percentage of Units % IN NC V DD NC 2IN D, J, N, OR PW PACKAGE (TOP VIEW) OUT IN IN V DD 2IN 2IN 2OUT FK PACKAGE (TOP VIEW) IN OUT NC IN 2OUT NC 4OUT 4IN 3OUT 3IN NC No internal connection 4OUT 4IN 4IN GND 3IN 3IN 3OUT 4IN NC GND NC 3IN DISTRIBUTION OF TLC279 INPUT OFFSET VOLTAGE 29 Units Tested From 2 Wafer Lots N Package 6 6 VIO Input Offset Voltage µv 2 Copyright 994, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS 75265

2 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 description (continued) In general, many features associated with bipolar technology are available on LinCMOS operational amplifiers, without the power penalties of bipolar technology. General applications such as transducer interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC274 and TLC279. The devices also exhibit low voltage single-supply operation, making them ideally suited for remote and inaccessible battery-powered applications. The common-mode input voltage range includes the negative rail. A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density system applications. The device inputs and outputs are designed withstand -ma surge currents without sustaining latch-up. The TLC274 and TLC279 incorporate internal ESD-protection circuits that prevent functional failures at voltages up 2 V as tested under MIL-STD-883C, Method 35.2; however, care should be exercised in handling these devices as exposure ESD may result in the degradation of the device parametric performance. The C-suffix devices are characterized for operation from C 7 C. The I-suffix devices are characterized for operation from 4 C 85 C. The M-suffix devices are characterized for operation over the full military temperature range of 55 C 25 C. TA C 7 C 4 C 85 C 55 C 25 C VIOmax AT 25 C 9 µv 2 mv 5 mv mv SMALL OUTLINE (D) TLC279CD TLC274BCD TLC274ACD TLC274CD AVAILABLE OPTIONS CHIP CARRIER (FK) PACKAGED DEVICES CERAMIC DIP (J) PLASTIC DIP (N) TLC279CN TLC274BCN TLC274ACN TLC274CN TSSOP (PW) TLC274CPW CHIP FORM (Y) TLC274Y 9 µv TLC279ID TLC279IN 2 mv TLC274BID TLC274BIN 5 mv TLC274AID TLC274AIN mv TLC274ID TLC274IN 9 µv mv TLC279MD TLC274MD TLC279MFK TLC274MFK TLC279MJ TLC274MJ TLC279MN TLC274MN The D package is available taped and reeled. Add R suffix the device type (e.g., TLC279CDR). 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 equivalent schematic (each amplifier) VDD SLOS92B SEPTEMBER 987 REVISED AUGUST 994 P3 P4 R6 IN R R2 N5 P5 P6 IN P P2 R5 C OUT N3 N N2 R3 D R4 D2 N4 N6 R7 N7 GND POST OFFICE BOX DALLAS, TEXAS

4 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 TLC274Y chip information These chips, when properly assembled, display characteristics similar the TLC274C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS 68 (4) (3) (2) () () (9) (8) () (2) (3) (4) (5) (6) (7) IN IN 2OUT 3IN 3IN 4OUT VDD (3) (4) () (2) OUT (5) (7) 2IN () (6) 2IN (8) (9) 3OUT (2) (4) 4IN (3) 4IN GND 8 CHIP THICKNESS: 5 TYPICAL BONDING PADS: 4 4 MINIMUM TJmax = 5 C TOLERANCES ARE ±%. ALL DIMENSIONS ARE IN MILS. PIN () IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V DD (see Note ) V Differential input voltage, V ID (see Note 2) ±V DD Input voltage range, V I (any input) V V DD Input current, I I ±5 ma Output current, l O (each output) ±3 ma Total current in V DD ma Total current out of GND ma Duration of short-circuit current at (or below) 25 C (see Note 3) unlimited Continuous tal dissipation See Dissipation Rating Table Operating free-air temperature, T A : C suffix C 7 C I suffix C 85 C M suffix C 25 C Srage temperature range C 5 C Case temperature for 6 seconds: FK package C Lead temperature,6 mm (/6 inch) from case for seconds: D, N, or PW package C Lead temperature,6 mm (/6 inch) from case for 6 seconds: J package C Stresses beyond those listed under absolute maximum ratings may cause permanent damage the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values, except differential voltages, are with respect network ground. 2. Differential voltages are at the noninverting input with respect the inverting input. 3. The output may be shorted either supply. Temperature and/or supply voltages must be limited ensure that the maximum dissipation rating is not exceeded (see application section). PACKAGE TA 25 C POWER RATING DISSIPATION RATING TABLE DERATING FACTOR ABOVE TA = 7 C POWER RATING TA = 85 C POWER RATING TA = 25 C POWER RATING D 95 mw 7.6 mw/ C 68 mw 494 mw FK 375 mw. mw/ C 88 mw 75 mw 275 mw J 375 mw. mw/ C 88 mw 75 mw 275 mw N 575 mw 2.6 mw/ C 8 mw 89 mw PW 7 mw 5.6 mw/ C 448 mw recommended operating conditions C SUFFIX I SUFFIX M SUFFIX UNIT MIN MAX MIN MAX MIN MAX Supply voltage, VDD V Common-mode mode input voltage, VIC V VDD = V Operating free-air temperature, TA C POST OFFICE BOX DALLAS, TEXAS

6 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 electrical characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted) VIO αvio PARAMETER TEST CONDITIONS TA TLC274BC, TLC279C TLC274C, TLC274AC, MIN TYP MAX VO =.4 V, VIC =, 25 C. TLC274C RS = 5 Ω, RL = kω Full range 2 Input offset voltage Average temperature coefficient of input offset voltage V =.4 V, VIC =, 25 C.9 5 TLC274AC O RS = 5 Ω, RL = kω Full range 6.5 V =.4 V, VIC =, 25 C 34 2 TLC274BC O RS = 5 Ω, RL = kω Full range 3 VO =.4 V, VIC =, 25 C 32 9 TLC279C RS = 5 Ω, RL = kω Full range 5 IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V IIB Input bias current (see Note 4) VO =25V 2.5 V, VIC =25V 2.5 VICR Common-mode input voltage range (see Note 5) 25 C 7 C 25 C. UNIT mv µv.8 µv/ C 7 C C.6 7 C C Full range C VOH High-level output voltage VID = mv, RL = kω C V 7 C C 5 VOL Low-level output voltage VID = mv, IOL = C 5 mv AVD Large-signal differential voltage amplification 7 C 5 25 C 5 23 VO =.25 V 2 V, RL = kω C 4 27 V/mV 7 C C 65 8 CMRR Common-mode rejection ratio VIC = VICRmin C 6 84 db ksvr IDD Supply-voltage lt rejection ratio ( VDD / VIO) Supply current (four amplifiers) 7 C C V, VO =.4 V C 6 94 db VO = 2.5 V, VIC = 2.5 V, No load 7 C C pa pa C ma 7 C Full range is C 7 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 electrical characteristics at specified free-air temperature, V DD = V (unless otherwise noted) VIO αvio PARAMETER TEST CONDITIONS TA A TLC274BC, TLC279C TLC274C, TLC274AC, MIN TYP MAX VO =.4 V, VIC =, 25 C. TLC274C RS = 5 Ω, RL = kω Full range 2 Input offset voltage Average temperature coefficient of input offset voltage V =.4 V, VIC =, 25 C.9 5 TLC274AC O RS = 5 Ω, RL = kω Full range 6.5 V =.4 V, VIC =, 25 C 39 2 TLC274BC O RS = 5 Ω, RL = kω Full range 3 VO =.4 V, VIC =, 25 C 37 2 TLC279C RS = 5 Ω, RL = kω Full range 9 IIO Input offset current (see Note 4) VO =.5 V, VIC = 5 V IIB Input bias current (see Note 4) VO =5V V, VIC =5V VICR Common-mode input voltage range (see Note 5) 25 C 7 C 25 C. UNIT mv µv 2 µv/ C 7 C C.7 7 C C Full range C VOH High-level output voltage VID = mv, RL = kω C V 7 C C 5 VOL Low-level output voltage VID = mv, IOL = C 5 mv AVD Large-signal differential voltage amplification 7 C 5 25 C 36 VO = V 6 V, RL = kω C V/mV 7 C C CMRR Common-mode rejection ratio VIC = VICRmin C 6 88 db ksvr IDD Supply-voltage lt rejection ratio ( VDD / VIO) Supply current (four amplifiers) 7 C C V, VO =.4 V C 6 94 db VO = 5 V, VIC = 5 V, No load 7 C C pa pa C ma 7 C Full range is C 7 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V POST OFFICE BOX DALLAS, TEXAS

8 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 electrical characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted) VIO αvio PARAMETER TEST CONDITIONS TA TLC274BI, TLC279I TLC274I, TLC274AI, MIN TYP MAX VO =.4 V, VIC =, 25 C. TLC274I RS = 5 Ω, RL = kω Full range 3 Input offset voltage Average temperature coefficient of input offset voltage VO =.4 V, VIC =, 25 C.9 5 TLC274AI O RS = 5 Ω, RL = kω Full range 7 VO =.4 V, VIC =, 25 C 34 2 TLC274BI RS = 5 Ω, RL = kω Full range 35 VO =.4 V, VIC =, 25 C 32 9 TLC279I RS = 5 Ω, RL = kω Full range 2 IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V IIB Input bias current (see Note 4) VO =25V 2.5 V, VIC =25V 2.5 VICR Common-mode input voltage range (see Note 5) 25 C 85 C 25 C. UNIT mv µv.8 µv/ C 85 C C.6 85 C C Full range C VOH High-level output voltage VID = mv, RL = kω 4 C V 85 C C 5 VOL Low-level output voltage VID = mv, IOL = 4 C 5 mv AVD Large-signal differential voltage amplification 85 C 5 25 C 5 23 VO =.25 V 2 V, RL = kω 4 C V/mV 85 C C 65 8 CMRR Common-mode rejection ratio VIC = VICRmin 4 C 6 8 db ksvr IDD Supply-voltage lt rejection ratio ( VDD / VIO) Supply current (four amplifiers) 85 C C V, VO =.4 V 4 C 6 92 db VO = 2.5 V, VIC = 2.5 V, No load 85 C C pa pa 4 C ma 85 C Full range is 4 C 85 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 electrical characteristics at specified free-air temperature, V DD = V (unless otherwise noted) VIO αvio PARAMETER TEST CONDITIONS TA TLC274BI, TLC279I TLC274I, TLC274AI, MIN TYP MAX VO =.4 V, VIC =, 25 C. TLC274I RS = 5 Ω, RL = kω Full range 3 Input offset voltage Average temperature coefficient of input offset voltage VO =.4 V, VIC =, 25 C.9 5 TLC274AI O RS = 5 Ω, RL = kω Full range 7 VO =.4 V, VIC =, 25 C 39 2 TLC274BI RS = 5 Ω, RL = kω Full range 35 VO =.4 V, VIC =, 25 C 37 2 TLC279I RS = 5 Ω, RL = kω Full range 29 IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V IIB Input bias current (see Note 4) VO =5V V, VIC =5V VICR Common-mode input voltage range (see Note 5) 25 C 85 C 25 C. UNIT mv µv 2 µv/ C 85 C C.7 85 C C Full range C VOH High-level output voltage VID = mv, RL = kω 4 C V 85 C C 5 VOL Low-level output voltage VID = mv, IOL = 4 C 5 mv AVD Large-signal differential voltage amplification 85 C 5 25 C 36 VO = V 6 V, RL = kω 4 C 7 47 V/mV 85 C C CMRR Common-mode rejection ratio VIC = VICRmin 4 C 6 87 db ksvr IDD Supply-voltage lt rejection ratio ( VDD / VIO) Supply current (four amplifiers) 85 C C V, VO =.4 V 4 C 6 92 db VO = 5 V, VIC = 5 V, No load 85 C C pa pa 4 C 5.5 ma 85 C Full range is 4 C 85 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V POST OFFICE BOX DALLAS, TEXAS

10 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 electrical characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted) TLC274M, TLC279M PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VIO αvio Input offset voltage Average temperature coefficient of input offset voltage VO =.4 V, VIC =, 25 C. TLC274M RS = 5 Ω, RL = kω Full range 2 VO =.4 V, VIC =, 25 C 32 9 TLC279M RS = 5 Ω, RL = kω Full range 375 IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V IIB Input bias current (see Note 4) VO =25V 2.5 V, VIC =25V 2.5 VICR Common-mode input voltage range (see Note 5) 25 C 25 C mv µv 2. µv/ C 25 C. pa 25 C.4 5 na 25 C.6 pa 25 C 9 35 na 25 C Full range C VOH High-level output voltage VID = mv, RL = kω 55 C V 25 C C 5 VOL Low-level output voltage VID = mv, IOL = 55 C 5 mv AVD Large-signal differential voltage amplification 25 C 5 25 C 5 23 VO =.25 V 2 V, RL = kω 55 C V/mV 25 C C 65 8 CMRR Common-mode rejection ratio VIC = VICRmin 55 C 6 8 db ksvr IDD Supply-voltage lt rejection ratio ( VDD / VIO) Supply current (four amplifiers) 25 C C V, VO =.4 V 55 C 6 9 db VO = 2.5 V, VIC = 2.5 V, No load 25 C C C 4 ma 25 C Full range is 55 C 25 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V POST OFFICE BOX DALLAS, TEXAS 75265

11 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 electrical characteristics at specified free-air temperature, V DD = V (unless) otherwise noted) VIO αvio TLC274M, TLC279M PARAMETER TEST CONDITIONS TA MIN TYP MAX Input offset voltage Average temperature coefficient of input offset voltage VO =.4 V, VIC =, 25 C. TLC274M RS = 5 Ω, RL = kω Full range 2 VO =.4 V, VIC =, 25 C 37 2 TLC279M RS = 5 Ω, RL = kω Full range 43 IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V IIB Input bias current (see Note 4) VO =5V V, VIC =5V VICR Common-mode input voltage range (see Note 5) 25 C 25 C UNIT mv µv 2.2 µv/ C 25 C. pa 25 C.8 5 na 25 C.7 pa 25 C 35 na 25 C Full range C VOH High-level output voltage VID = mv, RL = kω 55 C V 25 C C 5 VOL Low-level output voltage VID = mv, IOL = 55 C 5 mv AVD Large-signal differential voltage amplification 25 C 5 25 C 36 VO = V 6 V, RL = kω 55 C 7 5 V/mV 25 C C CMRR Common-mode rejection ratio VIC = VICRmin 55 C 6 87 db ksvr IDD Supply-voltage lt rejection ratio ( VDD / VIO) Supply current (four amplifiers) 25 C C V, VO =.4 V 55 C 6 9 db VO = 5 V, VIC = 5 V, No load 25 C C C 6. 2 ma 25 C Full range is 55 C 25 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V POST OFFICE BOX DALLAS, TEXAS 75265

12 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 operating characteristics at specified free-air temperature, V DD = 5 V PARAMETER TEST CONDITIONS TA TLC274C, TLC274AC, TLC274AC, TLC274BC, TLC279C MIN TYP MAX 25 C 3.6 RL = Ω, SR Slew rate at unity gain CL = 2 PF, See Figure Vn BOM B φm Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth Phase margin f = khz, See Figure 2 VIPP = V C 4 7 C 3 25 C 2.9 VIPP = 2.5 V C 3. RS = 2 Ω, VO = VOH, CL = 2 PF, RL = kω, See Figure VI = mv, CL = 2 PF, See Figure 3 VI = mv, f = B, CL = 2 PF, 7 C 2.5 UNIT V/µs 25 C 25 nv/ Hz 25 C 32 C 34 khz 7 C C.7 C 2 MHz 7 C.3 25 C 46 C 47 7 C 44 operating characteristics at specified free-air temperature, V DD = V PARAMETER TEST CONDITIONS TA TLC274C, TLC274AC, TLC274AC, TLC274BC, TLC279C MIN TYP MAX 25 C 5.3 RL = Ω, SR Slew rate at unity gain CL = 2 PF, See Figure Vn BOM B φm Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth Phase margin f = khz, See Figure 2 VIPP = V C C C 4.6 VIPP = 5.5 V C 5. RS = 2 Ω, VO = VOH, CL = 2 PF, RL = kω, See Figure VI = mv, CL = 2 PF, F See Figure 3 VI = mv, f = B, CL = 2 PF, See Figure 3 7 C 3.8 UNIT V/µs 25 C 25 nv/ Hz 25 C 2 C 22 khz 7 C 4 25 C 2.2 C 2.5 MHz 7 C.8 25 C 49 C 5 7 C 46 2 POST OFFICE BOX DALLAS, TEXAS 75265

13 operating characteristics at specified free-air temperature, V DD = 5 V PARAMETER TEST CONDITIONS TA RL = kω, SR Slew rate at unity gain CL = 2 PF, See Figure Vn BOM B Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth f = khz, See Figure 2 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 TLC274I, TLC274AI, TLC274BI, TLC279I MIN TYP MAX 25 C 3.6 VIPP = V 4 C C C 2.9 VIPP = 2.5 V 4 C 3.5 RS = 2 Ω, VO = VOH, CL = 2 PF, RL = kω, See Figure VI = mv, CL = 2 PF, F See Figure 3 φ m Phase margin VI = mv, f = B, CL = 2 PF, See Figure 3 85 C 2.3 UNIT V/µs 25 C 25 nv/ Hz 25 C 32 4 C 38 khz 85 C C.7 4 C 2.6 MHz 85 C.2 25 C 46 4 C C 43 operating characteristics at specified free-air temperature, V DD = V PARAMETER TEST CONDITIONS TAA RL = Ω, SR Slew rate at unity gain CL = 2 PF, See Figure Vn BOM B Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth f = khz, See Figure 2 TLC274I, TLC274AI, TLC274BI, TLC279I MIN TYP MAX 25 C 5.3 VIPP = V 4 C C 4 25 C 4.6 VIPP = 5.5 V 4 C 5.8 RS = 2 Ω, VO = VOH, CL = 2 PF, RL = kω, See Figure VI = mv, CL = 2 PF, See Figure 3 φ m Phase margin VI = mv, f = B, CL = 2 PF, See Figure 3 85 C 3.5 UNIT V/µs 25 C 25 nv/ Hz 25 C 2 4 C 26 khz 85 C 3 25 C C 3. MHz 85 C.7 25 C 49 4 C C 46 POST OFFICE BOX DALLAS, TEXAS

14 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 operating characteristics at specified free-air temperature, V DD = 5 V PARAMETER TEST CONDITIONS TA RL = kω, SR Slew rate at unity gain CL = 2 PF, See Figure Vn BOM B Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth f = khz, See Figure 2 TLC274M, TLC279M MIN TYP MAX 25 C 3.6 VIPP = V 55 C C C 2.9 VIPP = 2.5 V 55 C 3.7 RS = 2 Ω, VO = VOH, CL = 2 PF, F RL = kω, See Figure VI = mv, CL = 2 PF, See Figure 3 φ m Phase margin VI = mv, f = B, CL = 2 PF, See Figure 3 25 C 2 UNIT V/µs 25 C 25 nv/ Hz 25 C C 4 khz 25 C C.7 55 C 2.9 MHz 25 C. 25 C C C 4 operating characteristics at specified free-air temperature, V DD = V PARAMETER TEST CONDITIONS TA RL = Ω, SR Slew rate at unity gain CL = 2 PF, See Figure Vn BOM B Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth f = khz, See Figure 2 TLC274M, TLC279M MIN TYP MAX 25 C 5.3 VIPP = V 55 C C C 4.6 VIPP = 5.5 V 55 C 6. RS = 2 Ω, VO = VOH, CL = 2 PF, RL = kω, See Figure VI = mv, CL = 2 PF, See Figure 3 φ m Phase margin VI = mv, f = B, CL = 2 PF, See Figure 3 25 C 2.7 UNIT V/µs 25 C 25 nv/ Hz 25 C 2 55 C 28 khz 25 C 25 C C 3.4 MHz 25 C.6 25 C C C 44 4 POST OFFICE BOX DALLAS, TEXAS 75265

15 electrical characteristics, V DD = 5 V, T A = 25 C (unless otherwise noted) VIO Input offset voltage PARAMETER VO =.4 V, RS = 5 Ω, TEST CONDITIONS SLOS92B SEPTEMBER 987 REVISED AUGUST 994 VIC =, RL = kω TLC274Y MIN TYP MAX UNIT. mv IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V. pa IIB Input bias current (see Note 4) VO = 2.5 V, VIC = 2.5 V.6 pa VICR Common-mode input voltage range (see Note 5) VOH High-level output voltage VID = mv, RL = kω V VOL Low-level output voltage VID = mv, IOL = 5 mv AVD Large-signal differential voltage amplification VO =.25 V 2 V, RL = kω 5 23 V/mV CMRR Common-mode rejection ratio VIC = VICRmin 65 8 db ksvr Supply-voltage rejection ratio ( VDD / VIO) V, VO =.4 V db IDD Supply current (four amplifiers) VO = 2.5 V, VIC = 2.5 V, ma No load V electrical characteristics, V DD = V, T A = 25 C (unless otherwise noted) VIO Input offset voltage PARAMETER VO =.4 V, RS = 5 Ω, TEST CONDITIONS VIC =, RL = kω TLC274Y MIN TYP MAX UNIT. mv IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V. pa IIB Input bias current (see Note 4) VO = 5 V, VIC = 5 V.7 pa VICR Common-mode input voltage range (see Note 5) VOH High-level output voltage VID = mv, RL = kω V VOL Low-level output voltage VID = mv, IOL = 5 mv AVD Large-signal differential voltage amplification VO = V 6 V, RL = kω 36 V/mV CMRR Common-mode rejection ratio VIC = VICRmin db ksvr Supply-voltage rejection ratio ( VDD / VIO) V, VO =.4 V db IDD Supply current (four amplifiers) VO = 5 V, VIC = 5 V, ma No load NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually V POST OFFICE BOX DALLAS, TEXAS

16 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 operating characteristics, V DD = 5 V, T A = 25 C PARAMETER TEST CONDITIONS TLC274Y MIN TYP MAX RL = kω, CL = 2 PF, VIPP = V 3.6 SR Slew rate at unity gain See Figure VIPP = 2.5 V 2.9 Vn Equivalent input noise voltage f = khz, RS = 2 Ω, See Figure 2 25 nv/ Hz BOM Maximum output-swing bandwidth VO = VOH, See Figure CL = 2 PF, RL = kω, 32 khz B Unity-gain bandwidth VI = mv, CL = 2 PF, See Figure 3.7 MHz φ m Phase margin VI = mv, f = B, CL = 2 PF, 46 See Figure 3 UNIT V/µs operating characteristics, V DD = V, T A = 25 C PARAMETER TEST CONDITIONS TLC274Y MIN TYP MAX RL = kω, CL = 2 PF, VIPP = V 5.3 SR Slew rate at unity gain See Figure VIPP = 5.5 V 4.6 Vn Equivalent input noise voltage f = khz, RS = 2 Ω, See Figure 2 25 nv/ Hz BOM Maximum output-swing bandwidth VO = VOH, See Figure CL = 2 PF, RL = kω, 2 khz B Unity-gain bandwidth VI = mv, CL = 2 PF, See Figure MHz φ m Phase margin VI = mv, f = B, CL = 2 PF, 49 See Figure 3 UNIT V/µs 6 POST OFFICE BOX DALLAS, TEXAS 75265

17 single-supply versus split-supply test circuits PARAMETER MEASUREMENT INFORMATION SLOS92B SEPTEMBER 987 REVISED AUGUST 994 Because the TLC274 and TLC279 are optimized for single-supply operation, circuit configurations used for the various tests often present some inconvenience since the input signal, in many cases, must be offset from ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives the same result. VDD VDD VO VO VI CL RL VI CL RL VDD (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure. Unity-Gain Amplifier 2 kω 2 kω /2 VDD 2 Ω 2 Ω VDD VO VDD VO 2 Ω 2 Ω VDD (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 2. Noise-Test Circuit kω kω VI Ω VDD VO VI Ω VDD VO /2 VDD CL CL VDD (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 3. Gain-of- Inverting Amplifier POST OFFICE BOX DALLAS, TEXAS

18 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 input bias current PARAMETER MEASUREMENT INFORMATION Because of the high input impedance of the TLC274 and TLC279 operational amplifiers, attempts measure the input bias current can result in erroneous readings. The bias current at normal room ambient temperature is typically less than pa, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered avoid erroneous measurements:. Isolate the device from other potential leakage sources. Use a grounded shield around and between the device inputs (see Figure 4). Leakages that would otherwise flow the inputs are shunted away. 2. Compensate for the leakage of the test socket by actually performing an input bias current test (using a picoammeter) with no device in the test socket. The actual input bias current can then be calculated by subtracting the open-socket leakage readings from the readings obtained with a device in the test socket. One word of caution: many aumatic testers as well as some bench-p operational amplifier testers use the servo-loop technique with a resisr in series with the device input measure the input bias current (the voltage drop across the series resisr is measured and the bias current is calculated). This method requires that a device be inserted in the test socket obtain a correct reading; therefore, an open-socket reading is not feasible using this method. 7 V = VIC 8 4 low-level output voltage Figure 4. Isolation Metal Around Device Inputs (J and N packages) To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise results in the device low-level output being dependent on both the common-mode input voltage level as well as the differential input voltage level. When attempting correlate low-level output readings with those quoted in the electrical specifications, these two conditions should be observed. If conditions other than these are be used, please refer Figures 4 through 9 in the Typical Characteristics of this data sheet. input offset voltage temperature coefficient Erroneous readings often result from attempts measure temperature coefficient of input offset voltage. This parameter is actually a calculation using input offset voltage measurements obtained at two different temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these measurements be performed at temperatures above freezing minimize error. 8 POST OFFICE BOX DALLAS, TEXAS 75265

19 PARAMETER MEASUREMENT INFORMATION SLOS92B SEPTEMBER 987 REVISED AUGUST 994 full-power response Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is generally measured by moniring the disrtion level of the output while increasing the frequency of a sinusoidal input signal until the maximum frequency is found above which the output contains significant disrtion. The full-peak response is defined as the maximum output frequency, without regard disrtion, above which full peak--peak output swing cannot be maintained. Because there is no industry-wide accepted value for significant disrtion, the full-peak response is specified in this data sheet and is measured using the circuit of Figure. The initial setup involves the use of a sinusoidal input determine the maximum peak--peak output of the device (the amplitude of the sinusoidal wave is increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same amplitude. The frequency is then increased until the maximum peak--peak output can no longer be maintained (Figure 5). A square wave is used allow a more accurate determination of the point at which the maximum peak--peak output is reached. test time (a) f = khz (b) BOM > f > khz (c) f = BOM (d) f > BOM Figure 5. Full-Power-Response Output Signal Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume, short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and lower temperatures. POST OFFICE BOX DALLAS, TEXAS

20 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution 6, 7 αvio Temperature coefficient of input offset voltage Distribution 8, 9 High-level output current, VOH High-level output voltage Supply voltage 2 Free-air temperature 3 VOL AVD Low-level output voltage Large-signal differential voltage amplification Common-mode mode input voltage 4, 5 Differential input voltage 6 Free-air temperature 7 Low-level output current 8, 9 Supply voltage 2 Free-air temperature 2 Frequency 32, 33 IIB Input bias current Free-air temperature 22 IIO Input offset current Free-air temperature 22 VIC Common-mode input voltage Supply voltage 23 IDD SR Supply current Slew rate Supply voltage 24 Free-air temperature 25 Supply voltage 26 Free-air temperature 27 Normalized slew rate Free-air temperature 28 VO(PP) Maximum peak--peak output voltage Frequency 29 B φmm Unity-gain bandwidth Phase margin Free-air temperature 3 Supply voltage 3 Supply voltage 34 Free-air temperature 35 Load capacitance 36 Vn Equivalent input noise voltage Frequency 37 Phase shift Frequency 32, 33 2 POST OFFICE BOX DALLAS, TEXAS 75265

21 TYPICAL CHARACTERISTICS SLOS92B SEPTEMBER 987 REVISED AUGUST 994 DISTRIBUTION OF TLC274 INPUT OFFSET VOLTAGE DISTRIBUTION OF TLC274 INPUT OFFSET VOLTAGE Percentage of Units % ÑÑÑÑÑÑÑÑÑÑÑÑ 753 Amplifiers Tested From 6 Wafer Lots TA= 25 C N Package Percentage of Units % ÑÑÑÑÑÑÑÑÑÑÑÑ 753 Amplifiers Tested From 6 Wafer Lots VDD = V N Package VIO Input Offset Voltage mv VIO Input Offset Voltage mv 4 5 Figure 6 Figure 7 Percentage of Units % DISTRIBUTION OF TLC274 AND TLC279 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT ÑÑÑÑÑÑÑÑÑÑÑ 324 Amplifiers Tested From 8 Wafer Lots 25 C N Package Outliers: () 2.5 V/ C Percentage of Units % 6 ÑÑÑÑÑÑÑÑÑÑÑÑ 324 Amplifiers Tested From 8 Wafer Lots VDD = V 5 25 C N Package Outliers: 4 () 2.2 V/C 3 2 DISTRIBUTION OF TLC274 AND TLC279 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT αvio Temperature Coefficient µv/ C αvio Temperature Coefficient µv/ C Figure 8 Figure 9 POST OFFICE BOX DALLAS, TEXAS

22 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 TYPICAL CHARACTERISTICS Q HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT 5 6 High-Level Output Voltage V V OH VDD = 3 V VDD = 4 V VID = mv High-Level Output Voltage V V OH VDD = 6 V VDD = V VID = mv IOH High-Level Output Current ma IOH High-Level Output Current ma Figure Figure HIGH-LEVEL OUTPUT VOLTAGE SUPPLY VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE 6 VDD.6 High-Level Output Voltage V VID = mv RL = kω High-Level Output Voltage V VDD.7 VDD.8 VDD.9 VDD 2 VDD 2. VDD 2.2 VDD = V IOH = 5 ma VID = ma V OH 2 V OH VDD VDD VDD Supply Voltage V TA Free-Air Temperature C Figure 2 Figure 3 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 22 POST OFFICE BOX DALLAS, TEXAS 75265

23 TYPICAL CHARACTERISTICS SLOS92B SEPTEMBER 987 REVISED AUGUST 994 LOW-LEVEL OUTPUT VOLTAGE COMMON-MODE INPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE COMMON-MODE INPUT VOLTAGE 7 5 Low-Level Output Voltage mv V OL VID = V VID = mv IOL = 5 ma V OL Low-Level Output Voltage mv VID = mv VID = V VID = 2.5 V VDD = V IOL = 5 ma VIC Common-Mode Input Voltage V VIC Common-Mode Input Voltage V Figure 4 Figure 5 LOW-LEVEL OUTPUT VOLTAGE DIFFERENTIAL INPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE 8 9 V OL Low-Level Output Voltage mv VDD = V IOL = 5 ma VIC = VID/2 V OL Low-Level Output Voltage mv IOL = 5 ma VID = V VIC =.5 V VDD = V VID Differential Input Voltage V TA Free-Air Temperature C 25 Figure 6 Figure 7 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS

24 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT V OL Low-Level Output Voltage V VID = V VIC =.5 V VDD = 3 V VDD = 4 V V OL Low-Level Output Voltage V 3 VID = V VIC =.5 V VDD = V ÑÑÑÑ VDD = 6 V IOL Low-Level Output Current ma IOL Low-Level Output Current ma 3 Figure 8 Figure 9 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION SUPPLY VOLTAGE LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION FREE-AIR TEMPERATURE ÁÁAVD Large-Signal Differential Voltage Amplification V/mV ÁÁ RL = kω TA = 55 C TA = C ÑÑÑÑ TA = 85 C TA = 25 C AVD VD Large-Signal Differential Voltage Amplification V/mV ÁÁ ÁÁ VDD = V RL = kω VDD Supply Voltage V TA Free-Air Temperature C 25 Figure 2 Figure 2 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 24 POST OFFICE BOX DALLAS, TEXAS 75265

25 TYPICAL CHARACTERISTICS SLOS92B SEPTEMBER 987 REVISED AUGUST 994 Input Bias and Offset Currents pa IIB and IIO INPUT BIAS CURRENT AND INPUT OFFSET CURRENT FREE-AIR TEMPERATURE. 25 VDD = V VIC = 5 V See Note A ÑÑÑ IIB ÑÑ I IO TA Free-Air Temperature C 25 NOTE A: The typical values of input bias current and input offset current below 5 pa were determined mathematically. V IC Common-Mode Input Voltage V COMMON-MODE INPUT VOLTAGE POSITIVE LIMIT SUPPLY VOLTAGE VDD Supply Voltage V 6 Figure 22 Figure 23 SUPPLY CURRENT SUPPLY VOLTAGE SUPPLY CURRENT FREE-AIR TEMPERATURE 8 I DD Supply Current ma VO = VDD/2 No Load ÑÑÑÑ TA = 55 C TA = C ÑÑÑÑ TA = 7 C ÑÑÑÑÑ TA = 25 C VDD Supply Voltage V 6 Supply Current ma I DD VO = VDD/2 No Load VDD = V TA Free-Air Temperature C 25 Figure 24 Figure 25 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS

26 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 TYPICAL CHARACTERISTICS SR Slew Rate V/µs AV = VIPP = V RL = k Ω CL = 2 pf See Figure SLEW RATE SUPPLY VOLTAGE SR Slew Rate V/µs SLEW RATE FREE-AIR TEMPERATURE VIPP = V AV = ÑÑÑÑÑ R L = k Ω VDD = V CL = 2 pf VIPP = 5.5 V See Figure VDD = V VIPP = V VIPP = 2.5 V VDD Supply Voltage V TA Free-Air Temperature C 25 Figure 26 Figure 27 Normalized Slew Rate NORMALIZED SLEW RATE FREE-AIR TEMPERATURE VDD = V AV = VIPP = V RL = kω CL = 2 pf TA Free-Air Temperature C 25 Maximum Peak--Peak Output Voltage V V O(PP) MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE FREQUENCY VDD = V RL = k Ω See Figure f Frequency khz TA = 25 C TA = 55 C Figure 28 Figure 29 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 26 POST OFFICE BOX DALLAS, TEXAS 75265

27 TYPICAL CHARACTERISTICS SLOS92B SEPTEMBER 987 REVISED AUGUST UNITY-GAIN BANDWIDTH FREE-AIR TEMPERATURE 2.5 UNITY-GAIN BANDWIDTH SUPPLY VOLTAGE B Unity-Gain Bandwidth MHz VI = mv CL = 2 pf See Figure 3 B Unity-Gain Bandwidth MHz 2.5 VI = mv CL = 2 pf See Figure TA Free-Air Temperature C VDD Supply Voltage V 6 Figure 3 Figure 3 AVD Large-Signal Differential Voltage Amplification ÁÁ LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT FREQUENCY RL = k Ω AVD Phase Shift Phase Shift. k k k M f Frequency Hz Figure 32 8 M Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS

28 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 TYPICAL CHARACTERISTICS ÁÁAVD Large-Signal Differential Voltage Amplification ÁÁ LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT FREQUENCY VDD = V RL = k Ω AVD Phase Shift Phase Shift. k k k M f Frequency Hz Figure 33 8 M PHASE MARGIN SUPPLY VOLTAGE PHASE MARGIN FREE-AIR TEMPERATURE VI = mv CL = 2 pf See Figure 3 φ m Phase Margin VI = mv CL = 2 pf See Figure 3 φ m Phase Margin VDD Supply Voltage V TA Free-Air Temperature C Figure 34 Figure 35 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 28 POST OFFICE BOX DALLAS, TEXAS 75265

29 TYPICAL CHARACTERISTICS SLOS92B SEPTEMBER 987 REVISED AUGUST 994 PHASE MARGIN CAPACITIVE LOAD EQUIVALENT INPUT NOISE VOLTAGE FREQUENCY 5 4 φ m Phase Margin VI = mv See Figure 3 nv/ Hz Equivalent Input Noise Voltage 3 2 RS = 2 Ω See Figure 2 Vn CL Capacitive Load pf f Frequency Hz Figure 36 Figure 37 POST OFFICE BOX DALLAS, TEXAS

30 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 single-supply operation APPLICATION INFORMATION While the TLC274 and TLC279 perform well using dual power supplies (also called balanced or split supplies), the design is optimized for single-supply operation. This design includes an input common-mode voltage range that encompasses ground as well as an output voltage range that pulls down ground. The supply voltage range extends down 3 V (C-suffix types), thus allowing operation with supply levels commonly available for TTL and HCMOS; however, for maximum dynamic range, 6-V single-supply operation is recommended. Many single-supply applications require that a voltage be applied one input establish a reference level that is above ground. A resistive voltage divider is usually sufficient establish this reference level (see Figure 38). The low input bias current of the TLC274 and TLC279 permits the use of very large resistive values implement the voltage divider, thus minimizing power consumption. The TLC274 and TLC279 work well in conjunction with digital logic; however, when powering both linear devices and digital logic from the same power supply, the following precautions are recommended:. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise the linear device supply rails can fluctuate due voltage drops caused by high switching currents in the digital logic. 2. Use proper bypass techniques reduce the probability of noise-induced errors. Single capacitive decoupling is often adequate; however, high-frequency applications may require R C decoupling. VDD R4 VI R R2 VO VREF = R3 VDD R R3 VO = (VREF VI ) R4 R2 V REF VREF R3 C. µf Figure 38. Inverting Amplifier With Voltage Reference VO Logic Logic Logic Power Supply (a) COMMON SUPPLY RAILS VO Logic Logic Logic Power Supply (b) SEPARATE BYPASSED SUPPLY RAILS (preferred) Figure 39. Common Versus Separate Supply Rails 3 POST OFFICE BOX DALLAS, TEXAS 75265

31 APPLICATION INFORMATION SLOS92B SEPTEMBER 987 REVISED AUGUST 994 input characteristics The TLC274 and TLC279 are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device malfunction. Exceeding this specified range is a common problem, especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit is specified at V DD V at T A = 25 C and at V DD.5 V at all other temperatures. The use of the polysilicon-gate process and the careful input circuit design gives the TLC274 and TLC279 very good input offset voltage drift characteristics relative conventional metal-gate processes. Offset voltage drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. Placing the phosphorus dopant in a conducr (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with time has been calculated be typically. µv/month, including the first month of operation. Because of the extremely high input impedance and resulting low bias current requirements, the TLC274 and TLC279 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good practice include guard rings around inputs (similar those of Figure 4 in the Parameter Measurement Information section). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input (see Figure 4). Unused amplifiers should be connected as grounded unity-gain followers avoid possible oscillation. noise performance The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier. The low input bias current requirements of the TLC274 and TLC279 result in a very low noise current, which is insignificant in most applications. This feature makes the devices especially favorable over bipolar devices when using values of circuit impedance greater than 5 kω, since bipolar devices exhibit greater noise currents. VI VI VO VO VO VI (a) NONINVERTING AMPLIFIER output characteristics (b) INVERTING AMPLIFIER Figure 4. Guard-Ring Schemes (c) UNITY-GAIN AMPLIFIER The output stage of the TLC274 and TLC279 is designed sink and source relatively high amounts of current (see typical characteristics). If the output is subjected a short-circuit condition, this high current capability can cause device damage under certain conditions. Output current capability increases with supply voltage. All operating characteristics of the TLC274 and TLC279 were measured using a 2-pF load. The devices drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 4). In many cases, adding a small amount of resistance in series with the load capacitance alleviates the problem. POST OFFICE BOX DALLAS, TEXAS

32 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 output characteristics (continued) APPLICATION INFORMATION (a) CL = 2 pf, RL = NO LOAD (b) CL = 3 pf, RL = NO LOAD 2.5 V VO VI CL f = khz VIPP = V (c) CL = 5 pf, RL = NO LOAD 2.5 V (d) TEST CIRCUIT Figure 4. Effect of Capacitive Loads and Test Circuit Although the TLC274 and TLC279 possess excellent high-level output voltage and current capability, methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup resisr (R P ) connected from the output the positive supply rail (see Figure 42). There are two disadvantages the use of this circuit. First, the NMOS pulldown transisr N4 (see equivalent schematic) must sink a comparatively large amount of current. In this circuit, N4 behaves like a linear resisr with an on-resistance between approximately 6 Ω and 8 Ω, depending on how hard the op amp input is driven. With very low values of R P, a voltage offset from V at the output occurs. Second, pullup resisr R P acts as a drain load N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying the output current. 32 POST OFFICE BOX DALLAS, TEXAS 75265

33 output characteristics (continued) APPLICATION INFORMATION SLOS92B SEPTEMBER 987 REVISED AUGUST 994 VDD C VI IP RP IF VO VO R R2 IL RL Rp = V DD VO IF IL IP IP = Pullup current required by the operational amplifier (typically 5 µa) Figure 43. Compensation for Input Capacitance Figure 42. Resistive Pullup Increase V OH feedback Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads (discussed previously) and ignoring stray input capacitance. A small-value capacir connected in parallel with the feedback resisr is an effective remedy (see Figure 43). The value of this capacir is optimized empirically. electrostatic discharge protection latch-up The TLC274 and TLC279 incorporate an internal electrostatic discharge (ESD) protection circuit that prevents functional failures at voltages up 2 V as tested under MIL-STD-883C, Method Care should be exercised, however, when handling these devices as exposure ESD may result in the degradation of the device parametric performance. The protection circuit also causes the input bias currents be temperature-dependent and have the characteristics of a reverse-biased diode. Because CMOS devices are susceptible latch-up due their inherent parasitic thyrisrs, the TLC274 and TLC279 inputs and outputs were designed withstand -ma surge currents without sustaining latch-up; however, techniques should be used reduce the chance of latch-up whenever possible. Internal protection diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply voltage by more than 3 mv. Care should be exercised when using capacitive coupling on pulse generars. Supply transients should be shunted by the use of decoupling capacirs (. µf typical) located across the supply rails as close the device as possible. The current path established if latch-up occurs is usually between the positive supply rail and ground and can be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the forward resistance of the parasitic thyrisr and usually results in the destruction of the device. The chance of latch-up occurring increases with increasing temperature and supply voltages. POST OFFICE BOX DALLAS, TEXAS

34 SLOS92B SEPTEMBER 987 REVISED AUGUST 994 APPLICATION INFORMATION kω kω.6 µf.6 µf VI kω /4 TLC274 kω /4 TLC274 kω 5 V /4 TLC274 Low Pass HIgh Pass 5 kω R = 5 kω (3/d) (see Note A) Band Pass NOTE A: d = damping facr, /Q Figure 44. State-Variable Filter 2 V VI /4 TLC274 H.P µf Mylar N.O. Reset /4 TLC274 VO kω Figure 45. Positive-Peak Detecr 34 POST OFFICE BOX DALLAS, TEXAS 75265

35 APPLICATION INFORMATION SLOS92B SEPTEMBER 987 REVISED AUGUST 994 VI (see Note A).2 kω kω.47 µf TL43 2 kω 4.7 kω. µf /4 TLC274 kω 47 kω TIS93 5 Ω 25 µf, 25 V TIP3 kω VO (see Note B). µf 22 kω Ω NOTES: B. VI = 3.5 V 5 V C. VO = 2 V, A Figure 46. Logic-Array Power Supply 9 V VO (see Note A) kω 9 V. µf C /4 kω TLC274 R2 /4 kω TLC274 VO (see Note B) kω R 47 kω fo = 4C(R2) R R2 R3 NOTES: A. VO(PP) = 8 V B. VO(PP) = 4 V Figure 47. Single-Supply Function Generar POST OFFICE BOX DALLAS, TEXAS

36 SLOS92B SEPTEMBER 987 REVISED AUGUST V APPLICATION INFORMATION VI /4 TLC279 kω kω /4 TLC279 VO kω /4 TLC279 kω 95 kω R, kω (see Note A) VI 5 V NOTE C: CMRR adjustment must be noninductive. Figure 48. Low-Power Instrumentation Amplifier 5 V VI R MΩ R MΩ /4 TLC274 VO 2C 54 pf R/2 5 MΩ f NOTCH 2RC C 27 pf C 27 pf Figure 49. Single-Supply Twin-T Notch Filter 36 POST OFFICE BOX DALLAS, TEXAS 75265

37 IMPORTANT NOTICE Texas Instruments (TI) reserves the right make changes its products or discontinue any semiconducr product or service without notice, and advises its cusmers obtain the latest version of relevant information verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconducr products and related software the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized the extent TI deems necessary support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconducr products may involve potential risks of death, personal injury, or severe property or environmental damage ( Critical Applications ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is undersod be fully at the risk of the cusmer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed TI through a local SC sales office. In order minimize risks associated with the cusmer s applications, adequate design and operating safeguards should be provided by the cusmer minimize inherent or procedural hazards. TI assumes no liability for applications assistance, cusmer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating any combination, machine, or process in which such semiconducr products or services might be or are used. Copyright 996, Texas Instruments Incorporated