TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9 LinCMOS PRECISION QUAD OPERATIONAL AMPLIFIERS

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1 SLOS93C OCTOBER 1987 REVISED MAY 1999 Trimmed Offset Voltage: TLC27M9...9 µv Max at T A = 25 C, V DD = 5 V Input Offset Voltage Drift...Typically.1 µv/month, Including the First 3 Days Wide Range of Supply Voltages Over Specified Temperature Range: C 7 C...3 V 16 V 4 C 85 C...4 V 16 V 55 C 125 C...4 V 16 V Single-Supply Operation Common-Mode Input Voltage Range Extends Below the Negative Rail (C-Suffix, I-Suffix Types) Low Noise...Typically 32 nv/ Hz at f = 1 khz Low Power...Typically 2.1 mw at T A =25 C, V DD = 5 V Output Voltage Range Includes Negative Rail High Input Impedance Ω Typ ESD-Protection Circuitry Small-Outline Package Option Also Available in Tape and Reel Designed-In Latch-Up Immunity description The TLC27M4 and TLC27M9 quad operational amplifiers combine a wide range of input offset voltage grades with low offset voltage drift, high input impedance, low noise, and speeds comparable that of general-purpose bipolar devices.these devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset voltage stability far exceeding the stability available with conventional metal-gate processes. The extremely high input impedance, low bias currents, make these cost-effective devices ideal for applications that have previously been reserved for general-purpose bipolar products, but with only a fraction of the power consumption. Percentage of Units % IN NC V DD NC 2IN 12 D, J, N, OR PW PACKAGE (TOP VIEW) 1OUT 1IN 1IN V DD 2IN 2IN 2OUT FK PACKAGE (TOP VIEW) 1IN 1OUT NC IN 2OUT NC 4OUT 4IN 3OUT 3IN NC No internal connection 4OUT 4IN 4IN GND 3IN 3IN 3OUT 4IN NC GND NC 3IN DISTRIBUTION OF TLC27M9 INPUT OFFSET VOLTAGE 31 Units Tested From 2 Wafer Lots VDD = 5 V N Package VIO Input Offset Voltage µv Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconducr products and disclaimers there appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1998, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 SLOS93C OCTOBER 1987 REVISED MAY 1999 description (continued) Four offset voltage grades are available (C-suffix and I-suffix types), ranging from the low-cost TLC27M4 (1 mv) the high-precision TLC27M9 (9 µv). These advantages, in combination with good common-mode rejection and supply voltage rejection, make these devices a good choice for new state-of-the-art designs as well as for upgrading existing designs. In general, many features associated with bipolar technology are available on LinCMOS operational amplifiers, without the power penalties of bipolar technology. General applications such as transducer interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27M4 and TLC27M9. The devices also exhibit low voltage single-supply operation, and low power consumption, making them ideally suited for remote and inaccessible battery-powered applications. The common-mode input voltage range includes the negative rail. A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density system applications. The device inputs and outputs are designed withstand 1-mA surge currents without sustaining latch-up. The TLC27M4 and TLC27M9 incorporate internal ESD-protection circuits that prevent functional failures at voltages up 2 V as tested under MIL-STD-883C, Method 315; however, care should be exercised in handling these devices, as exposure ESD may result in the degradation of the device parametric performance. The C-suffix devices are characterized for operation from C 7 C. The I-suffix devices are characterized for operation from 4 C 85 C. The M-suffix devices are characterized for operation over the full military temperature range of 55 C 125 C. TA C 7 C 4 C 85 C 55 C 125 C VIOmax AT 25 C SMALL OUTLINE (D) AVAILABLE OPTIONS CHIP CARRIER (FK) PACKAGE CERAMIC DIP (J) PLASTIC DIP (N) TSSOP (PW) 9 µv TLC27M9CD TLC27M9CN 2 mv TLC27M4BCD TLC27M4BCN 5 mv TLC27M4ACD TLC27M4ACN CHIP FORM (Y) 1 mv TLC27M4CD TLC27M4CN TLC27M4CPW TLC27M4Y 9 µv TLC27M9ID TLC27M9IN 2 mv TLC27M4BID TLC27M4BIN 5 mv TLC27M4AID TLC27M4AIN 1 mv TLC27M4ID TLC27M4IN TLC27M41PW 9 µv TLC27M9MD TLC27M9MFK TLC27M9MJ TLC27M9MN 1 mv TLC27M4MD TLC27M4MFK TLC27M4MJ TLC27M4MN The D and PW package is available taped and reeled. Add R suffix the device type (e.g., TLC279CDR). 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 equivalent schematic (each amplifier) VDD SLOS93C OCTOBER 1987 REVISED MAY 1999 P3 P4 R6 IN IN R1 P1 P2 R2 R5 N5 C1 P5 P6 OUT N3 N1 N2 R3 D1 R4 D2 N4 N6 R7 N7 GND POST OFFICE BOX DALLAS, TEXAS

4 SLOS93C OCTOBER 1987 REVISED MAY 1999 TLC27M4Y chip information This chip, when properly assembled, displays characteristics similar the TLC27M4C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS 68 (14) (13) (12) (11) (1) (9) (8) (1) (2) (3) (4) (5) (6) (7) 1IN 1IN 2OUT 3IN 3IN 4OUT VDD (3) (4) (1) (2) 1OUT (5) (7) 2IN (1) (6) 2IN (8) (9) 3OUT (12) (14) 4IN (13) 4IN (11) GND 18 CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 4 MINIMUM TJmax = 15 C TOLERANCES ARE ±1%. ALL DIMENSIONS ARE IN MILS. PIN (11) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 SLOS93C OCTOBER 1987 REVISED MAY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V DD (see Note 1) V Differential input voltage, V ID (see Note 2) ±V DD Input voltage range, V I (any input) V V DD Input current, I I ±5 ma Output current, l O (each output) ±3 ma Total current in V DD ma Total current out of GND ma Duration of short-circuit current at (or below) 25 C (see Note 3) unlimited Continuous tal dissipation See Dissipation Rating Table Operating free-air temperature, T A : C suffix C 7 C I suffix C 85 C M suffix C 125 C Srage temperature range C 15 C Case temperature for 6 seconds: FK package C Lead temperature 1,6 mm (1/16 inch) from case for 1 seconds: D, N, or PW package C Lead temperature 1,6 mm (1/16 inch) from case for 6 seconds: J package C Stresses beyond those listed under absolute maximum ratings may cause permanent damage the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect network ground. 2. Differential voltages are at IN with respect IN. 3. The output may be shorted either supply. Temperature and/or supply voltages must be limited ensure that the maximum dissipation rating is not exceeded (see application section). PACKAGE TA 25 C POWER RATING DISSIPATION RATING TABLE DERATING FACTOR ABOVE TA = 7 C POWER RATING TA = 85 C POWER RATING TA = 125 C POWER RATING D 95 mw 7.6 mw/ C 68 mw 494 mw FK 1375 mw 11. mw/ C 88 mw 715 mw 275 mw J 1375 mw 11. mw/ C 88 mw 715 mw 275 mw N 1575 mw 12.6 mw/ C 18 mw 819 mw PW 7 mw 5.6 mw/ C 448 mw recommended operating conditions C SUFFIX I SUFFIX M SUFFIX MIN MAX MIN MAX MIN MAX Supply voltage, VDD V Common-mode mode input voltage, VIC VDD = 5 V VDD = 1 V Operating free-air temperature, TA C UNIT V POST OFFICE BOX DALLAS, TEXAS

6 SLOS93C OCTOBER 1987 REVISED MAY 1999 electrical characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted) VIO αvio Input offset voltage TLC27M4C TLC27M4AC PARAMETER TEST CONDITIONS TA TLC27M4BC TLC27M9C MIN TYP MAX VO = 1.4 V, VIC =, 25 C TLC27M4C RS = 5 Ω, RL = 1 kω Full range 12 Average temperature coefficient of input offset voltage V = 1.4 V, VIC =, 25 C.9 5 TLC27M4AC O RS = 5 Ω, RL = 1 kω Full range 6.5 VO = 1.4 V, VIC =, 25 C 25 2 TLC274BC RS = 5 Ω, RL = 1 kω Full range 3 VO = 1.4 V, VIC =, 25 C 21 9 TLC279C RS = 5 Ω, RL = 1 kω Full range 15 IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V IIB Input bias current (see Note 4) VO =25V 2.5 V, VIC =25V 2.5 VICR Common-mode input voltage range (see Note 5) 25 C 7 C 25 C.1 UNIT mv µv 1.7 µv/ C 7 C C.6 7 C C Full range C VOH High-level output voltage VID = 1 mv, RL = 1 kω C V 7 C C 5 VOL Low-level output voltage VID = 1 mv, IOL = C 5 mv AVD Large-signal differential voltage amplification 7 C 5 25 C VO =.25 V 2 V, RL = 1 kω C 15 2 V/mV 7 C C CMRR Common-mode rejection ratio VIC = VICRmin C 6 91 db ksvr IDD Supply-voltage lt rejection ratio ( VDD / VIO) Supply current (four amplifiers) 7 C C 7 93 VDD = 5 V 1 V, VO = 1.4 V C 6 92 db VO = 2.5 V, VIC = 2.5 V, No load 7 C C pa pa C µa 7 C Full range is C 7 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 SLOS93C OCTOBER 1987 REVISED MAY 1999 electrical characteristics at specified free-air temperature, V DD = 1 V (unless otherwise noted) VIO αvio TLC27M4C TLC27M4AC PARAMETER TEST CONDITIONS TA TLC27M4BC TLC27M9C MIN TYP MAX VO = 1.4 V, VIC =, 25 C TLC27M4C RS = 5 Ω, RL = 1 kω Full range 12 Input offset voltage Average temperature coefficient of input offset voltage VO = 1.4 V, VIC =, 25 C.9 5 TLC27M4AC RS = 5 Ω, RL = 1 kω Full range 6.5 VO = 1.4 V, VIC =, 25 C 26 2 TLC27M4BC RS = 5 Ω, RL = 1 kω Full range 3 VO = 1.4 V, VIC =, 25 C TLC27M9C RS = 5 Ω, RL = 1 kω Full range 19 IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V IIB Input bias current (see Note 4) VO =5V V, VIC =5V VICR Common-mode input voltage range (see Note 5) 25 C 7 C 25 C.1 UNIT mv µv 2.1 µv/ C 7 C C.7 7 C C Full range C VOH High-level output voltage VID = 1 mv, RL = 1 kω C V 7 C C 5 VOL Low-level output voltage VID = 1 mv, IOL = C 5 mv AVD Large-signal differential voltage amplification 7 C 5 25 C VO = 1 V 6 V, RL = 1 kω C V/mV 7 C C CMRR Common-mode rejection ratio VIC = VICRmin C 6 94 db ksvr IDD Supply-voltage lt rejection ratio ( VDD / VIO) Supply current (four amplifiers) 7 C C 7 93 VDD = 5 V 1 V, VO = 1.4 V C 6 92 db VO = 5 V, VIC = 5 V, No load 7 C C pa pa C µa 7 C Full range is C 7 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V POST OFFICE BOX DALLAS, TEXAS

8 SLOS93C OCTOBER 1987 REVISED MAY 1999 electrical characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted) VIO αvio TLC27M4I TLC27M4AI PARAMETER TEST CONDITIONS TA TLC27M4BI TLC27M9I MIN TYP MAX VO = 1.4 V, VIC =, 25 C TLC27M4I RS = 5 Ω, RL = 1 kω Full range 13 Input offset voltage Average temperature coefficient of input offset voltage VO = 1.4 V, VIC =, 25 C.9 5 TLC27M4AI RS = 5 Ω, RL = 1 kω Full range 6.5 VO = 1.4 V, VIC =, 25 C 25 2 TLC27M4BI RS = 5 Ω, RL = 1 kω Full range 3 VO = 1.4 V, VIC =, 25 C 21 9 TLC27M9I RS = 5 Ω, RL = 1 kω Full range 2 IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V IIB Input bias current (see Note 4) VO =25V 2.5 V, VIC =25V 2.5 VICR Common-mode input voltage range (see Note 5) 25 C 85 C 25 C.1 UNIT mv µv 1.7 µv/ C 85 C C.6 85 C C Full range C VOH High-level output voltage VID = 1 mv, RL = 1 kω 4 C V 85 C C 5 VOL Low-level output voltage VID = 1 mv, IOL = 4 C 5 mv AVD Large-signal differential voltage amplification 85 C 5 25 C VO =.25 V 2 V, RL = 1 kω 4 C V/mV 85 C C CMRR Common-mode rejection ratio VIC = VICRmin 4 C 6 9 db ksvr IDD Supply-voltage lt rejection ratio ( VDD / VIO) Supply current (four amplifiers) 85 C C 7 93 VDD = 5 V 1 V, VO = 1.4 V 4 C 6 91 db VO = 2.5 V, VIC = 2.5 V, No load 85 C C pa pa 4 C µa 85 C 32 8 Full range is 4 C 85 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 SLOS93C OCTOBER 1987 REVISED MAY 1999 electrical characteristics at specified free-air temperature, V DD = 1 V (unless otherwise noted) VIO αvio TLC27M4I TLC27M4AI PARAMETER TEST CONDITIONS TA TLC27M4BI TLC27M9I MIN TYP MAX VO = 1.4 V, VIC =, 25 C TLC27M4I RS = 5 Ω, RL = 1 kω Full range 13 Input offset voltage Average temperature coefficient of input offset voltage VO = 1.4 V, VIC =, 25 C.9 5 TLC27M4AI RS = 5 Ω, RL = 1 kω Full range 7 VO = 1.4 V, VIC =, 25 C 26 2 TLC27M4BI RS = 5 Ω, RL = 1 kω Full range 35 VO = 1.4 V, VIC =, 25 C TLC27M9I RS = 5 Ω, RL = 1 kω Full range 29 IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V IIB Input bias current (see Note 4) VO =5V V, VIC =5V VICR Common-mode input voltage range (see Note 5) 25 C 85 C 25 C.1 UNIT mv µv 2.1 µv/ C 85 C C.7 85 C C Full range C VOH High-level output voltage VID = 1 mv, RL = 1 kω 4 C V 85 C C 5 VOL Low-level output voltage VID = 1 mv, IOL = 4 C 5 mv AVD Large-signal differential voltage amplification 85 C 5 25 C VO = 1 V 6 V, RL = 1 kω 4 C V/mV 85 C C CMRR Common-mode rejection ratio VIC = VICRmin 4 C 6 93 db ksvr IDD Supply-voltage lt rejection ratio ( VDD / VIO) Supply current (four amplifiers) 85 C C 7 93 VDD = 5 V 1 V, VO = 1.4 V 4 C 6 91 db VO = 5 V, VIC = 5 V, No load 85 C C pa pa 4 C 9 18 µa 85 C Full range is 4 C 85 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V POST OFFICE BOX DALLAS, TEXAS

10 SLOS93C OCTOBER 1987 REVISED MAY 1999 electrical characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted) VIO αvio PARAMETER TEST CONDITIONS TA TLC27M9M TLC27M4M MIN TYP MAX Input offset voltage V = 1.4 V, VIC =, 25 C TLC27M4M O RS = 5 Ω, RL = 1 kω Full range 12 = 1.4 V, VIC =, 25 C 21 9 TLC27M9M O RS = 5 Ω, RL = 1 kω Full range 375 Average temperature coefficient of input offset voltage IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V IIB Input bias current (see Note 4) VO =25V 2.5 V, VIC =25V 2.5 VICR Common-mode input voltage range (see Note 5) 25 C 125 C UNIT mv µv 1.7 µv/ C 25 C.1 pa 125 C na 25 C.6 pa 125 C 9 35 na 25 C Full range C VOH High-level output voltage VID = 1 mv, RL = 1 kω 55 C V 125 C C 5 VOL Low-level output voltage VID = 1 mv, IOL = 55 C 5 mv AVD Large-signal differential voltage amplification 125 C 5 25 C VO =.25 V 2 V, RL = 1 kω 55 C V/mV 125 C C CMRR Common-mode rejection ratio VIC = VICRmin 55 C 6 89 db ksvr IDD Supply-voltage rejection ratio ( VDD / VIO) Supply current (four amplifiers) 125 C C 7 93 VDD = 5 V 1 V, VO = 1.4 V 55 C 6 91 db VO = 2.5 V, VIC = 2.5 V, No load 125 C C C µa 125 C Full range is 55 C 125 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V 1 POST OFFICE BOX DALLAS, TEXAS 75265

11 SLOS93C OCTOBER 1987 REVISED MAY 1999 electrical characteristics at specified free-air temperature, V DD = 1 V (unless otherwise noted) VIO αvio PARAMETER TEST CONDITIONS TA TLC27M9M TLC27M4M MIN TYP MAX Input offset voltage V = 1.4 V, VIC =, 25 C TLC27M4M O RS = 5 Ω, RL = 1 kω Full range 12 = 1.4 V, VIC =, 25 C TLC27M9M O RS = 5 Ω, RL = 1 kω Full range 43 Average temperature coefficient of input offset voltage IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V IIB Input bias current (see Note 4) VO =5V V, VIC =5V VICR Common-mode input voltage range (see Note 5) 25 C 125 C UNIT mv µv 2.1 µv/ C 25 C.1 pa 125 C na 25 C.7 pa 125 C 1 35 na 25 C Full range C VOH High-level output voltage VID = 1 mv, RL = 1 kω 55 C V 125 C C 5 VOL Low-level output voltage VID = 1 mv, IOL = 55 C 5 mv AVD Large-signal differential voltage amplification 125 C 5 25 C VO = 1 V 6 V, RL = 1 kω 55 C V/mV 125 C C CMRR Common-mode rejection ratio VIC = VICRmin 55 C 6 93 db ksvr IDD Supply-voltage lt rejection ratio ( VDD / VIO) Supply current (four amplifiers) 125 C C 7 93 VDD = 5 V 1 V, VO = 1.4 V 55 C 6 91 db VO = 5 V, VIC = 5 V, No load 125 C C C 98 2 µa 125 C Full range is 55 C 125 C. NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually. V V POST OFFICE BOX DALLAS, TEXAS

12 SLOS93C OCTOBER 1987 REVISED MAY 1999 electrical characteristics, V DD = 5 V, T A = 25 C (unless otherwise noted) PARAMETER TEST CONDITIONS VO = 1.4 V, VIC =, VIO Input offset voltage RS = 5 Ω, RL = 1 kω TLC27M4Y MIN TYP MAX UNIT mv α VIO Temperature coefficient of input offset voltage 7 C 1.7 µv/ C IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V.1 pa IIB Input bias current (see Note 4) VO = 2.5 V, VIC = 2.5 V.6 pa VICR Common-mode input voltage range (see Note 5) VOH High-level output voltage VID = 1 mv, RL = 1 kω V VOL Low-level output voltage VID = 1 mv, IOL = 5 mv AVD Large-signal differential voltage amplification VO =.25 V 2 V, RL= 1 kω V/mV CMRR Common-mode rejection ratio VIC = VICRmin db ksvr Supply-voltage rejection ratio ( VDD / VIO) VDD = 5 V 1 V, VO = 1.4 V 7 93 db IDD Supply current (four amplifiers) VO = 2.5 V, VIC = 2.5 V, µa No load electrical characteristics, V DD = 1 V, T A = 25 C (unless otherwise noted) PARAMETER TEST CONDITIONS VO = 1.4 V, VIC =, VIO Input offset voltage RS = 5 Ω, RL = 1 kω TLC27M4Y MIN TYP MAX V UNIT mv α VIO Temperature coefficient of input offset voltage 7 C 2.1 µv/ C IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V.1 pa IIB Input bias current (see Note 4) VO = 5 V, VIC = 5 V.7 pa VICR Common-mode input voltage range (see Note 5) VOH High-level output voltage VID = 1 mv, RL = 1 kω V VOL Low-level output voltage VID = 1 mv, IOL = 5 mv AVD Large-signal differential voltage amplification VO = 1 V 6 V, RL = 1 kω V/mV CMRR Common-mode rejection ratio VIC = VICRmin db ksvr Supply-voltage rejection ratio ( VDD / VIO) VDD = 5 V 1 V, VO = 1.4 V 7 93 db IDD Supply current (four amplifiers) VO = 5 V, No load VIC = 5 V, µa NOTES: 4. The typical values of input bias current and input offset current below 5 pa were determined mathematically. 5. This range also applies each input individually V 12 POST OFFICE BOX DALLAS, TEXAS 75265

13 operating characteristics at specified free-air temperature, V DD = 5 V SLOS93C OCTOBER 1987 REVISED MAY 1999 TLC27M4C TLC27M4AC PARAMETER TEST CONDITIONS TLC27M4BC TA TLC27M9C MIN TYP MAX 25 C.43 RL = 1 Ω, SR Slew rate at unity gain CL = 2 pf, See Figure 1 Vn BOM B1 φ m Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth Phase margin f = 1 khz, See Figure 2 VIPP = 1 V C.46 7 C C.4 VIPP = 2.5 V C.43 RS = 2 Ω VO = VOH, CL = 2 pf, RL = 1 kω, See Figure 1 VI = 1 mv, CL = 2 pf, See Figure 3 VI = 1 mv, f = B1, CL =2pF F, See Figure 3 operating characteristics at specified free-air temperature, V DD = 1 V 7 C.34 UNIT V/µs 25 C 32 nv/ Hz 25 C 55 C 6 khz 7 C 5 25 C 525 C 61 khz 7 C 4 25 C 4 C 41 7 C 39 TLC27M4C TLC27M4AC PARAMETER TEST CONDITIONS TLC27M4BC TA TLC27M9C MIN TYP MAX 25 C.62 RL = 1 Ω, SR Slew rate at unity gain CL = 2 pf, See Figure 1 Vn BOM B1 φ m Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth Phase margin f = 1 khz, See Figure 2 VIPP = 1 V C.67 7 C C.56 VIPP = 5.5 V C.61 RS = 2 Ω, VO = VOH, CL = 2 pf, RL = 1 kω, See Figure 1 VI = 1 mv, CL = 2 pf, See Figure 3 VI = 1 mv, f = B1, CL =2pF F, See Figure 3 7 C.46 UNIT V/µs 25 C 32 nv/ Hz 25 C 35 C 4 khz 7 C 3 25 C 635 C 71 khz 7 C C 43 C 44 7 C 42 POST OFFICE BOX DALLAS, TEXAS

14 SLOS93C OCTOBER 1987 REVISED MAY 1999 operating characteristics at specified free-air temperature, V DD = 5 V TLC27M4I TLC27M4AI PARAMETER TEST CONDITIONS TLC27M4BI TA TLC27M9I MIN TYP MAX 25 C.43 RL = 1 Ω, SR Slew rate at unity gain CL = 2 pf, See Figure 1 Vn BOM B1 φ m Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth Phase margin f = 1 khz, See Figure 2 VIPP = 1 V 4 C C C.4 VIPP = 2.5 V 4 C.48 RS = 2 Ω, VO = VOH, CL = 2 pf, RL = 1 kω, See Figure 1 VI = 1 mv, CL = 2 pf, See Figure 3 VI = 1 mv, f = B1, CL =2pF F, See Figure 3 operating characteristics at specified free-air temperature, V DD = 1 V 85 C.32 UNIT V/µs 25 C 32 nv/ Hz 25 C 55 4 C 75 khz 85 C C C 77 khz 85 C C 4 4 C C 38 TLC27M4I TLC27M4AI PARAMETER TEST CONDITIONS TLC27M4BI TA TLC27M9I MIN TYP MAX 25 C.62 RL = 1 Ω, SR Slew rate at unity gain CL = 2 pf, See Figure 1 Vn BOM B1 φ m Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth Phase margin f = 1 khz, See Figure 2 VIPP = 1 V 4 C C C.56 VIPP = 5.5 V 4 C.7 RS = 2 Ω, VO = VOH, CL = 2 pf, RL = 1 kω, See Figure 1 VI = 1 mv, See Figure 3 VI = 1 mv, f = B1, CL =2pF F, See Figure 3 85 C.44 UNIT V/µs 25 C 32 nv/ Hz 25 C 35 4 C 45 khz 85 C C 635 CL = 2 pf, 4 C 88 khz 85 C C 43 4 C C POST OFFICE BOX DALLAS, TEXAS 75265

15 operating characteristics at specified free-air temperature, V DD = 5 V PARAMETER TEST CONDITIONS TA RL = 1 Ω, SR Slew rate at unity gain CL = 2 pf, See Figure 1 Vn BOM B1 φ m Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth Phase margin f = 1 khz, See Figure 2 SLOS93C OCTOBER 1987 REVISED MAY 1999 TLC27M4M TLC27M9M MIN TYP MAX 25 C.43 VIPP = 1 V 55 C C C.4 VIPP = 2.5 V 55 C.5 RS = 2 Ω, VO = VOH, CL = 2 pf, RL = 1 kω, See Figure 1 VI = 1 mv, CL = 2 pf, See Figure 3 VI = 1 mv, f = B1, CL =2pF F, See Figure 3 operating characteristics at specified free-air temperature, V DD = 1 V PARAMETER TEST CONDITIONS TA RL = 1 Ω, SR Slew rate at unity gain CL = 2 pf, See Figure 1 Vn BOM B1 φ m Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth Phase margin f = 1 khz, See Figure C.28 UNIT V/µs 25 C 32 nv/ Hz 25 C C 8 khz 125 C 4 25 C C 85 khz 125 C C 4 55 C C 36 TLC27M4M TLC27M9M MIN TYP MAX 25 C.62 VIPP = 1 V 55 C C C.56 VIPP = 5.5 V 55 C.73 RS = 2 Ω, VO = VOH, CL = 2 pf, RL = 1 kω, See Figure 1 VI = 1 mv, CL = 2 pf, See Figure 3 VI = 1 mv, f = B1, CL =2pF F, See Figure C.35 UNIT V/µs 25 C 32 nv/ Hz 25 C C 5 khz 125 C 2 25 C C 96 khz 125 C C C C 39 POST OFFICE BOX DALLAS, TEXAS

16 SLOS93C OCTOBER 1987 REVISED MAY 1999 operating characteristics, V DD = 5 V, T A = 25 C PARAMETER TEST CONDITIONS TLC27M4Y MIN TYP MAX RL = 1 kω, VIPP = 1 V.43 SR Slew rate at unity gain CL = 2 pf, See Figure 1 VIPP = 2.5 V.4 Vn BOM B1 φ m Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth Phase margin f = 1 khz, See Figure 2 VO = VOH, RL = 1 kω, VI = 1 mv, See Figure 3 VI = 1 mv, CL = 2 pf, RS = 2 Ω, CL = 2 pf, See Figure 1 CL = 2 pf, f = B1, See Figure 3 UNIT V/µs 32 nv/ Hz 55 khz 525 khz 4 operating characteristics, V DD = 1 V, T A = 25 C PARAMETER TEST CONDITIONS TLC27M4Y MIN TYP MAX RL = 1 kω, VIPP = 1 V.62 SR Slew rate at unity gain CL = 2 pf, See Figure 1 VIPP = 5.5 V.56 Vn BOM B1 φ m Equivalent input noise voltage Maximum output-swing bandwidth Unity-gain bandwidth Phase margin f = 1 khz, See Figure 2 VO = VOH, RL = 1 kω, VI = 1 mv, See Figure 3 VI = 1 mv, CL = 2 pf, RS = 2 Ω, CL = 2 pf, See Figure 1 CL = 2 pf, f = B1, See Figure 3 UNIT V/µs 32 nv/ Hz 35 khz 635 khz POST OFFICE BOX DALLAS, TEXAS 75265

17 single-supply versus split-supply test circuits PARAMETER MEASUREMENT INFORMATION SLOS93C OCTOBER 1987 REVISED MAY 1999 Because the TLC27M4 and TLC27M9 are optimized for single-supply operation, circuit configurations used for the various tests often present some inconvenience since the input signal, in many cases, must be offset from ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives the same result. VDD VDD VO VO VI CL RL VI CL RL VDD (a) SINGLE SUPPLY Figure 1. Unity-Gain Amplifier (b) SPLIT SUPPLY 2 kω 2 kω 2 Ω VDD VDD 1/2 VDD VO VO 2 Ω 2 Ω 2 Ω VDD (a) SINGLE SUPPLY Figure 2. Noise-Test Circuit (b) SPLIT SUPPLY 1 kω 1 kω VI 1 Ω VDD VO VI 1 Ω VDD VO 1/2 VDD CL CL VDD (a) SINGLE SUPPLY Figure 3. Gain-of-1 Inverting Amplifier (b) SPLIT SUPPLY POST OFFICE BOX DALLAS, TEXAS

18 SLOS93C OCTOBER 1987 REVISED MAY 1999 input bias current PARAMETER MEASUREMENT INFORMATION Because of the high input impedance of the TLC27M4 and TLC27M9 operational amplifiers, attempts measure the input bias current can result in erroneous readings. The bias current at normal room ambient temperature is typically less than 1 pa, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered avoid erroneous measurements: 1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the device inputs (see Figure 4). Leakages that would otherwise flow the inputs are shunted away. 2. Compensate for the leakage of the test socket by actually performing an input bias current test (using a picoammeter) with no device in the test socket. The actual input bias current can then be calculated by subtracting the open-socket leakage readings from the readings obtained with a device in the test socket. One word of caution many aumatic testers as well as some bench-p operational amplifier testers use the servo-loop technique with a resisr in series with the device input measure the input bias current; the voltage drop across the series resisr is measured and the bias current is calculated. This method requires that a device be inserted in the test socket obtain a correct reading; therefore, an open-socket reading is not feasible using this method. 7 1 V = VIC 8 14 Figure 4. Isolation Metal Around Device Inputs (J and N packages) low-level output voltage To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise results in the device low-level output being dependent on both the common-mode input voltage level as well as the differential input voltage level. When attempting correlate low-level output readings with those quoted in the electrical specifications, these two conditions should be observed. If conditions other than these are be used, please refer Figures 14 through 19 in the Typical Characteristics of this data sheet. 18 POST OFFICE BOX DALLAS, TEXAS 75265

19 input offset voltage temperature coefficient PARAMETER MEASUREMENT INFORMATION SLOS93C OCTOBER 1987 REVISED MAY 1999 Erroneous readings often result from attempts measure temperature coefficient of input offset voltage. This parameter is actually a calculation using input offset voltage measurements obtained at two different temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these measurements be performed at temperatures above freezing minimize error. full-power response Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is generally measured by moniring the disrtion level of the output, while increasing the frequency of a sinusoidal input signal until the maximum frequency is found above which the output contains significant disrtion. The full-peak response is defined as the maximum output frequency, without regard disrtion, above which full peak--peak output swing cannot be maintained. Because there is no industry-wide accepted value for significant disrtion, the full-peak response is specified in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal input determine the maximum peak--peak output of the device (the amplitude of the sinusoidal wave is increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same amplitude. The frequency is then increased until the maximum peak--peak output can no longer be maintained (Figure 5). A square wave is used allow a more accurate determination of the point at which the maximum peak--peak output is reached. test time (a) f = 1 khz (b) 1 khz < f < BOM (c) f = BOM (d) f > BOM Figure 5. Full-Power-Response Output Signal Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume, short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and lower temperatures. POST OFFICE BOX DALLAS, TEXAS

20 SLOS93C OCTOBER 1987 REVISED MAY 1999 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution 6, 7 αvio Temperature coefficient of input offset voltage Distribution 8, 9 High-level output current VOH High-level output voltage Supply voltage Free-air temperature VOL AVD Low-level output voltage Differential voltage amplification Common-mode input voltage Differential input voltage Free-air temperature Low-level output current 1, , , 19 Supply voltage 2 Free-air temperature 21 Frequency 32, 33 IIB Input bias current Free-air temperature 22 IIO Input offset current Free-air temperature 22 VIC Common-mode input voltage Supply voltage 23 IDD SR Supply current Slew rate Supply voltage 24 Free-air temperature 25 Supply voltage 26 Free-air temperature 27 Normalized slew rate Free-air temperature 28 VO(PP) Maximum peak--peak output voltage Frequency 29 B1 φmm Unity-gain bandwidth Free-air temperature 3 Supply voltage 31 Phase shift Frequency 32, 33 Phase margin Supply voltage 34 Free-air temperature 35 Load capacitance 36 Vn Equivalent input noise voltage Frequency 37 2 POST OFFICE BOX DALLAS, TEXAS 75265

21 TYPICAL CHARACTERISTICS SLOS93C OCTOBER 1987 REVISED MAY 1999 DISTRIBUTION OF TLC27M4 INPUT OFFSET VOLTAGE DISTRIBUTION OF TLC27M4 INPUT OFFSET VOLTAGE Amplifiers Tested From 6 Wafer Lots VDD = 5 V N Package Amplifiers Tested From 4 Wafer Lots VDD = 1 V N Package Percentage of Units % Percentage of Units % VIO Input Offset Voltage mv VIO Input Offset Voltage mv Figure 6 Figure 7 DISTRIBUTION OF TLC27M4 AND TLC27M9 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT DISTRIBUTION OF TLC27M4 AND TLC27M9 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT Percentage of Units % Amplifiers Tested From 6 Wafer Lots VDD = 5 V C N Package Outliers: (1) 33. µv/c Percentage of Units % Amplifiers Tested From 6 Wafer Lots VDD = 1 V 125 C N Package Outliers: (1) 34.6 µv/ C αvio Temperature Coefficient µv/ C Figure αvio Temperature Coefficient µv/ C Figure 9 POST OFFICE BOX DALLAS, TEXAS

22 SLOS93C OCTOBER 1987 REVISED MAY 1999 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT High-Level Output Voltage V V OH VDD = 3 V VDD = 4 V VID = 1 mv VDD = 5 V High-Level Output Voltage V V OH VDD = 16 V VDD = 1 V VID = 1 mv IOH High-Level Output Current ma Figure IOH High-Level Output Current ma Figure 11 4 High-Level Output Voltage V HIGH-LEVEL OUTPUT VOLTAGE SUPPLY VOLTAGE VID = 1 mv RL = 1 kω High-Level Output Voltage V VDD 1.6 VDD 1.7 VDD 1.8 VDD 1.9 VDD 2 VDD 2.1 VDD 2.2 HIGH-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE VDD = 1 V VDD = 5 V IOH = 5 ma VID = 1 ma V OH 2 V OH VDD VDD Supply Voltage V 16 VDD TA Free-Air Temperature C 125 Figure 12 Figure 13 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 22 POST OFFICE BOX DALLAS, TEXAS 75265

23 TYPICAL CHARACTERISTICS SLOS93C OCTOBER 1987 REVISED MAY 1999 LOW-LEVEL OUTPUT VOLTAGE COMMON-MODE INPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE COMMON-MODE INPUT VOLTAGE 7 5 Low-Level Output Voltage mv V OL VID = 1 mv VID = 1 V VDD = 5 V IOL = 5 ma V OL Low-Level Output Voltage mv VID = 1 mv VID = 1 V VID = 2.5 V VDD = 1 V IOL = 5 ma VIC Common-Mode Input Voltage V VIC Common-Mode Input Voltage V Figure 14 Figure 15 V OL Low-Level Output Voltage mv LOW-LEVEL OUTPUT VOLTAGE DIFFERENTIAL INPUT VOLTAGE VDD = 5 V VDD = 1 V IOL = 5 ma VIC = VID/2 V OL Low-Level Output Voltage mv LOW-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE IOL = 5 ma VID = 1 V VIC =.5 V VDD = 5 V VDD = 1 V VID Differential Input Voltage V TA Free-Air Temperature C 125 Figure 16 Figure 17 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS

24 SLOS93C OCTOBER 1987 REVISED MAY 1999 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT V OL Low-Level Output Voltage V VID = 1 V VIC =.5 V VDD = 3 V VDD = 4 V VDD = 5 V V OL Low-Level Output Voltage V VID = 1 V VIC =.5 V VDD = 1 V VDD = 16 V IOL Low-Level Output Current ma IOL Low-Level Output Current ma 3 Figure 18 Figure 19 A ÁÁAVD Large-Signal Differential Voltage Amplification V/mV 5 45 RL = 1 kω LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION SUPPLY VOLTAGE TA = 55 C 4 C C 25 C 7 C 85 C ÌÌÌÌÌ TA = 125 C AVD VD Large-Signal Differential Voltage Amplification V/mV ÁÁ LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION FREE-AIR TEMPERATURE VDD = 5 V VDD = 1 V RL = 1 kω VDD Supply Voltage V TA Free-Air Temperature C Figure 2 Figure 21 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 24 POST OFFICE BOX DALLAS, TEXAS 75265

25 TYPICAL CHARACTERISTICS SLOS93C OCTOBER 1987 REVISED MAY 1999 IIB and IIO Input Bias and Offset Currents pa INPUT BIAS CURRENT AND INPUT OFFSET CURRENT FREE-AIR TEMPERATURE VDD = 1 V VIC = 5 V See Note A IIB IIO TA Free-Air Temperature C 125 V IC Common-Mode Input Voltage V COMMON-MODE INPUT VOLTAGE POSITIVE LIMIT SUPPLY VOLTAGE VDD Supply Voltage V 16 NOTE A: The typical values of input bias current and input offset current below 5 pa were determined mathematically. Figure 22 Figure SUPPLY CURRENT SUPPLY VOLTAGE VO = VDD/2 No Load TA = 55 C 1 9 SUPPLY CURRENT FREE-AIR TEMPERATURE VO = VDD /2 No Load I DD Supply Current µa C C 25 C 7 C TA = 125 C I DD Supply Current µa VDD = 5 V VDD = 1 V VDD Supply Voltage V TA Free-Air Temperature C 125 Figure 24 Figure 25 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS

26 SLOS93C OCTOBER 1987 REVISED MAY 1999 TYPICAL CHARACTERISTICS µs SR Slew Rate V/ AV = 1 VIPP = 1 V RL = 1 kω CL = 2 pf See Figure 1 SLEW RATE SUPPLY VOLTAGE µs SR Slew Rate V/ SLEW RATE FREE-AIR TEMPERATURE VDD = 1 V VIPP = 5.5 V AV = 1 RL = 1 kω CL = 2 pf See Figure 1 VDD = 1 V VIPP = 1 V VDD Supply Voltage V VDD = 5 V VIPP = 1 V VDD = 5 V VIPP = 2.5 V TA Free-Air Temperature C 125 Figure 26 Figure 27 Normalized Slew Rate VDD = 5 V NORMALIZED SLEW RATE FREE-AIR TEMPERATURE VDD = 1 V AV = 1 VIPP = 1 V RL = 1 kω CL = 2 pf TA Free-Air Temperature C 125 Maximum Peak--Peak Output Voltage V V O(PP) MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE FREQUENCY VDD = 1 V VDD = 5 V RL = 1 kω See Figure f Frequency khz TA = 125 C TA = 55 C 1 Figure 28 Figure 29 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 26 POST OFFICE BOX DALLAS, TEXAS 75265

27 TYPICAL CHARACTERISTICS SLOS93C OCTOBER 1987 REVISED MAY 1999 B 1 Unity-Gain Bandwidth khz UNITY-GAIN BANDWIDTH FREE-AIR TEMPERATURE VDD = 5 V VI = 1 mv CL = 2 pf See Figure 3 B 1 Unity-Gain Bandwidth khz VI = 1 mv CL = 2 pf See Figure 3 UNITY-GAIN BANDWIDTH SUPPLY VOLTAGE TA Free-Air Temperature C VDD Supply Voltage V 16 Figure 3 Figure 31 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT FREQUENCY AVD Large-Signal Differential Voltage Amplification ÁÁ AVD Phase Shift VDD = 5 V RL = 1 kω Phase Shift k 1 k 1 k f Frequency Hz Figure M Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS

28 SLOS93C OCTOBER 1987 REVISED MAY 1999 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT FREQUENCY ÁÁAVD Large-Signal Differential Voltage Amplification ÁÁ ÌÌ A VD Phase Shift VDD = 1 V RL = 1 kω Phase Shift k 1 k f Frequency Hz 1 k 18 1 M Figure PHASE MARGIN SUPPLY VOLTAGE VI = 1 mv CL = 2 pf See Figure PHASE MARGIN FREE-AIR TEMPERATURE VDD = 5 V VI = 1 mv See Figure 3 φ m Phase Margin φ m Phase Margin VDD Supply Voltage V TA Free-Air Temperature C 125 Figure 34 Figure 35 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 28 POST OFFICE BOX DALLAS, TEXAS 75265

29 TYPICAL CHARACTERISTICS SLOS93C OCTOBER 1987 REVISED MAY 1999 PHASE MARGIN CAPACITIVE LOAD VDD = 5 V VI = 1 mv See Figure 3 φ m Phase Margin CL Capacitive Load pf 1 Figure 36 EQUIVALENT INPUT NOISE VOLTAGE FREQUENCY Equivalent Input Noise Voltage nv/ Hz VDD = 5 V RS = 2 Ω See Figure 2 Vn f Frequency Hz 1 Figure 37 POST OFFICE BOX DALLAS, TEXAS

30 SLOS93C OCTOBER 1987 REVISED MAY 1999 single-supply operation APPLICATION INFORMATION While the TLC27M4 and TLC27M9 perform well using dual power supplies (also called balanced or split supplies), the design is optimized for single-supply operation. This design includes an input common-mode voltage range that encompasses ground as well as an output voltage range that pulls down ground. The supply voltage range extends down 3 V (C-suffix types), thus allowing operation with supply levels commonly available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is recommended. Many single-supply applications require that a voltage be applied one input establish a reference level that is above ground. A resistive voltage divider is usually sufficient establish this reference level (see Figure 38). The low input bias current of the TLC27M4 and TLC27M9 permits the use of very large resistive values implement the voltage divider, thus minimizing power consumption. The TLC27M4 and TLC27M9 work well in conjunction with digital logic; however, when powering both linear devices and digital logic from the same power supply, the following precautions are recommended: 1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear device supply rails can fluctuate due voltage drops caused by high switching currents in the digital logic. 2. Use proper bypass techniques reduce the probability of noise-induced errors. Single capacitive decoupling is often adequate; however, high-frequency applications may require RC decoupling. VDD R4 VI R1 R2 VO VREF = R3 VDD R1 R3 VO = (VREF VI) R4 R2 V REF VREF R3 C.1 µf Figure 38. Inverting Amplifier With Voltage Reference 3 POST OFFICE BOX DALLAS, TEXAS 75265

31 single-supply operation (continued) APPLICATION INFORMATION SLOS93C OCTOBER 1987 REVISED MAY 1999 Output Logic Logic Logic Power Supply (a) COMMON SUPPLY RAILS Output Logic Logic Logic Power Supply (b) SEPARATE BYPASSED SUPPLY RAILS (preferred) Figure 39. Common Versus Separate Supply Rails input characteristics The TLC27M4 and TLC27M9 are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device malfunction. Exceeding this specified range is a common problem, especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit is specified at V DD 1 V at T A = 25 C and at V DD 1.5 V at all other temperatures. The use of the polysilicon-gate process and the careful input circuit design gives the TLC27M4 and TLC27M9 very good input offset voltage drift characteristics relative conventional metal-gate processes. Offset voltage drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. Placing the phosphorus dopant in a conducr (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with time has been calculated be typically.1 µv/month, including the first month of operation. Because of the extremely high input impedance and resulting low bias current requirements, the TLC27M4 and TLC27M9 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good practice include guard rings around inputs (similar those of Figure 4 in the Parameter Measurement Information section). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input (see Figure 4). Unused amplifiers should be connected as unity-gain followers avoid possible oscillation. noise performance The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier. The low input bias current requirements of the TLC27M4 and TLC27M9 result in a very low noise current, which is insignificant in most applications. This feature makes the devices especially favorable over bipolar devices when using values of circuit impedance greater than 5 kω, since bipolar devices exhibit greater noise currents. POST OFFICE BOX DALLAS, TEXAS

32 SLOS93C OCTOBER 1987 REVISED MAY 1999 noise performance (continued) APPLICATION INFORMATION VI VI VO VO VO VI (a) NONINVERTING AMPLIFIER output characteristics (b) INVERTING AMPLIFIER Figure 4. Guard-Ring Schemes (c) UNITY-GAIN AMPLIFIER The output stage of the TLC27M4 and TLC27M9 is designed sink and source relatively high amounts of current (see typical characteristics). If the output is subjected a short-circuit condition, this high current capability can cause device damage under certain conditions. Output current capability increases with supply voltage. All operating characteristics of the TLC27M4 and TLC27M9 were measured using a 2-pF load. The devices drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many cases, adding a small amount of resistance in series with the load capacitance alleviates the problem. (a) CL = 2 pf, RL = NO LOAD (b) CL = 17 pf, RL = NO LOAD 2.5 V VO VI CL f = 1 khz VIPP = 1 V 2.5 V (d) TEST CIRCUIT (c) CL = 19 pf, RL = NO LOAD Figure 41. Effect of Capacitive Loads and Test Circuit 32 POST OFFICE BOX DALLAS, TEXAS 75265

33 output characteristics (continued) APPLICATION INFORMATION SLOS93C OCTOBER 1987 REVISED MAY 1999 Although the TLC27M4 and TLC27M9 possess excellent high-level output voltage and current capability, methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup resisr (R P ) connected from the output the positive supply rail (see Figure 42). There are two disadvantages the use of this circuit. First, the NMOS pulldown transisr N4 (see equivalent schematic) must sink a comparatively large amount of current. In this circuit, N4 behaves like a linear resisr with an on-resistance between approximately 6 Ω and 18 Ω, depending on how hard the operational amplifier input is driven. With very low values of R P, a voltage offset from V at the output occurs. Second, pullup resisr R P acts as a drain load N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying the output current. VDD C VI R1 R2 IP IF IL RP RL VO Rp = V DD VO IF IL IP IP = Pullup current required by the operational amplifier (typically 5 µa) VO Figure 42. Resistive Pullup Increase V OH Figure 43. Compensation for Input Capacitance feedback Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads (discussed previously) and ignoring stray input capacitance. A small-value capacir connected in parallel with the feedback resisr is an effective remedy (see Figure 43). The value of this capacir is optimized empirically. electrostatic discharge protection latch-up The TLC27M4 and TLC27M9 incorporate an internal electrostatic discharge (ESD) protection circuit that prevents functional failures at voltages up 2 V as tested under MIL-STD-883C, Method Care should be exercised, however, when handling these devices, as exposure ESD may result in the degradation of the device parametric performance. The protection circuit also causes the input bias currents be temperature-dependent and have the characteristics of a reverse-biased diode. Because CMOS devices are susceptible latch-up due their inherent parasitic thyrisrs, the TLC27M4 and TLC27M9 inputs and outputs were designed withstand 1-mA surge currents without sustaining latch-up; however, techniques should be used reduce the chance of latch-up whenever possible. Internal protection diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply voltage by more than 3 mv. Care should be exercised when using capacitive coupling on pulse generars. Supply transients should be shunted by the use of decoupling capacirs (.1 µf typical) located across the supply rails as close the device as possible. POST OFFICE BOX DALLAS, TEXAS

34 SLOS93C OCTOBER 1987 REVISED MAY 1999 APPLICATION INFORMATION latch-up (continued) The current path established if latch-up occurs is usually between the positive supply rail and ground; it can be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the forward resistance of the parasitic thyrisr and usually results in the destruction of the device. The chance of latch-up occurring increases with increasing temperature and supply voltages. 47 kω 1N V 1 kω 1 kω 47 kω 1/4 TLC27M4 VO R2 68 kω 1 µf 1 kω R1 68 kω C1 2.2 nf C2 2.2 nf NOTE: VOPP 2 V 1 fo = 2π R1R2C1C2 Figure 44. Wien Oscillar IS VI 5 V 1/4 TLC27M9 2N3821 R NOTE: VI = V 3 V IS = V I R Figure 45. Precision Low-Current Sink 34 POST OFFICE BOX DALLAS, TEXAS 75265