TLC555, TLC555Y LinCMOS TIMERS

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1 ery Low Power Consumption mw Typ at DD = 5 Capable of Operation in Astable Mode CMOS Output Capable of Swinging Rail to Rail High Output-Current Capability Sink 00 ma Typ Source 0 ma Typ Output Fully Compatible With CMOS, TTL, and MOS Low Supply Current Reduces Spikes During Output Transitions Single-Supply Operation From 2 to 5 Functionally Interchangeable With the NE555; Has Same Pinout ESD Protection Exceeds 2000 Per MIL-STD-3C, Method TRIG OUT D, DB, JG, P, OR PW PACKAGE (TOP IEW) GND TRIG OUT RESET FK PACKAGE (TOP IEW) GND DD DD DISCH THRES CONT DISCH THRES description The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS process. The timer is fully compatible with CMOS, TTL, and RESET MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage. Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering. While the CMOS output is capable of sinking over 00 ma and sourcing over 0 ma, the TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555. The TLC555C is characterized for operation from 0 C to 70 C. The TLC555I is characterized for operation from 40 C to 5 C. The TLC555M is characterized for operation over the full military temperature range of 55 C to 25 C. CONT No internal connection This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 k according to MIL-STD-3C, Method 305; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. LinCMOS is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX DALLAS, TEXAS Copyright 997, Texas Instruments Incorporated

2 TA 0 C to 70 C 40 C to 5 C 55 C to 25 C DD RANGE SMALL OUTLINE (D) AAILABLE OPTIONS PACKAGED DEICES SSOP (DB) CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) TSSOP (PW) 2 to 5 TLC555CD TLC555CDBLE TLC555CP TLC555CPWLE CHIP FORM (Y) 3 to 5 TLC555ID TLC555IP TLC555Y 5 to 5 TLC555MD TLC555MFK TLC555MJG TLC555MP The D package is available taped and reeled. Add the R suffix to device type (e.g., TLC555CDR). The DB and PW packages are only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC555CDBLE). Chips are tested at 25 C. RESET OLTAGE functional block diagram TRIGGER OLTAGE FUTION TABLE THRESHOLD OLTAGE OUTPUT DISCHARGE SWITCH <MIN Irrelevant Irrelevant L On >MAX <MIN Irrelevant H Off >MAX >MAX >MAX L On >MAX >MAX <MIN As previously established For conditions shown as MIN or MAX, use the appropriate value specified under electrical characteristics. CONT 5 DD RESET 4 THRES 6 R R R 3 OUT S R TRIG 2 GND Pin numbers are for all packages except the FK package. RESET can override TRIG, which can override THRES. R 7 DISCH 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 TLC555Y chip information This chip, when properly assembled, displays characteristics similar to the TLC555. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CONT (5) DD () RESET (4) (6) THRES R R R (3) OUT 50 R S TRIG (2) R () GND (7) DISCH 64 RESET can override TRIG, which can override THRES. CHIP THICKNESS: 5 TYPICAL BONDING PADS: 4 4 MINIMUM TJmax = 50 C TOLERAES ARE ± 0%. ALL DIMENSIONS ARE IN MILS. PIN () IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. POST OFFICE BOX DALLAS, TEXAS

4 4 POST OFFICE BOX DALLAS, TEXAS equivalent schematic (each channel) CONT THRES COMPONENT COUNT Transistors Resistors 39 5 DD OUT LinCMOS TIMERS Template Release Date: 7 94 DISCH GND TRIG RESET

5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, DD (see Note ) Input voltage range, I (any input) to DD Sink current, discharge or output ma Source current, output, I O ma Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, T A : C-suffix C to 70 C I-suffix C to 5 C M-suffix C to 25 C Storage temperature range C to 50 C Case temperature for 60 seconds: FK package C Lead temperature,6 mm (/6 inch) from case for 60 seconds: JG package C Lead temperature,6 mm (/6 inch) from case for 0 seconds: D, DB, P, or PW package C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : All voltage values are with respect to network GND. DISSIPATION RATING TABLE PACKAGE TA 25 C POWER RATING 725 mw 525 mw 375 mw 050 mw 000 mw 525 mw DERATING FACTOR ABOE TA = 25 C 5. mw/ C 4.2 mw/ C.0 mw/ C.4 mw/ C.0 mw/ C 4.2 mw/ C TA = 70 C POWER RATING TA = 5 C POWER RATING 377 mw 273 mw 75 mw 546 mw 520 mw 273 mw TA = 25 C POWER RATING 45 mw 05 mw 275 mw 20 mw 200 mw 05 mw D DB FK JG P PW 464 mw 336 mw 0 mw 672 mw 640 mw 336 mw recommended operating conditions MIN MAX UNIT Supply voltage, DD 2 5 TLC555C 0 70 Operating free-air temperature range, TA TLC555I 40 5 C TLC555M POST OFFICE BOX DALLAS, TEXAS

6 electrical characteristics at specified free-air temperature, DD = 2 for TLC555C, DD = 3 for TLC555I IT IIT I(TRIG) II(TRIG) I(RESET) II(RESET) PARAMETER Threshold voltage Threshold current Trigger voltage Trigger current Reset voltage Reset current Control voltage (open circuit) as a percentage of supply voltage Discharge switch on-stage voltage TEST CONDITIONS IOL =ma TLC555C TLC555I TA MIN TYP MAX MIN TYP MAX 25 C Full range C 0 0 MAX C Full range C 0 0 MAX C Full range C 0 0 MAX MAX 66.7% 66.7% 25 C Full range Discharge switch off-stage 25 C current MAX C OH High-level output voltage IOH = 300 µa Full range OL Low-level output voltage IOL =ma IDD Supply current See Note 2 25 C Full range C Full range Full range is 0 C to 70 C for the TLC555C and 40 C to 5 C for the TLC555I. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG. UNIT pa pa pa na µa 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 electrical characteristics at specified free-air temperature, DD = 5 PARAMETER TEST CONDITIONS TLC555C TLC555I TLC555M T A MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT IT Threshold voltage 25 C Full range IIT Threshold current 25 C MAX pa I(TRIG) Trigger voltage 25 C Full range I I(TRIG) Trigger current 25 C MAX pa I(RESET) Reset voltage 25 C Full range I I(RESET) Reset current 25 C MAX pa Control voltage (open circuit) as a percentage of supply voltage MAX 66.7% 66.7% 66.7% Discharge switch 25 C I =0mA on-state voltage OL Full range Discharge switch 25 C off-state current MAX na OH OL High-level output voltage Low-level output voltage I OH = ma I OL =ma I OL =5mA I OL =32mA 3.2 I DD Supply current See Note 2 25 C Full range C Full range C Full range C Full range C Full range Full range is 0 C to 70 C the for TLC555C, 40 C to 5 C for the TLC555I, and 55 C to 25 C for the TLC555M. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. µa POST OFFICE BOX DALLAS, TEXAS

8 electrical characteristics at specified free-air temperature, DD = 5 IT I IT I(TRIG) I I(TRIG) I(RESET) I I(RESET) PARAMETER Threshold voltage Threshold current Trigger voltage Trigger current Reset voltage Reset current Control voltage (open circuit) as a percentage of supply voltage Discharge switch on-state voltage TEST CONDITIONS I OL = 00 ma T A TLC555C TLC555I TLC555M MIN TYP MAX MIN TYP MAX MIN TYP MAX 25 C Full range C MAX C Full range C MAX C Full range C MAX MAX 66.7% 66.7% 66.7% 25 C Full range... Discharge switch 25 C off-state current MAX UNIT pa pa pa na OH OL High-level output voltage Low-level output voltage I OH = 0 ma I OH = 5 ma I OH = ma I OL = 00 ma I OL =50mA I OL =0mA 25 C Full range C Full range C Full range C Full range C Full range C Full range C I DD Supply current See Note 2 µa Full range Full range is 0 C to 70 C for TLC555C, 40 C to 5 C for TLC555I, and 55 C to 25 C for TLC555M. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. POST OFFICE BOX DALLAS, TEXAS 75265

9 operating characteristics, DD = 5, T A = 25 C (unless otherwise noted) tr tf fmax PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Initial error of timing interval Supply voltage sensistivity of timing interval Output pulse rise time Output pulse fall time Maximum frequency in astable mode DD = 5 to 5, RA A = RB B = kω to 00 kω, % 3% CT = 0. µf, See Note %/ RL =0MΩ MΩ, RA = 470 Ω, CT = 200 pf, CL =0pF RB = 200 Ω, See Note ns.2 2. MHz Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. NOTE 3: RA, RB, and CT are as defined in Figure. electrical characteristics at DD = 5, T A = 25 C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IT Threshold voltage IIT Threshold current 0 pa I(TRIG) Trigger voltage II(TRIG) Trigger current 0 pa I(RESET) Reset voltage II(RESET) Reset current 0 pa Control voltage (open circuit) as a percentage of supply voltage 66.7% Discharge switch on-state voltage IOL = 0 ma Discharge switch off-state current 0. na OH High-level output voltage IOH = ma IOL = ma OL Low-level output voltage IOL = 5 ma IOL = 3.2 ma IDD Supply current See Note µa NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. POST OFFICE BOX DALLAS, TEXAS

10 TYPICAL CHARACTERISTICS Ω Discharge Switch On-State Resistance DISCHARGE SWITCH ON-STATE RESISTAE vs FREE-AIR TEMPERATURE DD = 2, IO = ma DD = 5, IO = 0 ma DD = 5, IO = 00 ma TA Free-Air Temperature C t PHL, t PLH Propagation Delay Times ns PROPAGATION DELAY TIMES TO DISCHARGE OUTPUT FROM TRIGGER AND THRESHOLD SHORTED TOGETHER vs SUPPLY OLTAGE DD Supply oltage IO(on) ma CL 0 TA = 25 C tphl tplh 20 Figure The effects of the load resistance on these values must be taken into account separately. Figure 2 0 POST OFFICE BOX DALLAS, TEXAS 75265

11 APPLICATION INFORMATION 0. µf tc(h) tc(l) RA RB CT 0. µf 5 4 CONT RESET DD 7 TLC555 DISCH 6 OUT THRES 2 TRIG GND 3 RL Output CL DD 2/3 DD /3 DD GND tphl tplh Pin numbers shown are for all packages except the TRIGGER AND THRESHOLD OLTAGE WAEFORM FK package. CIRCUIT Figure 3. Astable Operation Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor C T charges through R A and R B to the threshold voltage level (approximately 0.67 DD ) and then discharges through R B only to the value of the trigger voltage level (approximately 0.33 DD ). The output is high during the charging cycle (t c(h) ) and low during the discharge cycle (t c(l) ). The duty cycle is controlled by the values of R A, R B, and C T as shown in the equations below. t c(h) C T (R A R B )In2 (In ) t c(l) C T R B In 2 Period t c(h) t c(l) C T (R A 2R B )In2 Output driver duty cycle t c(l) t c(h) t c(l) R B R A 2R B Output waveform duty cycle t c(h) t c(h) t c(l) R B R A 2R B The 0.-µF capacitor at CONT in Figure 3 decreases the period by about 0%. The formulas shown above do not allow for any propagation delay times from the TRIG and THRES inputs to DISCH. These delay times add directly to the period and create differences between calculated and actual values that increase with frequency. In addition, the internal on-state resistance r on during discharge adds to R B to provide another source of timing error in the calculation when R B is very low or r on is very high. POST OFFICE BOX DALLAS, TEXAS 75265

12 APPLICATION INFORMATION The equations below provide better agreement with measured values. t t c(h) C (R T A R B )In* 3 exp. PLH C (R r T B on.* t ) PHL t c(l) C T (R B r on )In* 3 exp. t PHL C T (R A R B ).* t PLH These equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and In 3 at extremely high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic terms can be substituted t with good results. Duty cycles less than 50% c(h) require that t c(h) < and possibly R A r on. These t c(h) t t c(l) c(l) conditions can be difficult to obtain. In monostable applications, the trip point on TRIG can be set by a voltage applied to CONT. An input voltage between 0% and 0% of the supply voltage from a resistor divider with at least 500-µA bias provides good results. 2 POST OFFICE BOX DALLAS, TEXAS 75265

13 D (R-PDSO-G**) 4 PIN SHOWN MECHANICAL DATA PLASTIC SMALL-OUTLINE PACKAGE (,27) (0,5) 0.04 (0,35) 0.00 (0,25) M PINS ** DIM A MAX A MIN 0.97 (5,00) 0.9 (4,0) (,75) (,55) (0,00) 0.36 (9,0) 0.57 (4,00) 0.50 (3,) (6,20) 0.22 (5,0) 0.00 (0,20) NOM 7 Gage Plane A 0.00 (0,25) (,2) 0.06 (0,40) Seating Plane (,75) MAX 0.00 (0,25) (0,0) (0,0) / D 0/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed (0,5). D. Falls within JEDEC MS-02 POST OFFICE BOX DALLAS, TEXAS

14 DB (R-PDSO-G**) 2 PIN SHOWN MECHANICAL INFORMATION PLASTIC SMALL-OUTLINE PACKAGE 0,65 0,3 0,22 0,5 M 2 5 5,60 5,00,20 7,40 0,5 NOM Gage Plane 4 0,25 A 0,03 0,63 2,00 MAX 0,05 MIN Seating Plane 0,0 DIM PINS ** A MAX 3,30 6,50 6,50 7,50,50 0,50 0,50 2,90 A MIN 2,70 5,90 5,90 6,90 7,90 9,90 9,90 2, / C 0/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-50 4 POST OFFICE BOX DALLAS, TEXAS 75265

15 FK (S-CQCC-N**) 2 TERMINAL SHOWN MECHANICAL INFORMATION LEADLESS CERAMIC CHIP CARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (,69) 0.35 (9,09) (7,0) 0.35 (9,09) A SQ B SQ (,23) (6,26) (,7) 0.93 (23,3).4 (2,99) 0.45 (,63) (6,76) 0.76 (9,32) (24,43).65 (29,59) (0,3) (2,5) (2,5) 0.50 (2,6).047 (26,6) 0.45 (,63) (4,22) (4,22) 0.5 (2,).063 (27,0) (0,5) 0.00 (0,25) 0.00 (2,03) (,63) (0,5) 0.00 (0,25) (,40) (,4) (,4) (0,9) 0.02 (0,7) (0,54) (,27) (,4) (0,9) / D 0/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004 POST OFFICE BOX DALLAS, TEXAS

16 JG (R-GDIP-T) MECHANICAL INFORMATION CERAMIC DUAL-IN-LINE PACKAGE (0,20) (9,00) (7,) (6,22) (,65) (,4) (0,5) MIN 0.30 (7,7) (7,37) (5,0) MAX Seating Plane 0.30 (3,30) MIN (,60) 0.05 (0,3) 0.00 (2,54) (0,5) 0.05 (0,3) 0.04 (0,36) 0.00 (0,20) /C 0/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. E. Falls within MIL-STD-35 GDIP-T 6 POST OFFICE BOX DALLAS, TEXAS 75265

17 P (R-PDIP-T) MECHANICAL DATA PLASTIC DUAL-IN-LINE PACKAGE (0,60) (9,02) (6,60) (6,0) (,7) MAX (0,5) MIN 0.30 (7,7) (7,37) (5,0) MAX Seating Plane 0.25 (3,) MIN 0.00 (2,54) (0,53) 0.05 (0,3) 0.00 (0,25) M 0.00 (0,25) NOM / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00 POST OFFICE BOX DALLAS, TEXAS

18 PW (R-PDSO-G**) 4 PIN SHOWN MECHANICAL INFORMATION PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,0 M 0,9 4 4,50 4,30 6,60 6,20 0,5 NOM Gage Plane A 7 0 0,25 0,75 0,50 Seating Plane,20 MAX 0,05 MIN 0,0 DIM PINS ** A MAX 3,0 5,0 5,0 6,60 7,90 9,0 A MIN 2,90 4,90 4,90 6,40 7,70 9, / E 0/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-53 POST OFFICE BOX DALLAS, TEXAS 75265

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