NE555, NE555Y, SA555, SE555, SE555C PRECISION TIMERS

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1 Timing From Microseconds to Hours Astable or Monostable Operation Adjustable Duty Cycle TTL-Compatible Output Can Sink or Source up to 00 ma Functionally Interchangeable With the Signetics NE, SA, SE, SEC; Have Same Pinout SEC FOM TI IS NOT ECOMMENDED FO NEW DESIGNS D, JG, O P PACKAGE (TOP IEW) 8 FK PACKAGE (TOP IEW) CC description These devices are precision monolithic timing circuits capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle may be independently controlled with two external resistors and a single external capacitor No internal connection The threshold and trigger levels are normally two-thirds and one-third, respectively, of CC. These levels can be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. can override all other inputs and can be used to initiate a new timing cycle. When goes low, the flip-flop is reset and the output goes low. Whenever the output is low, a low-impedance path is provided between and ground. The output circuit is capable of sinking or sourcing current up to 00 ma. Operation is specified for supplies of to. With a - supply, output levels are compatible with TTL inputs. The NE is characterized for operation from 0 C to 0 C. The SA is characterized for operation from 0 C to 8 C. The SE and SEC are characterized for operation over the full military range of C to C. AAILABLE OPTIONS PACKAGE TA max SMALL LINE CHIP CAIE CEAMIC DIP PLASTIC DIP = (D) (FK) (J) (P) 0 C to 0 C. NED NEP 0 C to 8 C. SAD SAP C to C 0.. SED SECD SEFK SECFK SEJG SECJG The D package is available taped and reeled. Add the suffix to the device type (e.g., NED). SEP SECP CHIP FOM (Y) NEY PODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Instruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS

2 FUTION TABLE GE OLTAGE HOLD OLTAGE PUT AGE SWITCH Low Irrelevant Irrelevant Low On High < / DD Irrelevant High Off High > / DD > / DD Low On High > / DD < / DD As previously established oltage levels shown are nominal. functional block diagram 8 S Î can override, which can override. Pin numbers shown are for the D, JG, and P packages only. POST OFFICE BOX 0 DALLAS, TEXAS

3 chip information These chips, properly assembled, display characteristics similar to the NE (see electrical table for NEY). Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (8) () () () () () () S () () () () () () (8) CHIP THICKNESS: TYPICAL BONDING PADS: MINIMUM () () TJ max = 0 C TOLEAES AE ± 0% ALL DIMENSIONS AE IN MILS PIN () INTENALLY CONNECTED TO BACKSIDE OF CHIP POST OFFICE BOX 0 DALLAS, TEXAS

4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) NOTE : Supply voltage, CC (See Note ) Input voltage (,,, and ) CC Output current ± ma Continuous total dissipation See Dissipation ating Table Operating free-air temperature range: NE C to 0 C SA C to 8 C SE, SEC C to C Storage temperature range C to 0 C Case temperature for 0 seconds: FK package C Lead temperature, mm (/ inch) from case for 0 seconds: D or P package C Lead temperature, mm (/ inch) from case for 0 seconds: JG package C All voltage values are with respect to network ground terminal. PACKAGE TA C POWE ATING DISSIPATION ATING TABLE DEATING FACTO ABOE TA = C TA = 0 C POWE ATING TA = 8 C POWE ATING TA = C POWE ATING D mw.8 mw/ C mw mw N/A FK mw.0 mw/ C 880 mw mw mw JG (SE, SEC) 00 mw 8. mw/ C mw mw 0 mw JG (SA, NEC) 8 mw. mw/ C 8 mw 9 mw N/A P 000 mw 8.0 mw/ C 0 mw 0 mw N/A recommended operating conditions NE SA SE SEC MIN MAX MIN MAX MIN MAX MIN MAX UNIT Supply voltage, Input voltage (,,, and ) Output current ±00 ±00 ±00 ±00 ma Operating free-air temperature, TA C POST OFFICE BOX 0 DALLAS, TEXAS

5 electrical characteristics, CC = to, T A = C (unless otherwise noted) PAAMETE voltage level NE, SA, SE TEST CONDITIONS SEC MIN TYP MAX MIN TYP MAX = =..... current (see Note ) na voltage level =.8... = current at µa voltage level current at at switch off-state current na voltage (open circuit) Low-level output voltage High-level output voltage Supply current = = = = = IOL = 0 ma IOL = 0 ma IOL = 00 ma.. IOL = 00 ma.. IOL = ma IOL = 8 ma IOH = 00 ma... IOH = 00 ma.. = IOH = 00 ma... CC = 0 0 Output low, No load CC = CC = Output high, No load CC = UNIT ma ma NOTE : This parameter influences the maximum value of the timing resistors A and B in the circuit of Figure. For example, when =, the maximum value is = A + B. MΩ, and for =, the maximum value is 0 MΩ. operating characteristics, CC = and PAAMETE Initial error of timing interval Each timer, monostable Each timer, astable TEST CONDITIONS TA = C Temperature coefficient Each timer, monostable of timing interval TA = MIN to MAX Each timer, astable Supply voltage sensitivity Each timer, monostable = C of timing interval TA Each timer, astable SE NE, SA, SEC MIN TYP MAX MIN TYP MAX 0.%.% % %.%.% Output pulse rise time CL = pf, Output pulse fall time TA = C UNIT ppm/ C For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. alues specified are for a device in a monostable circuit similar to Figure 9, with component values as follow: A = kω to 00 kω, C = 0. µf. alues specified are for a device in an astable circuit similar to Figure, with component values as follow: A = kω to 00 kω, C = 0. µf. %/ ns POST OFFICE BOX 0 DALLAS, TEXAS

6 electrical characteristics, CC = to, T A = C (unless otherwise noted) voltage level PAAMETE TEST CONDITIONS MIN TYP MAX UNIT = =... current (see Note ) 0 0 na voltage level =.. =... current at 0 0. µa voltage level current at at switch off-state current 0 00 na voltage (open circuit) Low-level output voltage High-level output voltage Supply current NOTE : = 9 0 =.. = = = IOL = 0 ma IOL = 0 ma IOL = 00 ma. IOL = 00 ma. IOL = ma IOL = 8 ma IOH = 00 ma.. ma IOH = 00 ma. = IOH = 00 ma.. Output low, No load Output high, No load = 0 = = 9 = This parameter influences the maximum value of the timing resistors A and B in the circuit of Figure. For example, when =, the maximum value is = A + B. MΩ, and for =, the maximum value is 0 MΩ operating characteristics, CC = and, T A = C (unless otherwise noted) Initial error of timing interval Supply voltage sensitivity of timing interval PAAMETE ma TEST MIN TYP MAX UNIT CONDITIONS Each timer, monostable % % Each timer, astable.% Each timer, monostable Each timer, astable 0. Output pulse rise time CL =pf ns Output pulse fall time Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. alues specified are for a device in a monostable circuit similar to Figure 9, with component values as follow: A = kω to 00 kω, C = 0. µf. alues specified are for a device in an astable circuit similar to Figure, with component values as follow: A = kω to 00 kω, C = 0. µf. %/ POST OFFICE BOX 0 DALLAS, TEXAS

7 TYPICAL CHAACTEISTICS LOW-LEEL PUT OLTAGE LOW-LEEL PUT CUENT 0ÏÏÏÏ = 0 LOW-LEEL PUT OLTAGE LOW-LEEL PUT CUENT = 0 Low-Level Output oltage TA = C TA = C TA = C Low-Level Output oltage ÏÏÏÏ TA = C ÏÏÏÏ TA= C TA = C OL 0.0 OL IOL Low-Level Output Current ma Figure IOL Low-Level Output Current ma Figure Low-Level Output oltage OL LOW-LEEL PUT OLTAGE LOW-LEEL PUT CUENT ÏÏÏÏ = TA = C TA = C TA = C CC OH oltage Drop DOP BETWEEN SUPPLY OLTAGE AND PUT HIGH-LEEL PUT CUENT.0 TA = C ÏÏÏÏ TA = C TA = C IOL Low-Level Output Current ma 0. 0 = to IOH High-Level Output Current ma 00 Figure Figure Data for temperatures below 0 C and above 0 C are applicable for SE circuits only. POST OFFICE BOX 0 DALLAS, TEXAS

8 TYPICAL CHAACTEISTICS SUPPLY CUENT SUPPLY OLTAGE NOMALIZED PUT PULSE DUATION (MONOSTABLE OPEATION) SUPPLY OLTAGE Supply Current ma ICC Output Low, No Load TA = C TA = C TA = C Pulse Duration elative to alue at = Supply oltage Figure Supply oltage Figure 0 Pulse Duration elative to alue at T A = C NOMALIZED PUT PULSE DUATION (MONOSTABLE OPEATION) FEE-AI TEMPEATUE = 0 Propagation Delay Time ns t PD POPAGATION DELAY TIME LOWEST OLTAGE LEEL OF GE PULSE TA = C TA = 0 C TA = C TA = 0 C TA = C TA Free-Air Temperature C Figure x 0. x 0. x 0. x Lowest oltage Level of Trigger Pulse Figure 8 Data for temperatures below 0 C and above 0 C are applicable for SE circuits only. 8 POST OFFICE BOX 0 DALLAS, TEXAS

9 APPLICATION INFOMATION monostable operation For monostable operation, any of these timers may be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to sets the flip-flop (Q goes low), drives the output high, and turns off Q. Capacitor C is then charged through A until the voltage across the capacitor reaches the threshold voltage of input. If has returned to a high level, the output of the threshold comparator will reset the flip-flop (Q goes high), drive the output low, and discharge C through Q. ( to ) A = 9. kω CL = 0.0 µf L = kω See Figure 9 Input A 8 L Output oltage /div Input oltage Output oltage Capacitor oltage Pin numbers shown are for the D, JG, and P packages. Figure 9. Circuit for Monostable Operation Monostable operation is initiated when voltage falls below the trigger threshold. Once initiated, the sequence ends only if is high at the end of the timing interval. Because of the threshold level and saturation voltage of Q, the output pulse duration is approximately t w =. A C. Figure is a plot of the time constant for various values of A and C. The threshold levels and charge rates are both directly proportional to the supply voltage, CC. The timing interval is therefore independent of the supply voltage, so long as the supply voltage is constant during the time interval. Applying a negative-going trigger pulse simultaneously to and during the timing interval discharges C and re-initiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is low. To prevent false triggering, when is not used, it should be connected to CC. Output Pulse Duration s tw Time 0. ms/div Figure 0. Typical Monostable Waveforms A = 0 MΩ A = MΩ 0.0 A = 0 kω A = kω 0. C Capacitance µf A = 00 kω Figure. Output Pulse Duration Capacitance 0 00 POST OFFICE BOX 0 DALLAS, TEXAS 9

10 astable operation APPLICATION INFOMATION As shown in Figure, adding a second resistor, B, to the circuit of Figure 9 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C will charge through A and B and then discharge through B only. The duty cycle may be controlled, therefore, by the values of A and B. This astable connection results in capacitor C charging and discharging between the threshold-voltage level ( 0. CC ) and the trigger-voltage level ( 0. CC ). As in the monostable circuit, charge and discharge times (and therefore the frequency and duty cycle) are independent of the supply voltage. A B C 0.0 µf ( to ) Open (see Note A) 8 L Output oltage /div t H tl A = kω L = kω ÏÏÏÏ B = kω See Figure ÏÏÏÏ C = 0. µf Output oltage Pin numbrs shown are for the D, JG, and P packages. NOTE A: Decoupling voltage to ground with a capacitor may improve operation. This should be evaluated for individual applications. Figure. Circuit for Astable Operation Capacitor oltage Time 0. ms/div Figure. Typical Astable Waveforms 0 POST OFFICE BOX 0 DALLAS, TEXAS

11 APPLICATION INFOMATION Figure shows typical waveforms generated during astable operation. The output high-level duration t H and low-level duration t L may be calculated as follows: 00 k A + B = kω t H 0.9 ( A B) C t L 0.9 ( B) C Other useful relationships are shown below. period t H t L 0.9 ( A B )C frequency. ( A B )C Output driver duty cycle Output waveform duty cycle t H Low-o- t high ratio t L t H missing-pulse detector t L t H t L t H t L B A B B A B B A B f Free-unning Frequency Hz 0 k k 00 0 A + B = MΩ A + B = 0 MΩ A + B = 0 kω C Capacitance µf A + B = 00 kω 0 Figure. Free-unning Frequency The circuit shown in Figure may be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. The timing interval of the monostable circuit is continuously retriggered by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse as illustrated in Figure. 00 Input 0.0 µf ( to ) 8 L A ÏÏÏ Output C oltage /div = A = kω C = 0. µf See Figure Input oltage Ï Output oltage AT Capacitor oltage Pin numbers shown are shown for the D, JG, and P packages. Figure. Circuit for Missing Pulse Detector Time 0. ms/div Figure. Circuit for Missing Pulse Detector POST OFFICE BOX 0 DALLAS, TEXAS

12 frequency divider APPLICATION INFOMATION By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency divider. Figure illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. = A = 0 Ω C = 0.0 µf See Figure 9 oltage /div Input oltage Output oltage Capacitor oltage Time 0. ms/div Figure. Divide-By-Three Circuit Waveforms pulse-width modulation The operation of the timer may be modified by modulating the internal threshold and trigger voltages, which is accomplished by applying an external voltage (or current) to. Figure 8 shows a circuit for pulse-width modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the threshold voltage. Figure 9 illustrates the resulting output pulse-width modulation. While a sine-wave modulation signal is illustrated, any wave shape could be used. POST OFFICE BOX 0 DALLAS, TEXAS

13 APPLICATION INFOMATION Clock Input Modulation Input (see Note A) ( to ) 8 L A Output C oltage /div ÏÏ Modulation Input oltage ÏÏ Clock Input oltage A = kω C = 0.0 µf L = kω See Figure 8 Output oltage Pin numbers shown are for the D, JG, and P packages only. NOTE A: The modulating signal may be direct or capacitively coupled to. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Figure 8. Circuit for Pulse-Width Modulation Capacitor oltage Time 0. ms/div Figure 9. Pulse-Width Modulation Waveforms pulse-position modulation As shown in Figure 0, any of these timers may be used as a pulse-position modulator. This application modulates the threshold voltage, and thereby the time delay, of a free-running oscillator. Figure illustrates a triangular-wave modulation signal for such a circuit; however, any wave shape could be used. ( to ) 8 L A Ï A = kω Ï B = 00 Ω Ï L = kω See Figure 0 Modulation Input (see Note A) B C Output oltage /div ÏÏÏ Modulation Input oltage Ï Output oltage Pin numbers shown are for the D, JG, and P packages only. NOTE A: The modulating signal may be direct or capacitively coupled to. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Figure 0. Circuit for Pulse-Position Modulation Ï Capacitor oltage Time 0. ms/div Figure. Pulse-Position-Modulation Waveforms POST OFFICE BOX 0 DALLAS, TEXAS

14 APPLICATION INFOMATION sequential timer S 0.0 µf 8 CA A kω 0.00 µf 0.0 µf 8 CB B kω 0.00 µf 0.0 µf 8 CC C CA = 0 µf A = 00 kω Output A CB =. µf B = 00 kω Output B CC =. µf C = 00 kω Output C S closes momentarily at t = 0. Pin numbers shown are for the D, JG, and P packages only. Figure. Sequential Timer Circuit Many applications, such as computers, require signals for initializing conditions during start-up. Other applications, such as test equipment, require activation of test signals in sequence. These timing circuits may be connected to provide such sequential control. The timers may be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure illustrates a sequencer circuit with possible applications in many systems, and Figure shows the output waveforms. oltage /div See Figure ÏÏ t Output A wa ÏÏÏ Output B twa =. ACA ÏÏÏ t wb twb =. BCB Output C twc twc =. CCC ÏÏÏ t = 0 t Time s/div Figure. Sequential Timer Waveforms POST OFFICE BOX 0 DALLAS, TEXAS

15 IMPOTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CETAIN APPLICATIONS USING SEMICONDUCTO PODUCTS MAY INOLE POTENTIAL ISKS OF DEATH, PESONAL INJUY, O SEEE POPETY O ENIONMENTAL DAMAGE ( CITICAL APPLICATIONS ). TI SEMICONDUCTO PODUCTS AE NOT DESIGNED, AUTHOIZED, O WAANTED TO BE SUITABLE FO USE IN LIFE-SUPPOT DEICES O SYSTEMS O OTHE CITICAL APPLICATIONS. ILUSION OF TI PODUCTS IN SUCH APPLICATIONS IS UNDESTOOD TO BE FULLY AT THE CUSTOME S ISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 998, Texas Instruments Incorporated

NE555, NE555Y, SA555, SE555, SE555C PRECISION TIMERS

NE555, NE555Y, SA555, SE555, SE555C PRECISION TIMERS NE, NEY, SA, SE, SEC SLFS0 D9, SEPTEMBE 9 EISED FEBUAY 99 Timing From Microseconds to Hours Astable or Monostable Operation Adjustable Duty Cycle TTL-Compatible Output Can Sink or Source up to 00 ma Functionally