TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

Size: px

Start display at page:

Download "TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS"

Jerome Lambert
6 years ago
Views:

1 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVETES Easily Interfaced to Microprocessors On-Chip Data Latches Monotonic Over the Entire A/D Conversion ange Segmented High-Order Bits Ensure Low-Glitch Output Interchangeable With Analog Devices AD7524, PMI PM-7524, and Micro Power Systems MP7524 Fast Control Signaling for Digital Signal-Processor Applications Including Interface With TMS320 CMOS Technology description KEY PEFOMANCE SPECIFICATIONS esolution Linearity error Power dissipation at VDD = 5 V Setting time Propagation delay time 8 Bits /2 LSB Max 5 mw Max 00 ns Max 80 ns Max The TLC7524C, TLC7524E, and TLC7524I are CMOS, 8-bit, digital-to-analog converters (DACs) designed for easy interface to most popular microprocessors. SLAS06C SEPTEMBE 986 EVISED NOVEMBE 998 The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits, which produce the highest glitch impulse. The devices provide accuracy to /2 LSB without the need for thin-film resistors or laser trimming, while dissipating less than 5 mw typically. Featuring operation from a 5-V to 5-V single supply, these devices interface easily to most microprocessor buses or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many microprocessor-controlled gain-setting and signal-control applications. The TLC7524C is characterized for operation from 0 C to 70 C. The TLC7524I is characterized for operation from 25 C to 85 C. The TLC7524E is characterized for operation from 40 C to 85 C. TA SMALL OUTLINE PLASTIC DIP (D) AVAILABLE OPTIONS PACKAGE PLASTIC CHIP CAIE (FN) GND DB7 NC DB6 DB5 GND DB7 DB6 DB5 DB4 DB3 PLASTIC DIP (N) D, N, O PW PACKAGE (TOP VIEW) SMALL OUTLINE (PW) 0 C to 70 C TLC7524CD TLC7524CFN TLC7524CN TLC7524CPW 25 C to 85 C TLC7524ID TLC7524IFN TLC7524IN TLC7524IPW 40 C to 85 C TLC7524ED TLC7524EFN TLC7524EN FN PACKAGE (TOP VIEW) NC FB EF V DD W DB0 DB DB DB4 DB3 NC FB DB2 DB EF NC No internal connection V DD W NC DB0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 998, Texas Instruments Incorporated

2 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVETES SLAS06C SEPTEMBE 986 EVISED NOVEMBE 998 functional block diagram EF 5 2 S- 2 S-2 2 S-3 2 S FB W Data Latches 3 GND 4 DB7 (MSB) 5 DB6 6 DB5 DB0 (LSB) Data Inputs Terminal numbers shown are for the D or N package. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V DD V to 6.5 V Digital input voltage range, V I V to V DD V eference voltage, V ref ±25 V Peak digital input current, I I µa Operating free-air temperature range, T A : TLC7524C C to 70 C TLC7524I C to 85 C TLC7524E C to 85 C Storage temperature range, T stg C to 50 C Case temperature for 0 seconds, T C : FN package C Lead temperature,6 mm (/6 inch) from case for 0 seconds: D, N, or PW package C 2

3 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVETES SLAS06C SEPTEMBE 986 EVISED NOVEMBE 998 recommended operating conditions VDD = 5 V VDD = 5 V MIN NOM MAX MIN NOM MAX Supply voltage, VDD V eference voltage, Vref ±0 ±0 V High-level input voltage, VIH V Low-level input voltage, VIL V setup time, tsu() ns hold time, th() 0 0 ns Data bus input setup time, tsu(d) ns Data bus input hold time, th(d) 0 0 ns Pulse duration, W low, tw(w) ns TLC7524C Operating free-air temperature, TA TLC7524I C TLC7524E electrical characteristics over recommended operating free-air temperature range, V ref = ±0 V, and at GND (unless otherwise noted) PAAMETE TEST CONDITIONS VDD = 5 V VDD = 5 V MIN TYP MAX MIN TYP MAX IIH High-level input current VI = VDD 0 0 µa IIL Low-level input current VI = µa IIkg IDD ksvs Ci Co Output leakage current Supply current Supply voltage sensitivity, gain/ VDD Input capacitance,, W, Output capacitance at 0 V, Vref = ±0 V at VDD, Vref = ±0 V W, at 0 V, W, at 0 V, ±400 ±200 ±400 ±200 Quiescent at VIHmin or VILmax 2 ma Standby at 0 V or VDD µa eference input impedance (EF to GND) UNIT UNIT VDD = ±0% %FS/% VI = pf DB7 at 0 V, DB7 at VDD, W, at0v W, at0v na pf kω 3

4 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVETES SLAS06C SEPTEMBE 986 EVISED NOVEMBE 998 operating characteristics over recommended operating free-air temperature range, V ref = ±0 V, and at GND (unless otherwise noted) PAAMETE TEST CONDITIONS VDD = 5 V VDD = 5 V MIN TYP MAX MIN TYP MAX Linearity error ±0.5 ±0.5 LSB Gain error See Note ±2.5 ±2.5 LSB Settling time (to /2 LSB) See Note ns Propagation delay from digital input to 90% of final analog output current See Note ns Feedthrough at or Vref = ±0 V (00-kHz sinewave) W and at 0 V, at 0 V %FS Temperature coefficient of gain TA = 25 C to MAX ±0.004 ±0.00 %FS/ C NOTES:. Gain error is measured using the internal feedback resistor. Nominal full-scale range (FS) = Vref LSB. 2. load = 00 Ω, Cext = 3 pf, W at 0 V, at 0 V, DB0 DB7 at 0 V to VDD or VDD to 0 V. operating sequence UNIT tsu() th() W tw(w) ÎÎÎ tsu(d) th(d) 4

5 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVETES PINCIPLES OF OPEATION SLAS06C SEPTEMBE 986 EVISED NOVEMBE 998 voltage-mode operation It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the reference voltage terminal. Figure is an example of a current-multiplying DAC, which is operated in voltage mode. EF (Analog Output Voltage) (Fixed Input Voltage) Figure. Voltage Mode Operation The relationship between the fixed-input voltage and the analog-output voltage is given by the following equation: V O = V I (D/256) where V O = analog output voltage V I = fixed input voltage D = digital input code converted to decimal In voltage-mode operation, these devices meet the following specification: PAAMETE TEST CONDITIONS MIN MAX UNIT Linearity error at EF VDD = 5 V, = 2.5 V, at GND, TA = 25 C LSB 5

6 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVETES SLAS06C SEPTEMBE 986 EVISED NOVEMBE 998 PINCIPLES OF OPEATION The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted -2 ladder, analog switches, and data input latches. Binary-weighted currents are switched between the and bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are decoded. These decoded bits, through a modification in the -2 ladder, control three equally-weighted current sources. Most applications only require the addition of an external operational amplifier and a voltage reference. The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference current, I ref, is switched to. The current source I/256 represents the constant current flowing through the termination resistor of the -2 ladder, while the current source I Ikg represents leakage currents to the substrate. The capacitances appearing at and are dependent upon the digital input code. With all digital inputs high, the off-state switch capacitance (30 pf maximum) appears at and the on-state switch capacitance (20 pf maximum) appears at. With all digital inputs low, the situation is reversed as shown in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, I ref would be switched to. The DAC on these devices interfaces to a microprocessor through the data bus and the and W control signals. When and W are both low, analog output on these devices responds to the data activity on the data bus inputs. In this mode, the input latches are transparent and input data directly affects the analog output. When either the signal or W signal goes high, the data on the inputs are latched until the and W signals go low again. When is high, the data inputs are disabled regardless of the state of the W signal. These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for 2-quadrant or 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table and Table 2 summarize input coding for unipolar and bipolar operation respectively. FB IIkg 30 pf EF Iref I/256 IIkg 20 pf Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low 6

7 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVETES PINCIPLES OF OPEATION SLAS06C SEPTEMBE 986 EVISED NOVEMBE 998 Vref VDD A = 2 kω (see Note A) B FB C (see Note B) W GND + Output NOTES: A. A and B used only if gain adjustment is required. B. C phase compensation (0-5 pf) is required when using high-speed amplifiers to prevent ringing or oscillation. Figure 3. Unipolar Operation (2-Quadrant Multiplication) Vref VDD 20 kω A = 2 kω (see Note A) B 20 kω FB C (see Note B) 0 kω + Output W GND + 5 kω NOTES: A. A and B used only if gain adjustment is required. B. C phase compensation (0-5 pf) is required when using high-speed amplifiers to prevent ringing or oscillation. Figure 4. Bipolar Operation (4-Quadrant Operation) Table. Unipolar Binary Code Table 2. Bipolar (Offset Binary) Code DIGITAL INPUT DIGITAL INPUT (see Note 3) ANALOG OUTPUT (see Note 4) ANALOG OUTPUT MSB LSB MSB LSB Vref (255/256) Vref (27/28) Vref (29/256) Vref (/28) Vref (28/256) = Vref/ Vref (27/256) 0 Vref (/28) Vref (/256) Vref (27/28) Vref NOTE 3: LSB = /256 (Vref) NOTE 4: LSB = /28 (Vref) 7

8 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVETES SLAS06C SEPTEMBE 986 EVISED NOVEMBE 998 microprocessor interfaces PINCIPLES OF OPEATION Z 80A D0 D7 Data Bus W W TLC7524 IOQ Decode Logic A0 A5 Address Bus Figure 5. TLC7524 Z-80A Interface D0 D Data Bus φ2 W TLC7524 VMA Decode Logic A0 A5 Address Bus Figure 6. TLC Interface 8

9 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVETES microprocessor interfaces (continued) PINCIPLES OF OPEATION SLAS06C SEPTEMBE 986 EVISED NOVEMBE 998 A8 A5 805 Address Bus 8-Bit Latch Decode Logic ALE W W TLC7524 AD0 AD7 Adress/Data Bus Figure 7. TLC Interface 9

10 IMPOTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CETAIN APPLICATIONS USING SEMICONDUCTO PODUCTS MAY INVOLVE POTENTIAL ISKS OF DEATH, PESONAL INJUY, O SEVEE POPETY O ENVIONMENTAL DAMAGE ( CITICAL APPLICATIONS ). TI SEMICONDUCTO PODUCTS AE NOT DESIGNED, AUTHOIZED, O WAANTED TO BE SUITABLE FO USE IN LIFE-SUPPOT DEVICES O SYSTEMS O OTHE CITICAL APPLICATIONS. INCLUSION OF TI PODUCTS IN SUCH APPLICATIONS IS UNDESTOOD TO BE FULLY AT THE CUSTOME S ISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 998, Texas Instruments Incorporated

11 MECHANICAL DATA MPDI002A JANUAY 995 EVISED OCTOBE 995 N (-PDIP-T**) 6 PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE DIM PINS ** A A MAX (9,69) (9,69) (23,37) (24,77) 6 9 A MIN (8,92) (8,92) (2,59) (23,88) (6,60) (6,0) (,78) MAX (0,89) MAX (0,5) MIN 0.30 (7,87) (7,37) (5,08) MAX 0.25 (3,8) MIN Seating Plane 0.00 (2,54) (0,53) 0.05 (0,38) 0.00 (0,25) M 0.00 (0,25) NOM 4/8 PIN ONLY /C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00 (20-pin package is shorter than MS-00).

TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS Easily Interfaced to Microprocessors On-Chip Data Latches Monotonic Over the Entire A/D Conversion ange Segmented High-Order Bits Ensure Low-Glitch Output Interchangeable With Analog Devices AD7524, PMI