RF Built-In Self-Test for Integrated Transmitters Using Sigma-Delta Techniques

Transcription

1 RF Built-In Sel-Test or Integrated Transmitters Using Sigma-Delta Techniques Christian Münker Inineon Technologies AG P.O. Box München, Germany muenker@ieee.org Robert Weigel Chair o Electronics University o Erlangen-Nuremberg, Germany weigel@lte.e-technik.uni-erlangen.de Abstract A new approach to adding built-in sel test BIST) capabilities to integrated sigma-delta modulation RF transmitters is presented. An area eicient, all-ital building block generates multitone FM stimulus signals without compromising the perormance o the RF transmitter itsel. The RF signal is demodulated and itied in a on-chip ital FM discriminator. Both blocks are ully testable using standard scan chain methods and consume a chip area o only.3 mm 2 in a 3 nm CMOS technology. The spectral quality and reproducibility o the test signals are suitable or intermodulation distortion tests or PLL requency response measurements. I. INTRODUCTION In the 98 s ital ICs had reached a complexity level that caused poor test coverage in spite o exploding production test times. As a consequence, design-or-test DT) methodologies like scan chains, boundary scan and built-in sel test BIST) became an integral part o ital IC design low. During the 99 s similar concepts were implemented on mixed-signal ICs, mainly to speed up the time consuming production tests o high-resolution ADCs and DACs [] [3]. Until a ew years ago, production test or RF ICs required a good understanding o RF measurement techniques but little DT support. RF ICs were low-complexity devices manuactured in special high-perormance technologies, surrounded by a plethora o passive and active components on the PCB. Now, even mainstream CMOS technologies have transit requencies exceeding GH, enabling e.g. the integration o RF transceiver and base-band processor on one chip. Fired up by a general trend towards wireless devices, RF ICs have become highly integrated, high volume commodity products or consumer markets with ierce competition and shrinking proit margins. As a consequence, test costs account or a growing percentage o the total production costs. Once more, testability and production test have become a bottle-neck or IC manuacturers, turning DT and BIST into an economic necessity or RF ICs as well. Modern CMOS processes acilitate enormous integration densities but due to their large statistical parameter spread and low supply voltages they are not optimied or analog or RF perormance. This makes not only the design o analog and RF circuitry a challenging task, there is also an increased risk o parametric ailures in the analog BIST circuitry itsel. Interering with critical RF paths on chip is also undesirable due to possible perormance degradation. On the other hand, the high integration density o deep submicron CMOS technologies allows the realiation o complex ital signal processing blocks with little area penalty. This avors the ital implementation o on-chip test circuitry: it is compact and robust and it can be tested using well established ital test methodologies. Reerence Frequency Mod. Data Fig.. PFD TX Filter Loop Filter Carrier Freq. Word VCO N / N+ ital Digital Σ modulation transmitter d n) q RF out This paper presents a ully ital BIST concept or wireless RF transmitters that allows testing key parameters without disturbing perormance critical analog paths. Catastrophic and also some parametric ailures can be identiied quickly. The ocus o this paper is on transmitter architectures utiliing a ital sigma-delta modulator ig. ). This architecture is commonly used or highly integrated RF CMOS transceivers because it is well adapted to CMOS technologies [4]. Section II gives an overview over the proposed test concept, section III describes the generation o ital multitone stimuli and section IV the upconversion o these stimuli to the RF domain. Section V shows a solution or demodulating and

2 itiing the RF signal in a compact ital building block. Section VI demonstrates how the concepts were integrated on a GSM transceiver test chip. II. TEST CONCEPT Recently, several loop back test concepts have been proposed or integrated RF transceivers where the on-chip receiver RX) demodulates the RF signal generated by the transmitter TX) [5], [6]. While loop back concepts look very appealing due to low area overhead and high test coverage, there are some pitalls or the practical implementation: Most chips built or time-division multiplex access systems like GSM or Bluetooth are not speciied and oten not capable) o running the RX and TX path at the same time. Oten, both paths share the local oscillator LO) to save chip area. Even when RX and TX do have independent LO generation, there is a high risk o injection lock-in between two oscillators running at nearly the same requency. Besides, most standards use requency division duplexing which means either RX or TX path would have to operate outside its speciied requency range during a loop back test. Data Reerence Frequency Pattern Generator TX Filter Dig. Multitone Generator Σ modulated bit stream Fig. 2. PFD Loop Filter FM Carrier Freq. Word Discriminator VCO N / N+ ital d n) q RF out Fractional-N modulator with added BIST blocks On-chip analysis o the transmit signal requires extracting and itiing the RF phase / requency inormation rom the carrier. Standard receiver architectures apply analog downconversion and high-resolution ADCs. They are optimied or receiving low-level RF signals in the presence o strong intererers and require large area, precision RF analog circuitry which makes them unsuitable or implementation as additional BIST circuitry. ital domain on- or o-chip. A suitable stimulus signal or the transmitter is generated by a ital multi-tone sine generator and upconverted to RF by the sigma-delta modulation transmitter Fig. 2) that acts as a sort o DAC converting ital data into RF phase/requency [7]. Multitone FM signals can e.g. be used to measure intermodulation distortion or the requency response o the PLL: the amplitude o a sideband within the passband is compared with another one outside the passband to check whether the closed loop bandwidth o the PLL is within the speciied limits Fig. 8). This ully ital stimulus generation and RF analysis does not interere with the critical RF paths. III. DIGITAL MULTI-TONE GENERATION Multitone tests have been used or a long time to characterie intermodulation distortions and requency response o ampliiers, ADCs or RF modulators / demodulators. [3] presents a mixed A-D built-in sel test MADBIST) scheme consisting o ital biquad oscillators and a Σ DAC or generation o multi-tone test signals to test both baseband ADCs and DACs. [8] extends this approach into the RF domain by using higher order images o a ital test signal to veriy an RF receiver. Disadvantages o this method are that the amplitude o the higher order images is not very predictable and that two multiplexers need to be inserted into the critical RF path. x n) b a Register A x an+) Register B Fig. 3. x a n) x bn+) Digital biquad oscillator b x an) The main building block or generating multi-tone signals in [3] is a ital biquad oscillator with quadrature outputs x a n), x b n) ig. 3), realied with lossless ital integrators LDI). As the transmitter provides a narrowband signal with large, constant amplitude, a much simpler demodulation technique can be applied: a irst order ital FM discriminator consists o simple, compact ital blocks and delivers a sigma-delta modulated bit stream that can be urther analyed in the xn) Fig Second order sigma-delta modulator xdn)

3 Relations or output signal requency ω sig, amplitude x a,x b and initial phase φ a,φ b o the biquad depending on sampling requency s, coeicients a, b and the initial conditions x a ),x b ) are derived in [9]: ω sig = s cos ab ) 2 or < ab 2 ) φ a = tan sinω sig T s )x a ) cosω sig T s )x a ) ab)+ax b ) 2) ˆx a = ab)x a)+ax b ) sinω sig T s + φ a ) Results or φ b and ˆx b are attained by exchanging x a with x b and a with b. For small coeicients ab, the ollowing approximations hold true: cos ab ab 2 and cos ab ) ab 2 Using these approximations and setting x b ) = gives the simpliied relations 3) ω sig ab s 4) φ a tan 2x a) π/2, φ b = 5) ab ˆx a x a) b x a ), ˆx b x a ) 6) sinφ a a showing that amplitude, requency and phase or the test tone can be set independently. The initial conditions can be optimied x b ) ) or equal amplitudes x a and x b i precise quadrature signals are needed. x n) b a = 2 α Register A x a n) x n+) b Register B x n+) a ital MUX xd n) a +b b [3]: A sigma-delta modulator ) ig. 4) converts an N-bit wide stream xn) into an oversampled single-bit stream xdn). Multiplying the single-bit stream with a constant b now only requires an N x multiplier which is implemented as a multiplexer ig. 5). In order to maintain the stability o the oscillator, an like in ig. 4 with a latency o one sample clock has to be used. The sine signal is reconstructed rom the oversampled data stream by simple low-pass iltering. Fig. 6. xn) xdn) Second order sigma-delta modulator or two time-multiplexed signals Multitone signals can be generated by adding the signals o two or more sine generators. A more economic approach is achieved by sharing the oscillator hardware using time division multiplexing [3]. For each tone, registers have to be provided in the ig. 6) and the oscillator ig. 7) so that the tone signals can be processed independently. The adders and the bit shiter are shared between the signals saving approx. 5% chip area compared to generating the tones individually. Due to the time division multiplexing, the eective sampling requency or L tones is reduced by a actor o L: s,e = s /L 7) This limits the useul number o tones, 8) gives a rule-othumb or the usable bandwidth o the oscillator [3]. BW s,e /5 8) The achievable spurious ree dynamic range SFDR) o the multi-tone signal is diicult to calculate because the quantiation error is not uncorrelated rom the signal. Thereore, the signal spectrum will contain discrete sidebands reducing the SFDR. An SFDR o 6 db was achieved in simulations with a word length o 5 bits. + xn+) + xdn) a = 2 α Register A ital /2 s xd n) a Fig. 5. Digital biquad oscillator using attenuator Directly implementing the circuit o ig. 3 in hardware would require two large area N x N bit multipliers. Another, more area eicient approach, is achieved by replacing one multiplier with a bit shiter, restricting the coeicient a to values o the orm 2 α. The second multiplier is implemented with a sigma-delta attenuator to achieve a ine granularity or the output requency with only moderate area requirements xn) Fig. 7. x n) b Register B MUX +b b +b 2 b 2 + xdn) Digital two-tone biquad oscillator using attenuator

4 IV. RF SIGNAL GENERATION Multi-tone FM / PM RF stimuli are easily generated by combining the multi-tone generator rom the last section with a ital sigma-delta modulation transmitter. Due to the inherent low-pass characteristic o the PLL, no additional ilter is needed to reconstruct the sine tones rom the oversampled data stream o the test-generator. φ re t) Phase Detector K P Loop Filter Zs) N VCO K VCO s Divider N Nn) φ out t) VCO Power Spectral Density Dn) RBW = 62.9 H a = 2 4 b =.2634 => = 55.9 kh Fig. 9. Principle o ractional-n modulator 2 b 2 =.22 => 2 = 73.7 kh S φ db / H) = 2 wmod /2 w re = 2 wmodw re, 3) where wmod < w is the word length o the modulation word. This corresponds to a peak modulation index ˆµ o ˆµ = / mod = 2 wmodw re mod. 4) Fig. 8. Oset Frequency rom Carrier H) Simulated two-tone spectrum at the PLL output The output requency out o a ractional-n PLL with a reerence requency re and a division ratio N, consisting o integer part N I and ractional part N F = FRAC/2 w, is given by out = re N I + FRAC ) 2 w = re N I.N F = re N 9) where w is the word length o the ractional accumulator and FRAC is the ractional word. With such an architecture phase / requency modulation o the PLL can be achieved by adding ital modulation data Dn) to the ractional word: FRAC+ Dn) Nn) = N I + 2 w ) The ital modulation o the division ratio is iltered by the closed loop transer unction Gs) o the PLL ig. 9) []: Φ out s) Φ re s) = Ns) N + K P K VCO s Zs) = Ns)Gs) ) Ns) is the representation o Nn) in the complex requency domain. Within the loop bandwidth, Gs) is approximately unity and the ital data directly aects the PLL requency: out n) re N I + FRAC+ Dn) 2 w ) 2) When Dn) is a ital sinewave with requency mod and amplitude ˆm = max[dn)] = 2 wmod, a peak PLL requency deviation is created o V. DIGITAL FM DISCRIMINATOR An ital FM discriminator and itier Fig. ) has irst been proposed or demodulating an FM IF signal in 994 []. At that time, multi-gh dividers could only be implemented in ECL technology, requiring considerable chip area and power. Nowadays they can be realied as low-power, compact CMOS logic building blocks, enabling their use in RF BIST applications. To avoid aliasing, the requency deviation o the input signal has to be band-limited < re /2 5) which is automatically ulilled as the PLL bandwidth has to be much lower than re due to stability reasons. Just as the input signal o a sigma-delta ADC must not exceed the quantier input step ±q to avoid an overload condition, the input requency RF o the sigma-delta requency discriminator has to be within the limits Mod. Data Channel Word Fig.. re re mod rac int CUT PLL N / N+ N mod re div DFF D RF Demod Out First order FM discriminator with circuit-under-test CUT)

5 N re < RF < N + ) re. 6) I these conditions are ulilled, the demodulated output signal in ig. is an oversampled, sigma-delta modulated approximation o the requency modulating signal. Fig. shows the simulation plot o a demodulated two-tone signal, achieving an SNR o nearly 9 dbc. VI. IMPLEMENTATION Functional and RF perormance simulations were perormed with a standard VHDL simulator, using the methodology described in [2], [3]: The complete circuit in ig. 2 including the analog blocks like VCO and loop ilter was modeled in VHDL, the simulated period data o the VCO and the demodulated bit stream o the FM discriminator were dumped to a text ile and post-processed using Matlab. Fig. 8 shows the simulated two-tone test signal at the output o a PLL with a loop bandwidth o kh, the x-axis being the oset requency rom the carrier. The low-pass characteristic o the PLL is marked by the bold line. One tone is outside the loop bandwidth, it is attenuated by approx. 2 db compared to the in-band tone. This ratio can be easily veriied in a production test setup using a spectral analyer. The spurious ree dynamic range is nearly 6dB which is more than suicient or requency response measurements. Two dierent programmable test tone generators have been synthesied and put on a GSM transceiver test chip in a 3 nm CMOS technology. Table I shows the achieved requency range and the chip area excluding interconnect area). Tones Word Length Min. Freq. Max. Freq. Area 5 3 kh 365 kh. mm kh 82 kh.5 mm 2 S φ db / H) Spurs) Fig Samples: FFT Bins: 3767 Max: 9. db RBW = H TABLE I IMPLEMENTED TEST-TONE GENERATORS Demodulated VCO Signal st order FM Discriminator) Latency = cycles Frequency H) = 4.9 kh 2 = 55.9 kh Downconverted two-tone spectrum using st order FM discriminator The FM discriminator has been layouted by hand and requires an area less than.5 mm 2 on the test chip. No measurement results are available yet. VII. CONCLUSIONS An area eicient method or the built-in sel test o integrated RF transmitters has been presented that relies entirely on ital components. Multi-tone stimuli are generated with a compact generator utiliing lossless ital integrators and upconverted using the sigma-delta modulation transmit PLL. The FM /PM modulated RF signal is downconverted and itied using a ital FM discriminator. This test architecture does not interere with critical RF signal paths as the signal generation and demodulation is perormed entirely in the ital domain. VIII. OUTLOOK A ital on-chip spectral analysis o the demodulated bit stream will be the next step to allow a complete BIST, reducing even urther the requirements or costly RF production test equipment. Built-In Sel Calibration BISC) strategies can also be implemented with this setup to increase the yield and to make the circuit more robust against environmental variations. I necessary, the resolution o the integrated FM discriminator can be improved by increasing the order or the sampling requency. ACKNOWLEDGMENT Part o this work was unded by the BMBF in the rame o the EKompaSS project Nr. M37 DETAILS. REFERENCES [] S. L. Hurst, VLSI Testing: Digital and Mixed Analogue / Digital Techniques. London, United Kingdom: The Institution o Electrical Engineers, 998. [2] IEEE Standard Board, 49.4 mixed-signal test bus, [3] A. Lu and G. Roberts, An analog multi-tone signal generator or built-in-sel-test applications, in Test Conerence, 994. Proceedings., International, Oct. 994, pp [4] C. Muenker, B.-U. Klepser, B. Neurauter, and C. Mayer, Digital RF CMOS transceivers or GPRS and EDGE, in Radio Frequency integrated Circuits RFIC) Symposium, 25. Digest o Papers. 25 IEEE, 25, pp [5] S. Oev and C. Olgaard, Waer-level RF test and DT or VCO modulating transceiver architectures, in VLSI Test Symposium, 24. Proceedings. 22nd IEEE, 24, pp [6] A. Haider, S. Bhattacharya, G. Srinivasan, and A. Chatterjee, A systemlevel alternate test approach or speciication test o RF transceivers in loopback mode, in VLSI Design, 25. 8th International Conerence on, 25, pp [7] T. Riley, M. Copeland, and T. Kwasniewski, Delta-sigma modulation in ractional-n requency synthesis, Solid-State Circuits, IEEE Journal o, vol. 28, no. 5, pp , 993. [8] B. Veillette and G. Roberts, A built-in sel-test strategy or wireless communication systems, in Test Conerence, 995. Proceedings., International, Oct. 995, pp [9] A. Lu, G. Roberts, and D. Johns, A high-quality analog oscillator using oversampling D/A conversion techniques, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 4, no. 7, pp , 994.

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