Sample Rate Conversion for Software Radio

Transcription

1 SOFTWARE AND DSP IN RADIO Sample Rate Conversion or Sotware Radio Tim Hentschel and Gerhard Fettweis, Dresden University o Technology ABSTRACT Sotware radio terminals must be able to process many various communications standards. These standards are generally based on dierent master clock rates and thus employ dierent bit/chip rates. The most obvious solution to cope with the diversity o master clock rates in one terminal is to provide a dedicated master clock or each standard o operation. Not only too costly, this kind o solution limits the applicability o a realized terminal. Hence, it is much more elegant to run the terminal on a ixed clock rate, and perorm digital sample rate conversion controlled by sotware. INTRODUCTION Sotware radio is a notion as ambiguous as any object o research can be. Depending on the point o view, dierent acets can be emphasized (e.g., the network or terminal aspect), where either the hardware or sotware aspects may be o more interest. From a signal processing point o view, sotware radio is a means to realize as many as possible signal processing tasks o a communications transceiver by means o sotware. Hence, there must be a hardware platorm on which this sotware can run. As technology advances, this hardware platorm will more and more appear as a kind o compute engine driven by a digital signal processor (DSP) and equipped with certain accelerators. Together with the necessary interaces the analog-to digital converter (ADC) and digital-to-analog converter (DAC) this compute engine is clocked by a master crystal. The interaces especially require highquality clocks with very low jitter (Fig. 1). Since dierent communications standards are based on dierent master clock rates, it is mainly necessary to provide these dierent clock rates. However, due to the strong requirements or clock quality, it is reasonable to assume that only one ixed master clock will be provided in practical sotware radio applications. A solution to this is to provide the dierent clock rates virtually by means o digital sample rate conversion (SRC). Hence, with the advent o sotware radio a new unctionality has to be introduced to the signal processing o digital communications transceivers: SRC. Apart rom being just a lukewarm rehash o the wellknown interpolation problem, SRC is the task o converting the sample rate o a digital signal to another sample rate while a certain amount o inormation, usually in a limited requency band, must be preserved. As will be seen in the course o the article, the main concern is not interpolation but anti-aliasing [1]. SRC has to take place at each o the analogto-digital or digital-to-analog interaces. Depending on the characteristics o a signal and the amount o inormation to be preserved, dierent solutions or SRC exist. Among those, interpolation as suggested in [2] is a solution or a certain application scenario only. The reason interpolation is oten avored is a historical one. Interpolation is a well-known solution to the mathematical problem o calculating in-between values o tabulated unctions. In the context o signal processing the table elements are replaced by signal samples. However, when comparing the requirements or calculating in-between values o tabulated unctions and calculating those o discrete-time signals, it becomes apparent that the classical approach o employing interpolation or SRC is not suicient. The idea o interpolation is to have a smooth curve whose samples are the tabulated values. Thus, interpolation is a time-domain approximation. In signal processing the constraints on calculating in-between values can be dierent. A smooth course o the signal is generally not the issue; the main concern is the inormation carried by the signal or parts o it. To understand this it is helpul to shit the point o view rom the time to the requency domain, where usually dierent requency bands carry dierent inormation. By doing this the requirement or SRC can be ormulated as calculating in-between values o a discrete-time signal such that a certain requency band o the signal is not distorted. Once the signal characteristics (and thus the distribution o the interesting inormation in the requency domain) are known, the problem o SRC can be tackled with the idea o resampling ater reconstruction, where an analog signal is (virtually) reconstructed rom the digital signal by means o DAC and iltering. Eventually the reconstructed signal is resampled [3]. From this idea the basic equations can be derived, resulting in an all-digital description o the necessary iltering task. Although this all-digital description enables one to orget the /00/$ IEEE

2 RF/analog ront-end detour via reconstructing an analog signal and resampling it, it is o paramount importance to always keep in mind that SRC is a process o resampling. The undamental eects o sampling imaging and aliasing must be expected to appear with SRC. Hence, SRC turns out to be mainly a problem o designing appropriate (anti-imaging and anti-aliasing) ilters and hardware structures implementing these ilters. In particular, the underlying hardware structures should not be underestimated. Since power consumption is a major issue in mobile communications systems at least on the mobile terminal side hardware structures are sought which implement the necessary iltering tasks eiciently. Moreover, these hardware structures should be adaptive in such a way that SRC can be perormed independent o the current standard o operation o the sotware radio terminal. Dierent rate change actors, pass-bandwidth, and stop-band attenuation are the main characteristics which must be variable, and call or reconigurability o the hardware platorm or SRC in sotware radio transceivers. In order to show how demanding this reconigurable hardware platorm is, the article starts with a brie discussion o signal processing issues o sotware radio. A SIGNAL PROCESSING PERSPECTIVE ON SOFTWARE RADIO Approaching the sotware radio concept rom a signal processing perspective means that one tries to implement the dierent unctionalities o a transceiver by means o sotware. Since the signals at the antenna are analog signals, there will always be the need or a radio requency (RF) part and an analog ront-end. Depending on how many unctionalities o the transceiver can be realized in the digital domain, the complexity o the RF part and analog ront-end varies. It should be noted that realizing a certain unctionality in the digital domain does not necessarily mean that it is ully relected by sotware running on a DSP. There are certain DSP algorithms which are too demanding or a (conventional) DSP to achieve a cost-eective A D Analog-to-digital converter Accelerators DSP (sotware) Compute engine One common master crystal Figure 1. The hardware platorm o a sotware radio receiver. ~ D solution. A typical example is digital down-conversion (DDC) o a received signal, which is perormed directly ater ADC, and thus at a relatively high sample rate. DDC is multiplication o a bandpass signal with a rotating complex phasor. It can be realized by two separate multiplications with sine waves having a mutual phase dierence o p /2. One just has to imagine a sample rate o 65 Msamples/s to quickly realize that a conventional DSP with one multiply-accumulate (MAC) unit being clocked at 65 MHz is not capable o handling this task. Thereore, such number-crunching unctions are realized by dedicated pieces o hardware named accelerators. These accelerators are not programmable. Still, in the context o sotware radio they should be adaptable to the dierent modes o operation o the transceiver. This can be reached by making them parameterizable. Due to the very limited unctionality o a certain accelerator, it is suicient to just change its parameters in order to adapt it to a certain task; or example, it is suicient to change the carrier requency and phase oset o a DDC. The dierent accelerators and DSP orm the compute engine o a sotware radio transceiver. In Fig. 1 is sketched how a compute engine, the ADC, the DAC, and the RF part orm the hardware platorm o a sotware radio receiver. By reversing the order o the signal low, the principal structure o a hardware platorm o a sotware radio transmitter can be obtained. There are a manageable number o dierent signal processing tasks which might require acceleration: Viterbi equalization, despreading/ spreading, digital iltering (at high sample rates), digital down/upconversion, and so on. At any time some o them are part o every communications transceiver. Hence, it is sensible to merge them with the DSP, yielding a new generation o application-tailored DSPs; or urther details on this concept see [4, 5]. As will be seen later in this article, SRC should be implemented on a cascaded multirate architecture where some parts have to run at very high clock rates. Thereore, the necessary iltering tasks overstretch the capabilities o conventional DSPs, as DDC does. Hence, SRC is a candidate to get its own accelerator. A Digital-to-analog converter Digital output Analog output Approaching the sotware radio concept rom a signal processing perspective means that one tries to implement the dierent unctionalities o a transceiver by means o sotware. Since the signals at the antenna are analog signals, there will always be the need or an RF part and an analog ront-end. 143

3 x(t) x(kt 1 ) x a (t) Figure 2. Resampling ater reconstruction. y(t) t = kt 1 t = mt 2 Ideal Lowpass digital-to-analog ilter converter X() D A SIGNAL CHARACTERISTICS Beore dealing with SRC something must be said about the characteristics o signals whose sample rate should be converted. Basically, signals with high dynamic range and those with 1/T 1 Images h(t) y(mt 2 ) (a) Beore sampling X a () (b) Ater sampling H() Y() 1/T 1 2/T 1 c stop 1/T 1 2/T 1 Distortions in transition band 1/T 1 (c) Transer unction o reconstruction ilter (d) Ater reconstruction Incompletely attenuated image Y a () Aliasing-ree region (e) Ater resampling 1/T 2 2/T 2 Figure 3. Spectral interpretation o SRC (given or the case T 1 < T 2 ). ( Y a () is the magnitude spectrum o the sampled version o y(t), since X a () is the magnitude spectrum o the sampled version o x(t).) lower dynamic range must be distinguished. In the context o mobile communications the irst are mainly a result o sampling a signal covering a bandwidth which comprises several channels o a certain mobile communications standard. Due to the adjacent channel intererence characteristics allowing an adjacent channel to have a considerably higher power level than the channel o interest itsel, such multichannel signals have high dynamic range. Conversely, single-channel signals have lower dynamic range. With respect to Fig. 1, the ADC and a possible ollowing SRC have to cope with a multichannel signal, while the DAC and a possible preceding SRC might just have to process a single-channel signal (e.g., voice). In a transmitter the DAC has to cope with a multichannel (transmission) signal, while the ADC just needs to digitize a single-channel signal (e.g., an audio signal). With respect to the deinition o SRC in the introduction to this article, it should be noted that in many cases it is suicient to preserve the inormation o one single channel o interest o a multichannel signal when perorming SRC on a multichannel signal. RESAMPLING AFTER RECONSTRUCTION A straightorward solution to SRC is to reconstruct the original analog signal rom the discrete-time signal and resample the reconstructed signal with the new clock period T 2. This approach is sketched in Fig. 2. Assuming ideal DAC (ideal Dirac impulses) and a reconstruction ilter with impulse response h(t), the discrete-time signal ater SRC can be related to the discrete-time signal beore SRC as ollows: y( mt2) = x( kt1) h( mt2 kt1) k = with and mt mt µ m = 2 T 2 1 T1 mt n = k 2. T1 (1) mt2 = x T1 n h( T1 ( n m )) n T + µ = 1 The quantity m m is limited to the interval m m Œ [0,1). It relects the position o the current sample inside to be calculated inside the sample period T 1, and is commonly called the intersample position. Equation 1 is a direct digital representation o SRC. The impulse response h(t) is sampled with the period T 1 o the input signal, still, with dierent time osets m m T 1 which depend on the position o the output sample with respect to the input samples. This means that or each calculation o an output sample, a dierent set o samples o the impulse response h(t) is used. Hence, the digital representation o SRC is a time-varying iltering operation. The 144

4 ilter h(t) inluences the quality o the SRC process, which itsel is determined by the eects aliasing and imaging. This can be understood rom interpreting SRC spectrally, as in Fig. 3. I the sampling period T 1 is short enough with respect to the bandwidth o the bandlimited signal x(t), the images caused by spectral repetition due to sampling do not overlap and thus do not cause aliasing, as shown in Fig. 3b. Perect reconstruction would mean that h(t) is an ideal low-pass ilter canceling all images. Still, this is neither possible nor necessary in most cases. Depending on the band to be kept ree rom distortions by SRC, the ilter h(t) can employ more or less relaxed constraints, possibly causing passband distortions o the original signal and/or incomplete attenuation in the stop-band (e.g., incomplete attenuation o the images). These eects are sketched in Fig. 3c, d. Since any sampling process causes spectral repetition with respect to the sampling period, resampling also does. According to the characteristics o h(t) the images overlap. Consequently, aliasing distortions arise, as shown in Fig. 3e. Thus, the design o the ilter is the irst task to be solved when tackling the problem o SRC. The main purpose o this ilter is to control aliasing. As stated in [1], anti-aliasing is the most prominent constraint to be obeyed by any sample rate conversion system. The power o the aliasing distortions depends on the signal characteristics. It should be remembered that in the context o SRC the aliasing components are a result o the discrete-time nature o the original signal x(kt 1 ) and the respective spectral repetitions (Fig. 3). In a single-channel signal the aliasing components cannot be stronger than the channel o interest, while in multichannel signals the aliasing components can have a much higher power level than the channel o interest. This occurs i the channel o interest in a multichannel signal has low power while some adjacent channels potentially causing aliasing to the channel o interest have high power. From this short discussion it can be concluded that it is sensible to stick to the requency domain approach to SRC rather than the time domain approach. From Fig. 3 it is evident that the smaller the region which should be kept ree rom aliasing, the smaller the stop-bands o the ilter attenuating the aliasing components can be. This enables the application o comb ilters with reduced eort. RATIONAL FACTOR SRC Rational actor SRC is the case i the sample periods o the input and output signals are related by two positive integers L and M (i.e., T 1 /T 2 = L/M). Now, the second part o Eq. 1 can be rewritten as mm ymt ( 2) = x T 1 n h( T1( n m )). n L + µ = (2) The intersample position mm L µ m = ( )(mod ) L x(kt 1 ) w(nt 0 ) v(nt 0 ) y(mt 2 ) L h(nt 0 ) M T 1 T 0 = T1 L Figure 4. Rational actor SRC. can only take L distinct values. Thus, the number o dierent sets o samples o h(t) used or the calculation o y(mt 2 ) is limited to L. Since m m is periodic with period L, the ilter h( ) can be implemented as a periodically time-varying ilter with period LT 2. Introducing the period T 0 = T 1 /L = T 2 /M, and the two signals v(nt 0 ) and w(nt 0 ) enables us to rewrite Eq. 1 and derive the well-known block diagram o a system or rational actor SRC [3] sketched in Fig. 4. The signal w(nt 0 ) is the result o upsampling the signal x(kt 1 ) by L. It is generated by the L block, called an upsampler or a sample-rate expander. Upsampling by L is realized by inserting L 1 zeros between two consecutive samples o the original signal. In order to obtain the output signal y(mt 2 ) the signal v(nt 0 ) is downsampled by M. This is done by the MØ block, called a downsampler or a sample-rate compressor. Downsampling by M is realized by deleting all but every Mth sample rom the signal. Although very useul or investigations, the structure o Fig. 4 is not applicable in practice. This is due to the possibly very high intermediate sample rate 1/T 0 at which the ilter would have to be clocked. INTEGER FACTOR SRC By setting L or M to 1, integer actor SRC as a special case o rational actor SRC can be achieved. All considerations made with respect to rational actor SRC can be applied directly to integer actor SRC. In integer actor sample rate increase (L > 1, M = 1), the images caused by the SRC process can be regarded as not overlapping, and thus not causing aliasing. The ilter is a pure anti-imaging ilter. Oten, it is called an interpolation ilter, which together with the upsampler orms an interpolator (i.e., a system or integer actor sample rate increase). Setting L = 1 leads to a reduction o the sample rate by M. Depending on the bandwidth o the signal beore SRC the images resulting rom resampling might overlap, which means that aliasing occurs. Aliasing can be reduced by proper anti-aliasing iltering with h( ). The combination o the anti-aliasing ilter and downsampler is called a decimator. CONCEPTS FOR SRC Since the sample rate both beore and ater SRC can be expressed as an integer number o samples per time unit, the rate change (conversion) actor is a rational number. An exception to this is the case where two asynchronous digital systems are interaced [3]. Besides the conversion actor, another design parameter is important: the ratio between the sample rate o the signal, T 0 = T 2 = MT 0 T 1 L 145

5 Fractional SRC Decimation by integer actors Stage 1 Stage 2 Stage n x(kt 1 ) SRC SRC SRC y(mt 2 ) Figure 5. Eort vs. sample rate in a cascaded SRC system (with the suggestion o placing ractional SRC at a high sample rate). and the bandwidth o the channel o interest, that is, the oversampling ratio (OSR) o the channel o interest. The OSR ater the SRC process directly determines the relative bandwidth (compared to the sample rate) o potential aliasing components that have to be attenuated by the SRC ilter. The higher the OSR, the smaller the passband and the stop-bands o this ilter can be. Hence, a high OSR (ater SRC) relaxes the design constraints, leading to simpler ilter structures. A consequence o this is that SRC is advantageously implemented on a cascaded multirate system (i.e., a cascade o ilters with relaxed requirements at high sample rates and strong requirements at low sample rates) [3]. Since the number o coeicients o a ilter complying with a given tolerance scheme is heavily dependent on the type o ilter, it is not possible to give quantitative estimates that are generally valid. Thereore, it should be suicient to note that decreasing the sample rate while keeping the bandwidth o the channel o interest constant means a decreasing OSR. Again, this leads to an increase in the necessary number o coeicients o the respective ilter stage. Hence, in multirate systems a trade-o between sample rate and hardware eort (number o coeicients) can be made. The ratio o the output and input sample rates is 2 / 1 = L/M, where L and M are relatively prime (i.e., the greatest common divisor o L and M is 1). It can be distinguished between eective reduction (L < M) and eective increase (L > M) o the sample rate. Moreover, it can be distinguished between integer actor and ractional SRC. Although having several commonalities, integer actor and ractional SRC also have dierences. Thereore it is sensible to separate them. The rate change actor can be actorized to a ractional part (L/M) rac and an integer part L int (or M int ): L M T 1 << T 2 eective downsampling L Lint eective increase M rac = L. 1 eective reduction M rac Mint Requirements, eort, and word length (clock rate) Operations per time (eort x clock rate) It should be noted that the ractional actor (L/M) rac is limited to the interval (0.5,2). I the overall conversion is an eective reduction o the sample rate, this actor can be limited urther to the interval (0.5,1) or (1,2) in the case o an eective increase o the sample rate. Whether this urther limitation is sensible or not depends on the ilter algorithms and their implementation (e.g., it might be a problem to temporarily increase the sample rate in a system realizing an overall sample rate reduction). The order o arranging the ractional and integer parts is an open question. It should be noted that the OSR beore ractional SRC is o the same order as ater ractional SRC. Thereore, the requirements or integer actor SRC remain the same regardless o its position within the sequence o iltering. Thus, the above mentioned trade-o between sample rate and hardware eort can be made or the ractional part o the SRC system independently. The sample rate o the ilter directly determines the multiplication rate. Still, the multiplication rate and hardware eort are determined by the ilter type. For equiripple inite impulse response (FIR) low-pass ilters, the number o coeicients N depends on the pass-, transition-, and stop-band width, and thus on the OSR [3]. The relation between N and the OSR is given by the proportionality N~OSR/(OSR 1). Hence, as the OSR approaches 1, the number o coeicients explodes. Although this number cannot be ininite in practice, it can be concluded that placing the ractional part o SRC at a very low sample rate in a cascaded multirate system is not the optimal solution to minimizing the number o coeicients, at least i equiripple FIR low-pass ilters are employed. In Fig. 5 a cascaded multirate structure or SRC is sketched, indicating the increase o hardware eort as the sample rate, and thus the OSR, decreases. This leads to a (theoretically) constant eort in terms o operations per time unit regardless o the position in the cascaded structure. Dierent ilter types have dierent advantages and disadvantages. This leads to the act that placing ractional SRC at a high sample rate in a cascaded multirate system would lead to applying another type o ilter compared to the type which would be used in case o placing ractional SRC at a low sample rate in the cascade. For instance, i the OSR is high, comb ilters merely suppressing the aliasing components are a very eicient choice. Still, or low OSRs such ilters are not suicient. Generally, the advantages o placing ractional SRC at a high sample rate are: Lower complexity due to relaxed requirements. I noise-shaping ADCs with low output word length eed the ilter, coeicient multipliers can be realized by simple switches or lookup tables o relatively small size. The complete system or SRC has greater lexibility. The ractional part runs on the ixed input sample rate, while the integer part can be made parameterizable with respect to its output rate. I placed at the end o the cascade, the ractional part would have to run on dierent output sample rates, making it more diicult to ind eicient solutions. The disadvantages are: The high clock rate at which the ilters have to run The required high aliasing attenuation or multichannel signals 146

6 From these advantages and disadvantages the pros and cons o placing ractional SRC at a lower sample rate can be derived. Since the requirements on the ilters are stronger with lower OSRs, the eort or ractional SRC at a lower sample rate is higher. This is mainly relected by the number o coeicients o the ilter, and thus the number o multipliers. I the sample rate is so low that time-division hardware sharing is possible, several coeicient multipliers can be realized by a small number o MAC units o a DSP. In a ield programmable gate array (FPGA) or an application-speciic integrated circuit (ASIC) based implementation, each coeicient is usually realized by its own multiplier. Thereore, in this case it is ar more advantageous to place ractional SRC at a high sample rate. This enables the application o simple comb ilters whose implementation requires only a small number o multipliers. SYSTEMS FOR INTEGER FACTOR SRC Being a undamental signal processing task, integer actor SRC is not only a part o a cascade or rational actor SRC but is also a part o any system employing oversampling. In such systems it is necessary to convert between an oversampled rate and a processing rate, which could be the chip or symbol rate o a certain communications standard. The direct approach o realizing integer actor SRC is determined by the act that downsampling has to be preceded by iltering in order to avoid aliasing, while upsampling can be ollowed by iltering in order to remove spectral images. Thus, the ilter is always placed at the high sample rate. Principally, any kind o ilter can be used, insoar as it obeys a given tolerance scheme or magnitude and phase response. The signal at the input to an interpolation ilter comprises L 1 zeros between two consecutive samples o the original signal. At the output o the decimation ilter M 1 out o M samples are deleted. Exploiting this, the ilters can be combined with the upsampler or downsampler, respectively. This leads to solutions much more eicient than the direct ones. Their main parts are clocked at the lower o the two involved sample rates. These solutions are based on the polyphase representation o both the signal and the impulse response o the ilter, and can be derived, or example, rom the corresponding block processing structure [6]. Block processing is a very graphic way o analyzing systems or SRC. It is as simple as constructing a system with M inputs and L outputs which takes blocks o M samples o the input signal and generates blocks o L samples o the output signal. Such systems are generally time-invariant, enabling the use o the large apparatus o time-invariant system theory, which is the great advantage o applying block signal processing in this respect. The relation between a periodically time-varying system (e.g., Fig. 4) and the respective time-invariant block processing system is given by the socalled liting isomorphism or raising procedure [1, 7]. It is based on the state-space description o linear systems. For integer actor SRC the well-known structures o the polyphase-decimator and polyphase-interpolator result. The hardware platorm o these structures can be made independent rom the rate change actor by just oreseeing one polyphase branch and changing the set o coeicients periodically. For details on polyphase structures the reader is reerred to [3, 8]. A disadvantage o these solutions is that L sets o coeicients o the impulse response h(t) (sampled with 1/T 1 and L dierent osets m m T 1 ) must be stored. Especially or large values o L a considerable size o coeicient memory results. This can be avoided i the coeicients are not stored but calculated on demand. I the eort or calculating the coeicients is less than the eort or storing them, this approach is sensible. In order to keep the eort low or calculating the coeicients, the impulse response h(t) must be a unction (or must be approximated by a unction) o relatively low complexity. Polynomials are such unctions. Thus, h(t) can be described by piecewise polynomials. Combining polynomial iltering and block processing leads to structures which can be realized very eiciently. One o those is the Farrow structure, resulting rom implementing a polynomial impulse response on a polyphase interpolator [9, 2]. Although it is very eicient, there are still several multipliers required in the Farrow structure. The actual number depends on the length o the impulse response o the ilter and the degree o the polynomials o which the impulse response consists. Thereore, the Farrow structure and similar implementations o polynomial impulse responses should be realized on a DSP at a low sample rate where the ew MAC units o the DSP can realize all necessary multipliers in a time-shared manner. Another class o simpliied structures or integer-actor SRC results rom sensible actorizations o the transer unction o certain ilter types. These are cascaded comb ilters [10] and cascaded integrator comb (CIC) ilters [11]. Especially, the latter have enjoyed great success and wide application. They are multiplierless comb-ilters with low eort. Due to the small width o their stop-bands they should be applied at high OSRs o the channel o interest. Their simple structure supports an implementation at high sample rates. Finally, it should be mentioned that the application o block processing also leads to novel ilter structures employing time-varying eedback loops [12, 13]. These structures exhibit very low complexity with respect to the state-space (and thus, the number o registers). SYSTEMS FOR FRACTIONAL SRC Implementing Eq. 2 as shown in Fig. 4 can be regarded as the direct approach to realizing ractional SRC. A time-invariant realization o the ilter on the high intermediate sample rate 1/T 0 circumvents additional controlling eort, which is necessary in time-varying systems. Still, very quickly the intermediate sample rate can reach values that are not realizable. As mentioned above, the intermediate sample rate is directly Being a undamental signal processing task, integer actor SRC is not only a part o a cascade or rational actor SRC but is also a part o any system employing oversampling. 147

7 Time-varying polyphase structures or ractional SRC can be obtained rom combining a polyphase interpolator with a downsampler, or an upsampler with a polyphase decimator. determined by the ratio o the two rates at the input and output o the sample rate converter. Thus, realizations according to Fig. 4 are only easible in certain applications where the ractional rate-change actor (L/M) rac is given as a ratio o two small positive integer numbers L and M. I the impulse response o the reconstruction ilter can be realized by a comb ilter, its implementation as a CIC ilter can result in reduced eort, as in the case o integer actor SRC. However, parts o the ilter have to be clocked at the high intermediate sample rate, which again limits the application to small numbers L and M. Directly employing block processing is not a solution either, due to the act that a system with M inputs and L outputs is hardly realizable i L or M get large. Moreover, the dependence o the number o inputs and outputs on the rate change actor makes such systems unsuitable or arbitrary rate change actors, which is, however, necessary in sotware radio applications. The limitations o implementing time-invariant ilters (on a high intermediate sample rate, or as block processing ilters) or ractional SRC suggest the application o time-varying structures. A straightorward solution would be to realize Eq. 2 directly. This leads to time-varying polyphase structures. Time-varying polyphase structures or ractional SRC can be obtained rom combining a polyphase interpolator with a downsampler, or an upsampler with a polyphase decimator. Hence, it is simply a certain partitioning o Fig. 4 where either the upsampler and ilter are realized by a polyphase interpolator, or the ilter and downsampler are realized by a polyphase decimator. The great advantage o these structures is that they are exactly the same as the polyphase structures or integer actor SRC (interpolation and decimation). Only the additional downsampling or upsampling processes have to be taken into account. This is done by appropriately selecting the respective polyphase deined by the intersample position m m. It is also a simple matter to extend the application o polynomial ilters to ractional SRC. Hence, the Farrow structure as an eicient realization o polynomial polyphase ilters is also applicable [14], but with the restriction to low sample rates. Polyphase realizations can also be given or CIC ilters. They can be ound, or example, by exploiting the block processing idea. The result is time-varying CIC-ilters or ractional SRC with arbitrary actors [15, 16] which provide a means to realize ractional SRC at high sample rates. A CASE STUDY Although concrete solutions and structures or SRC are beyond the scope o this article, an illustrative example should be given. It is based on reerences given at the end o the article. They should help the reader ully comprehend the example. The object o the example is designing a system or ractional SRC which is part o a receiver or the Global System or Mobile Communications (GSM), IS-95, and Universal Mobile Telecommunications System (UMTS) air interaces. Digitization o the signal at intermediate requency (IF) with a sample rate o 80 Msamples/s and suicient dynamic range o the ADC is taken or granted. Furthermore, it is assumed that the analog iltering beore digitization is solely or anti-aliasing. Hence, 40 MHz o (real) bandwidth is available, comprising the channel o interest as well as adjacent channel intererers. Two solutions to SRC should be examined that are principally shown in Fig. 6: time-varying CIC ilters [15, 16] placed irst in a cascaded structure, and the Farrow structure [14] running at twice the chip or bit rate o the current mode o operation. Both approaches have been subject to investigation in the context o the ACTS project Sotware Radio Technology supported by the European Commission. Time-varying CIC ilters have been chosen or an implementation in a demonstrator o this project. Placing ractional SRC at the end o a cascaded structure or SRC means that all adjacent channel intererers have been attenuated beore. Potential aliasing components can only stem rom spectral replications o the channel o interest itsel, which can distort the signal. Thereore, an aliasing attenuation o 40 db is claimed to be suicient or ractional SRC. For an OSR o 10 this attenuation can be achieved by means o linear interpolation (i.e., a linear interpolator suppresses images o a 10x oversampled signal by 40 db at minimum). In order to achieve this OSR the signal must be upsampled by 10. The resulting nine spectral images must be attenuated. In order to keep up with the linear interpolator, an attenuation o 40 db is required or the anti-imaging ilter. This can be achieved with an equiripple low-pass ilter with approximately 40 taps. An implementation o the anti-imaging ilter in conjunction with the linear interpolator on the Farrow structure circumvents high intermediate sample rates (e.g. a 10x increased input sample rate) at the output o the equiripple low-pass ilter. It results in a time-varying system requiring 2 x 40 coeicients to be implemented. The doubling o the number o coeicients comes rom the linear interpolation combined with the iltering. The ilter implemented on the Farrow structure has a piecewise linear polynomial impulse response (straight lines connecting the 40 coeicients). Hence, to describe each o the linear polynomial pieces two values are needed. Since the incoming signal to the system is (virtually) 10x oversampled, only our samples o the impulse response are used at a time. This results in a requirement o eight multipliers or calculating the required samples rom the linear polynomial pieces. For each incoming signal sample dierent polynomial pieces are sampled. Thereore the 8 multipliers must be general purpose and cannot be ixed coeicient multipliers. Additionally, one general purpose multiplier is necessary or the calculation o the linear interpolation itsel. Principally any desired ractional rate-change actor can be implemented on this system without the need to change the number o coeicients. This is due to the act that the actual SRC with arbitrary rational actors takes place in the linear interpolator having a continuous- 148

8 From ADC Time-varying CIC ilter Fractional SRC H 1 M 1 H 2 M 2 H n M n Cascade or integer actor SRC Fractional ratechange actor Integer rate-change actor Msamples/s (GSM) M = ksamples/s (GSM) 80 Msamples/s Msamples/s (IS-95) M = M 1. M2 Mn M = Msamples/s (IS-95) Msamples/s (UMTS) M = Msamples/s (UMTS) (a) Fractional SRC placed irst From ADC H 1 M 1 H 2 M 2 H n M n Farrow structure Cascade or integer actor SRC Fractional SRC Integer rate-change actor Fractional ratechange actor M = ksamples/s (GSM) ksamples/s (GSM) 80 Msamples/s M = M 1. M2... Mn M = Msamples/s (IS-95) Msamples/s (IS-95) M = 10 8 Msamples/s (UMTS) Msamples/s (UMTS) (b) Fractional SRC placed last Figure 6. A cascaded structure or SRC (down to twice the bit/chip rate o the standard o operation). time impulse response. Any sample o this impulse response can be calculated. For urther details see [14]. When placing ractional SRC irst in the cascade (i.e., directly ater the ADC) and digital downconversion o the signal to baseband, all adjacent channel intererers are still part o the signal. Hence, the aliasing attenuation o the ilter or SRC must be much higher than in the previous case. This is where the anti-aliasing constraint is important. It states that the required high aliasing attenuation is necessary only in the very requency bands which contribute to aliasing in the channel o interest. Comb ilters suppressing these aliasing components result rom this idea. For ractional SRC, time-varying CIC ilters should be chosen. They achieve high attenuation in a narrow bandwidth (i.e., or high OSRs) and less attenuation as the bandwidth o the aliasing bands increases (i.e., the OSR decreases). Within the context o this example second-order time-varying CIC ilters suice. Concretely, they achieve 110 db aliasing attenuation or GSM, 70 db or IS-95, and 50 db or UMTS. A second-order time-varying CIC ilter requires one general-purpose multiplier and one ixed coeicient multiplier. The latter requires one coeicient to be stored in memory. For urther details on time-varying CIC ilters see [16]. Assuming a digitization rate o 80 Msamples/s, the eort o the two solutions is compared in Table 1. The Farrow structure is implemented on two times the target rate o the standard o operation (i.e., two times the bit rate o GSM, and two times the chip rate o IS-95 or UMTS, respectively). With ksamples/s the bit rate o GSM, Mchips/s the chip rate o IS-95, and 3.84 Mchips/s the chip rate o UMTS, the multiplication rates in million multiplications per second can be calculated. It can be concluded that the hardware eort or the time-varying CIC ilter is much lower, 149

9 Time-varying CIC ilter (sec- ond-order) Farrow structure (irst-order interpolation, 40 taps) Number o general-purpose multipliers 9 1 Number o ixed coeicient multipliers 0 1 Number o coeicients to store 80 1 Multiplication rate (millions o multiplications per second) or GSM or IS or UMTS Table 1. Eorts o the Farrow structure vs. time-varying CIC ilter or SRC. while the multiplication rate is lower or the Farrow structure. Hence, the Farrow structure is advantageously implemented i hardware eort is not an issue, or time-shared hardware is available (e.g., on a DSP), while time-varying CIC ilters have the great advantage o a small occupied chip area in an ASIC or FPGA. CONCLUSIONS Digital communications standards are generally based on dierent master clock rates. Thus, sample rate conversion is required in systems that process signals o dierent communications standards. In the context o sotwaredeined radio sample rate conversion must be realized digitally. conversion is a process o resampling. Since any sampling process causes aliasing and imaging, resampling also does. These two undamental characteristics o sampling require iltering. Thus, the design o systems or SRC is mainly a ilter design problem. Since it is the very characteristics which can destroy the signal, aliasing is the most important eect o SRC which must be avoided by proper ilter design. Since the constraints on the ilters are most relaxed at high oversampling ratios o the signal o interest, it is reasonable to place the most complex part o SRC, namely ractional SRC, at high sample rates. Feasible implementations or integer actor SRC can be ound by realizing block processing structures, or by properly actorizing the transer unctions o the ilters. Among the irst are the well-known polyphase decimators and interpolators, while CIC ilters belong to the second group. Based on time-varying realizations o the combination o block ilters or integer actor SRC with either an up- or a downsampler, systems or ractional SRC can be derived. These structures are parameterizable, and thus can adopt arbitrary rate change actors, which is required or sotware radio applications. ACKNOWLEDGMENT This work has been partially supported by the European Commission ACTS Sotware Radio Technology project. REFERENCES [1] T. Hentschel, M. Henker, and G. Fettweis, The Digital Front-End o Sotware Radio Terminals, IEEE Pers. Commun., vol. 6, no. 4, Aug. 1999, pp [2] H. Meyr, M. Moeneclaey, and S. A. Fechtel, Digital Communication Receivers: Synchronization, Channel Estimation and Signal Processing, Wiley, [3] R. E. Crochiere and L. R. Rabiner, Multirate Digital Signal Processing, Prentice Hall, [4] G. P. Fettweis et al., Breaking New Grounds Over 3000 MOPS: A Broadband Mobile Multimedia Modem DSP, ICSPAT 98, Toronto, Canada, Sept , [5] M. Weiss, F. Engel, and G. P. Fettweis, A New Scalable DSP Architecture or System on Chip (soc) Domains, ICASSP 99, Phoenix, AZ, Mar , [6] T. Hentschel, Systems or Sample Rate Conversion in Sotware Radio, Ph.D. thesis, in preparation, Dresden Univ. o Tech., [7] A. Feuer and G. C. Goodwin, Sampling in Digital Signal Processing and Control, Birkhauser, [8] N. J. Fliege, Multirate Digital Signal Processing: Multirate Systems, Filter Banks, Wavelets, Wiley, [9] C. W. Farrow, A Continuously Variable Digital Delay Element, Proc. IEEE Int l. Symp. Circuits and Sys., Espoo, Finland, June 1988, pp [10] M. E. Frerking, Digital Signal Processing in Communication Systems, Van Nostrand Reinhold, [11] E. B. Hogenauer, An Economical Class o Digital Filters or Decimation and Interpolation, IEEE Trans. Acoustics, Speech and Sig. Proc., vol. ASSP-29, no. 2, Apr. 1981, pp [12] T. Hentschel and G. P. Fettweis, Reduced Complexity Comb-Filters or Decimation and Interpolation in Mobile Communications Terminals, Proc. 6th IEEE Int l. Con. Elect., Circuits and Sys., Papos, Cyprus, Sept. 5 8, 1999, vol. 1, pp [13] T. Hentschel and G. P. Fettweis, Time-Varying Recursive Filters or Decimation and Interpolation, Proc. 10th Euro. Sig. Processing Con., Tampere, Finland, Sept. 5 8, [14] L. Lundheim and T. A. Ramstad, An Eicient and Flexible Structure or Decimation and Sample Rate Adaptation in Sotware Radio Receivers, Proc. ACTS Mobile Commun. Summit, June 1999, pp [15] T. Hentschel, M. Henker, and G. P. Fettweis, Sample Rate Conversion in Sotware Radio Terminals, ACTS Mobile Commun. Summit, Sorrento, Italy, June 1999, pp [16] M. Henker, T. Hentschel, and G. P. Fettweis, Time-Variant CIC-Filters or Sample-Rate Conversion with Arbitrary Rational Factors, IEEE 6th Int l. Con. Elect., Circuits and Sys., Paphos, Cyprus, Sept. 1999, pp BIOGRAPHY TIM HENTSCHEL [S 93] (hentsch@in.et.tu-dresden.de) received his M.Sc./Dipl.-Ing. degree in electrical engineering rom King s College London, University o London, U.K., and Dresden University o Technology, Germany, in 1993 and 1995, respectively. From 1995 to 1996 he was with Philips Communications Industries, Nurnberg, Germany. Since May 1996 he has been with the Mannesmann Mobilunk Chair or Mobile Communications Systems, working toward his Ph.D. His current research interests include sotware radio, speciically the design and investigation o digital signal processing algorithms or reconigureable ront-ends. GERHARD FETTWEIS [S 82-M 90-SM 98] (ettweis@in.et.tudresden.de) received his M.Sc./Dipl.-Ing. and Ph.D. degrees in electrical engineering rom Aachen University o Technology (RWTH), Germany, in 1986 and 1990, respectively. From 1990 to 1991 he was a visiting scientist at the IBM Almaden Research Center, San Jose, Caliornia, working on signal processing or disk drives. From 1991 to 1994 he was a scientist with TCSI, Berkeley, Caliornia, responsible or signal processor developments or mobile phones. Since September 1994 he has held the Mannesmann Mobilunk Chair or Mobile Communications Systems at Dresden University o Technology, Germany. He is an elected member o the SSC Society s Administrative Committee and the IEEE ComSoc Board o governors since 1999 and 1998, respectively. He has been associate editor or IEEE Transactions on CAS II, and is now associate editor or the IEEE J-SAC Wireless Series. 150