DIGITAL TRANSMITTER I/Q IMBALANCE CALIBRATION: REAL-TIME PROTOTYPE IMPLEMENTATION AND PERFORMANCE MEASUREMENT

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1 18th European Signal Processing Conerence (EUSIPCO-21) Aalborg, Denmark, August 23-27, 21 DIGITAL TRANSMITTER I/Q IMBALANCE CALIBRATION: REAL-TIME PROTOTYPE IMPLEMENTATION AND PERFORMANCE MEASUREMENT Olli Mylläri, Lauri Anttila, and Mikko Valkama Department o Communications Engineering, Tampere University o Technology P.O.Box 553, FI-3311 Tampere, Finland phone: + (358) , ax: + (358) , {olli.myllari, lauri.anttila, mikko.e.valkama}@tut.i ABSTRACT Nowadays, the direct-conversion and the low-if transceiver principles are seen as the most promising architectures or uture lexible radios. Both o the architectures employ complex I/Q mixing or up- and downconversion. Consequently, the perormance o the transceiver architectures can be seriously deteriorated by the phenomenon called I/Q imbalance. I/Q imbalance stems rom relative amplitude and phase mismatch between I- and Q-branches o the transceiver. As a result, sel-intererence or adjacent channel intererence is introduced. This paper addresses details o the real-time prototype implementation o the transceiver unit realizing widelylinear least-squares based I/Q imbalance estimation algorithm and corresponding pre-distortion structure proposed earlier by the authors. First the estimation itsel is reviewed and a recursive version o it is derived. Ater that, implementation related practical issues are addressed and implementation platorm is also briely introduced. Finally, implementation details and comprehensive RF measurement results rom the real-time implementation are presented. 1. INTRODUCTION The current trend in implementing uture wireless radio transceivers is to use the direct-conversion or the low-if transceiver architectures [1, 2]. However, there are still number o practical issues to be overcome beore these transceiver architectures can be ully implemented in uture wideband lexible transceiver units. In both architectures many transceiver unctions have been moved rom analog parts towards the digital signal processing (DSP) parts, thus enabling low-cost, simple, less power consuming and highly integrable transceiver unit [2]. One practical problem, however, is the sensitivity o such simpliied analog ront-ends (FE) to imperections o the used radio electronics. This is the central theme also in this article, with most ocus on the transmitter (TX) side. Both o the above transceiver architectures are based on analog complex in-phase/quadrature (I/Q) up- and downconversion which makes them vulnerable to amplitude and phase mismatch between I- and Q-branches. As a result, there is crosstalk between mirror requencies which yields, depending on the selected transceiver architecture, sel-intererence or adjacent channels intererence, when interpreted in requency domain. Other major nonidealities on TX side are local oscillator (LO) leakage and power ampliier (PA) nonlinearity which also contribute to signal deterioration [3]. Moreover, uture wireless systems demand higher transmission rates which yields wider bandwidths, higher order modulations and utilization o multi carrier schemes. However, signals with wider bandwidths and higher order modulations, and multi-carrier (MC) signals (e.g. OFDM) are especially sensitive to analog FE nonidealities [3, 4]. This paper ocuses to implementations related details and practical aspects o TX I/Q imbalance calibration scheme based on parameter estimation by widely-linear least-squares (WL-LS) approach and pre-distortion (PD) iltering. Special emphasis is on real-time prototype implementation and RF perormance measurements o a complete TX. The approach here is applicable or singlecarrier (SC) and MC signals. The paper is organized as ollows. First in Section 2 I/Q imbalance as a phenomenon and TX signal model are introduced, and selected PD structure is reviewed. Thereater in Section 3, recursive WL-LS approach-based I/Q imbalance parameter estimation is derived. Then implementation related problems are discussed in Section 4. Ater that, the implementation platorm is introduced in Section 5. Ater that, implementation details and measurement results are presented and analyzed in Section 6. Paper is concluded in Section 7. Notation: (.) denotes complex conjugation, (.) H hermitian transpose and convolution. All bold lower-case letters and uppercase letters denote vectors and matrices, respectively. 2. I/Q IMBALANCE AND DIGITAL PRE-DISTORTER STRUCTURE In an ideal I/Q TX, analog circuits in the I and Q branches have equal characteristics, but in practice, due to hardware manuacturing tolerances a perectly balanced analog FE is not achievable. In addition, electrical characteristics o analog components can undergo short time deviation due to e.g. temperature variation and, similarly, they are subjected to change over long time period due to aging. These physical limitations in the implementation accuracy o analog I/Q processing result in a inite attenuation o the image requencies and thus degrades the transmit signal quality. Current state-o-the-art transceivers have around 1 2% amplitude imbalance and 1 2 phase imbalance which yields about 3 4dB image rejection ratio (IRR) [2]. The approach in this paper to overcome I/Q imbalance problem is to use DSP techniques to compensate the I/Q imbalance eects. The DSP based calibration methods allow errors in the analog design and have an advantage o achieving good perormance without modiying the original transceiver architecture. In addition, adaptive DSP based approaches enable the possibility to ollow timevariant changes o the TX FE. 2.1 Signal Model In a wideband system context, the overall eective I/Q imbalance eects can vary as a unction o requency over the whole requency band and wider bandwidths are more vulnerable to the requencyselective behavior o I/Q imbalance [5]. Consequently, the I/Q imbalance can be modeled as requency-selective relative amplitude and phase dierence between the I and Q branches. In ollowing, g T and ϕ T are the I/Q mixer amplitude and phase imbalances, respectively. In addition, the non-ideal ilter characteristics between the I and Q branches is modeled with the ilters h I (t) and h Q (t). I signal bandwidth is narrow, the imbalance model is considered to be requency-independent and the ilters h I (t) and h Q (t) can be extracted rom the ormulation. For urther analysis, denote the ideal baseband equivalent transmit signal as z(t) = z I (t) + jz Q (t). The corresponding imbalanced baseband equivalent is then [6] x(t) = g 1 (t) z(t) + g 2 (t) z (t). (1) With urther derivation the impulse responses g 1 (t) and g 2 (t) can be shown to be g 1 (t) = [h I (t) + g T exp( jϕ T )h Q (t)]/2 and g 2 (t) = [h I (t) g T exp( jϕ T )h Q (t)]/2 [7]. In addition, the Fourier transorm EURASIP, 21 ISSN

2 (FT) o x(t) is X( ) = G 1 ( )Z( ) + G 2 ( )Z ( ). From X( ) the mirror requency attenuation can be ound to be IRR db ( ) = 1log 1 ( G1 ( ) I/Q Imbalance Compensation G 2 ( ) 2 ). (2) The aim o the I/Q imbalance mitigation is to remove conjugate term in (1) by properly pre-distorting the ideal TX data. Based on above imbalance model, and switching to discrete-time notations, the ollowing PD o the orm z p (n) = z(n) + w(n) z (n) (3) can be used [7]. Here w(n) represents the PD impulse response. From (1) and (3), it ollows that the pre-distorted and imbalanced signal is x p (n) = g 1,p (n) z(n) + g 2,p (n) z (n), where the modiied imbalance model impulse responses are g 1,p (n) = g 2 (n) + g 1 (n) w (n) and g 2,p (n) = g 2 (n) + g 1 (n) w(n). From this it can be derived that optimum solution or PD must satisy g 2,p (n) = g 2 (n) + g 1 (n) w(n) =, n. Solution can be seen more intuitively ater FT, as W OPT (e jω ) = G 2(e jω ) G 1 (e jω ), (4) where ω is normalized angular requency. In practice, however, this solution cannot be directly used or estimation because g 1 (n) and g 2 (n) are considered unknown. Thus, practical imbalance parameter estimation schemes using eedback rom RF back to TX digital parts are addressed next. The PD structure realizing above derivation can be seen in Fig. 1. In the igure, ater the real mixing, iltering and ADC, the DSP block perorms inal down-conversion rom the IF to baseband and consequent decimation and low-pass iltering. Moreover, DC oset removal, timing synchronization, I/Q imbalance parameter estimation and PD ilter calculation are perormed inside the DSP block. Here, real mixing is chosen to avoid any additional I/Q imbalance to the eedback loop (FBL) signal. 3.1 Block Least-Squares Approach Ater removing FBL delay the observed eedback data sequence can be ormulated as y(n) = Z(n)ĝ 1 + Z (n)ĝ 2 ] = [Z(n) Z (n)][ ĝ1 ] ĝ 2 ĝ1 = Z b (n)[, ĝ 2 where y(n) = [y(n) y(n 1) y(n L b + 1)] T, with L b denoting the length o the observed eedback data sequence and Z(n) is the convolution matrix ormed rom original TX data sequence z(n). I least-squares (LS) solution is ormed with auto-correlation data windowing method the estimation process gives biased results. Consequently, covariance or pre-windowing methods should be utilized. For covariance method the convolution matrix Z(n) o the original signal is ormulated in (6) [7, 8], where denotes the length o estimated imbalance ilters ĝ 1 and ĝ 2. Z(n) = z(n + 1) z(n) z(n L b + 1) z(n L b ) (5) (6) Corresponding observed eedback data sequence is y(n) = [y(n +1) y(n ) y(n L b +1)] T. The minimum phase imbalance ilter coeicients g 1 and g 2 best describing the data in the LS sense can be then solved rom [ ] ĝ1 = Z ĝ + b (n)y(n). (7) 2 In (7) Z + b (n) = (ZH b (n)z b(n)) 1 Z H b (n) is the pseudo-inverse o Z b (n). Finally the PD ilter coeicients can be solved rom equation ŵ = (Ĝ H 1 Ĝ1) 1 Ĝ H 1 ĝ 2, (8) z(n) Pre-Distortion z I(n)+jz Q(n) (.)* W(z) z p(n) DSP DAC LO DAC ADC IF FB LO LO PA r(t) where Ĝ H 1 is convolution matrix ormed rom ĝ 1, and ĝ 2 = [ĝt 2 ] T is a zero-padded version o ĝ 2 with 1 additional zeros. PD ilter w can be truncated to length N w, where 1 N w. 3.2 Recursive Least-Squares Approach Recursive LS () ollows the LS principle but it does not execute matrix inversions which makes it computationally more eicient than plain LS. Recursion has been implemented through matrix inversion lemma which gives tools to create matrix inversions in recursive manner. Following ormulation corresponds to above block LS with covariance data windowing: [8] Figure 1: Block diagram I/Q up-conversion based TX structure with calibration unctionality. 3. I/Q IMBALANCE PARAMETER ESTIMATION In this section the WL-LS estimation method described in [7] is briely reviewed and derivation o recursive version o it is introduced being particularly suitable or real-time implementations. Imbalance parameter estimation is in general based on a eedback signal capturing the complex envelope o the generated RF waveorm back to the TX digital parts. This is illustrated in Fig. 1. From now on, switching to vector-matrix notation or convenience. First, derive an estimator or g 1 and g 2, which include also FBL response, using time-domain model-itting approach. The aim is to ind estimates ĝ 1 and ĝ 2 which give the best it between original data sequence z(n) and observed eedback data sequence y(n). k(n) = λ 1 P(n 1)u(n) 1 + λ 1 u H (n)p(n 1)u(n) e(n) = y(n) ĝ H (n 1)u(n) (1) ĝ(n) = ĝ(n 1)k(n)e (n) (11) P(n) = λ 1 P(n 1) λ 1 k(n)u H (n)p(n 1) (12) where, u(n) = [z(n) z(n 1) z(n N + 1) z (n) z (n 1) z (n N + 1)], P() = δ 1 I and ĝ() =. δ is small positive constant to ensure non-singularity o the inverse P(n) o the covariance matrix ormed rom the original signal. From estimated imbalance vectors ĝ we get ĝ 1 = [ĝ() ĝ( 1)] T and ĝ 2 = [ĝ( ) ĝ(2 1)] T. Moreover, zeropadded versions ĝ 1 and ĝ 2 are ĝ 1 = [ ĝt 1 ]T and ĝ 2 = [ ĝ T 2 ]T both with 1 appended zeros. Ater this PD ilter coeicients ŵ(n) are solved again with recursive calculations (9) 538

3 compared to (8), basically in a similar manner as the estimation o ĝ. Only dierences are that equation (1) is changed to e(n) = ĝ 2 (n) ŵh (n 1)u(n), (13) where u(n) = [ĝ 1 (n) ĝ 1 (n 1) ĝ 1 (n + 1)] and equation (11) is getting the orm ŵ(n) = ŵ(n 1)k(n)e (n). (14) Again, PD ilter impulse response ŵ can be truncated to the length N w. 4. PRACTICAL ASPECTS There are a number o implementation related issues which have to be taken into account to attain maximum perormance or the algorithm. Namely, carrier requency oset (CFO), delay between FBL signal and original signal, FBL signal-to-noise ratio (SNR) and computational complexity o dierent adaptive algorithms. In this section, other adaptive algorithms ound in the literature are considered aside o the algorithm because it is computationally rather complex and perormance o the other algorithms have been compared to it. All Matlab simulations are based on requency-selective I/Q imbalance model with impulse response o length 3, where total amplitude response varies between.978 and 1.71, and total phase response varies between 1 and 7 degrees. Moreover, signal with 16-QAM modulation, 35 % roll-o, 5 times over-sampling, 1 MHz symbol rate, 5 MHz sampling requency, and MHz IF has been used. 1 independent simulation runs have been ran or each simulation. 4.1 CFO First o all, CFO o the FBL signal has to be within certain limits. This requirement should be trivial to ulill even with ree-running LO because requency source is usually common or up- and downconversion. For additional ino on requency synchronization see e.g. [9]. The basic impact how FBL CFO aects the average (integrated) IRR on the whole TX band can be seen in Fig. 2. From the igure it can be seen that CFO must be lower than 2Hz to achieve 6 db IRR. It is also worth noticing that Gauss-Newton () [8] algorithm outperorms other adaptive algorithms when considering FBL CFO. more demanding. Moreover, I/Q imbalance tends to bias FD estimates which makes the compensation even more demanding. The eect o FD between original signal and FBL signal on the IRR can be seen in Fig. 3 where perormance o dierent algorithms practically coincide. It can be seen that FD has signiicant eect on the perormance o the algorithm and residual FD less than 1.1 % gives over 6 db IRR. In addition, 1 % accuracy should be achievable with algorihtms ound in the literature, see e.g. [9]. Average IRR vs. ractional delay between original signal and eedback signa 8 LS 7 F Fractional Delay [%] Figure 3: Average IRR as a unction o ractional-delay between original signal and FBL signal. 25, samples used or I/Q imbalance parameter estimation. On the other hand, it has been discussed in [7] that with long enough imbalance ilters ĝ 1 and ĝ 2 the FD can be tolerated to some extent without separate FD compensation. In this paper, it is shown that longer imbalance ilters indeed relax FD compensation requirements. To achieve this, the assumption o imbalance ilters ĝ 1 and ĝ 2 being minimum phase has to be relaxed and delay to them has to be introduced. However, utilization o longer imbalance ilters requires higher FBL SNR. Comparison o IRR with dierent imbalance ilter lengths, and corresponding delays, can be seen in Fig. 4. The optimum delay is always D = ( 1)/2. From the Fig. 4, it can be clearly seen that algorithm perormance between integer delay multiples is signiicantly improved, and it can tolerate FD to some extent without perormance degradation. 8 Average IRR vs. eedback signal carrier requency oset 8 Average IRR as a unction o FBL delay with dierent =23, D= LS F Frequency oset [Hz] Figure 2: Average IRR as a unction o carrier requency oset. 25, samples used or I/Q imbalance parameter estimation =5, D=2 =15, D=7 =23, D=11 =3, w/o delay =3, w/o delay Fractional Delay [% o the sample interval] Figure 4: Average IRR with dierent ilter lengths and delays as a unction o delay between FBL signal and original signal. 25, samples used or I/Q imbalance parameter estimation. 4.2 Delay Compensation Another, more paramount requirement is delay estimation and compensation between original digital TX signal and digital FBL signal. Integer delay is easily estimated and compensated but estimation and compensation o ractional-delay (FD) has been ound to be 4.3 Feedback loop SNR Number o samples used or the estimation has also inluence on the perormance. From the Fig. 5 it can be seen that the SNR o the FBL signal should be over 3 db to keep the perormance degradation due to eedback noise negligible with the reasonable block 539

4 lengths discussed here. Fixed PD length results in a saturation o the IRR in Fig. 5. Longer PD lengths result in higher IRR. In the real-time implementation o this paper SNR o the FBL signal in the implementation is around 35 db. The SNR level was examined oline rom received FBL signal =5, IRR vs. eedback loop SNR =1, =1 =2 =3 =4 =5 =5, =1, =1 =2 =3 =4 = Feedback Loop SNR [db] 5.1 USRP and RFX24 USRP is a SDR platorm developed by Ettus Research. The USRP platorm is based on ield programmable gate array (FPGA) and it provides analog-to-digital converters (ADC), DACs, decimating/interpolating low-pass ilters, and PC connectivity [13]. Furthermore, it can be used as a low-if or direct-conversion transceiver which makes it especially suitable or perormance measurement o the implemented algorithm. USRP is connected to the PC with universal serial bus (USB) 2. interace which limits, in practice, the Rx/Tx bandwidth to 4 MHz. In the implementation here, the RFX24 transceiver daughter board (DB) is used. It can operate rom 2.3 to 2.7 GHz and has maximum transmission power o 17 dbm [13]. The DB has two RF antenna connections, one or hal-duplex transmit and receive called RX/TX and another or receiving called RX2. I RX/TX connection is used or transmitting and RX2 or receiving, the DB is capable o ull-duplex data transmission. The RFX24 has already airly good IRR igure o about 38 db but still insuicient or uture wireless systems. Block diagram o the RFX24 can be seen in Fig. 7. Figure 5: Average IRR with dierent parameter estimation lengths as a unction o SNR o the FBL signal. 4.4 Computational complexity Computational complexity o dierent adaptive algorithms is also a very important aspect o the implementation because computation power is always limited and computational burden should be kept as low as possible. In Fig. 6 it can be seen that and are clearly the most complex algorithms that have been considered. Approximate () [1] and Fast Approximate (F) [11] have complexity close to the normalized least mean squares () and their perormance is very good i problems discussed above have been solved properly. On the other hand, and algorithms outperorm other algorithms under more demanding conditions. Total number o calculations per iteration F Complexity o algorithms as a unction o length o pre distortion ilter w N w Figure 6: Computational complexity o adaptive algorithms as a unction PD ilter length. is o same length as N w. 5. REAL-TIME IMPLEMENTATION PLATFORM The development environment or the real-time prototype implementation consists o personal computer (PC), sotware deined radio (SDR) evaluation board and radio-requency (RF) daughter board. In this work, the evaluation board is Universal Sotware Radio Peripheral (USRP). The USRP together with daughter board and PC construct a ully unctional transceiver unit. In addition, this transceiver unit is deinable with computer sotware, namely U Radio [12, 13]. Figure 7: Block diagram o RFX24 DB and main connections to USRP. 5.2 U Radio U Radio (GR) is an open-source sotware running on Linux operating system which can be used with multiple hardware platorms rom a sound card to sophisticated (SDR) platorms, like USRP. Although GR supports multiple platorms, it is mainly intended to be used with the USRP. GR has also been built and installed on Mac OS X. Similarly, there has been attempts to install GR on Microsot Windows, but successes have not been reported so ar [12]. Python low graphs act as a ramework or GR applications. They consist o signal sources, signal processing blocks and signal sinks. Though, signals in GR are discrete time signals, they are processed in block wise manner [14]. GR includes large variety o built-in signal processing blocks. All signal processing blocks are written in C++ or Python programming languages [12, 15]. C++ programming language is considerably more eicient than Python and it has much better ability to execute computationally complex calculations. As a result, blocks with elaborate unctionality are programmed in C++ language [16]. 6. IMPLEMENTATION AND MEASUREMENT EXAMPLES RX/TX antenna connection o the RFX24 was used as a RF output and RX2 antenna connection as FBL RF FE. Physical connections o the implementation can be seen more clearly in block diagram o Fig. 8. Implementation was built on GR sotware by writing C++ signal processing blocks (SPB) or FBL signal synchronization, I/Q imbalance estimation and PD. Additionally, own interaces to USRP were written to get better controllability o digital IF and to enable real downconversion in FBL. Also GR Companion (GRC) graphical user interace (GUI) blocks were written or programmed SPBs to get easier usability o overall transceiver. Arbitrary 16-QAM data sequence was generated on-line in each measurement made with prototype implementation. 54

5 In the implementation, the accuracy o TX and FBL RX oscillator signals are very good (in the order o 1 Hz), and thus no additional CFO mitigation is here implemented. Integer delay estimation was perormed with ast FT (FFT)-based correlator and FD was estimated with non-data-aided (NDA) Maximum Likelihood (ML) algorithm ound in [9]. Additionally, the perormance o the NDA ML synchronization algorithm was improved with simple interpolating polynomial itting approach. Integer delay was compensated by changing vector indexing and FD was compensated with look-up-table (LUT)-based FD iltering. The LUT includes 1 all-pass FD ilters o order 32 generated o-line, thus giving an accuracy o 1 % o the sample interval or the compensation. For urther inormation about FD ilters, see e.g [17]. Integer delay compensation does not increase computational complexity but FD compensation needs additional 32 multiplications and summations or each output sample. Block diagram o the main implementation DSP unctionalities can be seen in Fig. 8. Moreover, parameters or I/Q imbalance estimation in the measurements have been λ = 1 and δ =.1. Original signal Integer Delay Estimation & Removal PC + U Radio Fractional-Delay Estimation & Removal Pre-distortion I/Q Imbalance Estimation DC Oset Removal USB USRP + RFX24 RX/TX RX2 Rohde&Scwarz FSG SPLITTER ATTENUATOR Figure 8: Block diagram o the measurement setup where connections and signal low can be seen. Measured spectra are obtained and saved with Rohde&Schwarz FSG spectrum analyzer with measurement setup seen in Fig. 8. In Fig. 9 are USRP output spectra with dierent PD lengths. Finite image rejection o I/Q mixer on RFX24 can be seen as rather strong mirror image at 2455 MHz. The perormance o the I/Q imbalance mitigation on low-if signal is very good or all PD lengths. Spectrum plot show over 55 db average IIR igure which can be considered suicient or uture lexible transceivers. Note that the spike at 2456 MHz is due to the LO leakage o the TX which could be compensated with PD [18] but it has not been considered here. Lower perormance o the PD with 2 and 3 taps could be explained with estimation noise due to the FBL SNR, phase noise, residual time synchronization errors or other impairments which have not been taken into account. Magnitude [db] Without PD With PD, 1 tap With PD, 2 tap With PD, 3 tap LO Leakage USRP output spectrums Frequency [MHz] Figure 9: Output spectrum o USRP without and with I/Q imbalance calibration algorithm. Signal with 16-QAM modulation, 1 MHz symbol rate, 1 MHz TX IF, 4 MHZ RX IF, 35 % roll-o, 4 times over-sampling. PD lengths 1, 2 and 3, and 25, samples used or estimation. 7. CONCLUSIONS This article ocuses on complex I/Q up-conversion based TX architectures and especially the I/Q imbalance problem in them. An eicient digital PD based imbalance calibration method was presented, with most ocus on prototype implementation related aspects and corresponding calibration perormance evaluations. The estimation algorithm and PD structure discussed was shown to be implementable with rather easible computational resources and it was shown to oer excellent calibration perormance. The reliability o the estimation algorithm is practically dependent on the exact delay compensation which was proved to be a demanding task. This prototype implementation gives good basis on uture research and work to realize possible FPGA based solutions. Future work will also include real-time prototype implementation o joint PA nonlinearity and I/Q imbalance mitigation algorithm [18]. REFERENCES [1] S. Mirabbasi, and K. Martin, Classical and modern receiver architectures, IEEE Commun. Mag., vol. 38, pp , Nov. 2. [2] P-I. Mak, S-P. U, and R.P. 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