A Study of PN Junction Diffusion Capacitance of MOSFET in Presence of Single Event Transient

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1 Journal of Electronic Testing (217) 33: A Study of PN Junction Diffusion Capacitance of MOSFET in Presence of Single Event Transient Tengyue Yi 1 & Yi Liu 1 & Yintang Yang 1 Received: 14 July 217 /Accepted: 14 November 217 /Published online: 1 December 217 # Springer Science+Business Media, LLC, part of Springer Nature 217 Abstract In this paper, a 65 nm MOSFET 3D structure is built based on Technology Computer Aided Design (TCAD) 3D device simulation software, and the single-event transient (SET) effect in 65 nm CMOS inverter is analyzed using TCAD-HSPICE mixed-mode simulation based on heavy ion model. The formation and function of the PN junction diffusion capacitance in the Metal-Oxide-Semiconductor (MOS) device are discussed by analyzing the drain and substrate voltage characteristics of the device under the SET effect. Then the sub-circuit structure of this device for SET is established, and the mechanism of the diffusion capacitance of PN junction during the heavy ion action process is verified comparing with the results of sub-circuit HSPICE simulation results and the TCAD-HSPICE simulation results. Finally, A sub-circuit model is provided, to support circuit-level simulation of single-event effects. Keywords Single event transient. diffusion capacitance. sub-circuit 1 Introduction In space environment, single-event effects (SEE) are important factors in the functional failure and performance degradation of the circuits [1, 3, 11, 14, 15]. However, the experiment and measurement methods for a real circuit with SEE are limited, and the cost of such experiments is very high. Structural simulation methods are important for evaluating circuit characteristics in the presence of SEE and guiding the measurement of real circuits with SEE in the future. Therefore, the establishment of HSPICE device model is necessary for supporting the circuit level SEE simulation. Previous research on the mechanism and circuit level model approach of SET has covered various aspects. Due to the substrate s doping type of MOS device being opposite that of the source and the drain, a parasitic lateral Bipolar Junction Transistor (BJT) is formed. Thus the SEE will be enhanced by this BJT. The mechanism and the approach of HSPICE model have been studied by several authors [8, 9, 12]. The particle that strikes the device can be equivalent to a current source, Responsible Editor: V. D. Agrawal * Tengyue Yi yty82@126.com 1 Laboratory of Digital IC and Space Application, School of Microelectronics, Xidian University, Xi an 7171, China and a large amount of research assumes double-exponential type current sources. Black et al. have modified the traditional double-exponential current source model and proposed an improved double-exponential current source model [2]. However, the mechanism and model of the PN junction diffusion capacitance of MOSFET for SET have not been discussed. The source / substrate and drain / substrate of a MOSFET are two parasitic PN junctions. Under normal working conditions, the substrate of PMOS is connected to VDD and the substrate of NMOS is grounded. These two PN junctions are zero biased, reversely biased or slightly positively biased. For NMOS, the sensitively biased state is that the gate voltage Vg =, and for PMOS, the sensitively biased state is that the gate voltage Vg = 1.2 V. When an ion bombards the drain of a MOSFET in sensitively biased state, the drain voltage and the substrate voltage are changed, and these two PN junctions are positively biased, thus two larger positively biased diffusion capacitances are established [1]. When the drain level of a MOSFET is recovered, the two parasitic PN junctions are again under negatively biased state or zero biased state. At the same time, the diffusion capacitance disappear. Thus characteristics of substrate s voltage will be influenced by the PN junction diffusion capacitance due to the heavy ion bombardment process. Although many electrical characteristic parameters inside a device cannot be measured by experiment during the particle

2 77 J Electron Test (217) 33: action process, these parameters can be obtained by TCAD tools. Thus TCAD can be used to study the mechanism and to support the establishment of HSPICE model. In this paper, the mechanism of the PN junction diffusion capacitance is analyzed base on the results of the TCAD- HSPICE mixed-mode SET simulation. The equivalent subcircuit of PMOS for SET is established. The results of TCAD-HSPICE mixed-mode simulation are compared with the results of the sub-circuit HSPICE simulation. By comparison, the mechanism of the PN junction diffusion capacitance is verified, and the sub-circuit model is established. Fig. 1 shows the main contribution of this paper. 2 TCAD-HSPICE mixed-mode simulation Based on the HSPICE model of 65 nm CMOS process device provided by Semiconductor Manufacturing International Corporation (SMIC), the electrical characteristic curves are obtained. By adjusting the doping parameters and size parameters in TCAD to fit the electrical characteristic curves, the parameters of the devices are obtained, and then the 3D TCAD structure of 65 nm CMOS device is established. Table 1 shows the main parameters of PMOS in 65 nm CMOS inverter. Then, the TCAD-HSPICE mixed-mode simulation was carried out on SET of the PMOS in 65 nm CMOS inverter. In this simulation, 3D TCAD model was used for PMOS, while for NMOS, HSPICE model was used. In order to simulate the actual working environment of the PMOS, the active area of the NMOS is retained in the 3D TCAD structure. Fig. 2 shows the 3D TCAD structure of the PMOS in 65 nm CMOS inverter which is established by using Cogenda Table 1 Main parameters of PMOS in 65 nm CMOS inverter Channel Length(nm) 6 Channel Width(nm) 585 Gate Oxide Thickness(nm) 1.5 Source/Drain Doping Concentration(cm 3 ) 1e2 Source/Drain Diffusion Zone Doping Concentration(cm 3 ) 1e19 Substrate Doping Concentration(cm 3 ) 2e17 VisualTCAD software [13]. The trajectories of the Chlorine (Cl) ions (E = 138 MeV, LET = 15 MeV cm 2 /mg) are obtained by the GSEAT simulation tool, and the core of the tool is GEANT4. Fig. 3 shows the particle trajectories formed by the Chlorine ions vertically bombarding the PMOS drain center, which is generated by Cogenda GSEAT simulation tool [4]. A particle trajectory is loaded into the PMOS 3D structure for TCAD-HSPICE mixed-mode simulation. 3 The equivalent sub-circuit of PMOS on SET To verify the mechanism of the diffusion capacitance, a SET equivalent sub-circuit is built [8, 9, 12], and the results of TCAD-HSPICE mixed-mode simulation and the results of sub-circuits HSPICE simulation are compared. In this section, the method of the equivalent sub-circuit of PMOS for SET is introduced. The results of different simulations are discussed in the next section. For PMOS, the source-substrate-drain constitutes a parasitic lateral PNP type BJT, the well resistance exists in the substrate, and the source/substrate and the drain/substrate form Fig. 1 Contribution of this paper Fig. 2 The 3D TCAD structure of the PMOS in 65 nm CMOS inverter

3 J Electron Test (217) 33: Fig. 3 The trajectories of Chorine ions that bombard the PMOS drain center two parasitic PN junctions. When the drain of the device is bombarded by a heavy ion, a transient current is generated. Due to the current flowing through the substrate, the substrate voltage is pulled down, thus the parasitic lateral BJT is transformed to a state of saturation bias and the SET is enhanced by the parasitic lateral BJT [8, 9, 12]. Since the drain voltage is recovered, the parasitic BJT is recovered to a state of cutoff bias. With the existence of the PN junction diffusion capacitance during the heavy ion bombardment process, the voltage pulse of the substrate of the MOSFET is extended. Fig. 4 shows the equivalent sub-circuit structure of the PMOS for SET. In Fig. 4, Q1 is the parasitic lateral PNP type BJT in the PMOS. A 3D PMOS was built on TCAD software, the gate is connected to 1.2 V, and DC simulation was done on the substrate, source and drain. The main parameters (IS, NF, BF, NE, ISE, IKF) of the parasitic BJT are obtained by TCAD S B C2 P12ll Rb Q1 C1 simulation, and the parameters of this BJT are: IS = 2.e-2, NF = 1.1, BF = 1.3, NE = 12, ISE = 7.e-12, IKF = 7.e-2 [6]. C1, C2 represent the two diffusion capacitors of the drain/substrate parasitic PN junction and source/substrate parasitic PN junction respectively, and the C-V relation for them are obtained by TCAD AC simulation. Two voltage controlled capacitors (VCCAP) are used to simulate these two PN junction diffusion capacitors, and the parameters of these two capacitors are as shown in Table 2 [7]. Iion is the heavy ion equivalent current source, which can be described by double-exponential model. The basic expression of the double-exponential current source model is given by Eq. (1): 8 ; t < t d1 ðt td1 Þ <I ; t d1 < t < t d2 Peak 1 e ð1þ I ðt Þ ¼ ðt t Þ ðt t Þ d1 d1 ; t t d2 e : I Peak e where, td1 is the onset of the rise of the current, td2 is the onset of the fall of the current, IPeak is the maximum current to be approached, is the rise time constant, and τ2 is the fall time constant [2], their values are: td1 =, td2 = 5 ps, IPeak = 3.8 ma, = 1.2 ps, τ2 = 3 ps. Rb is the substrate resistor, and its value is 4 K ohms. Iion Table 2 D Fig. 4 The sub-circuit structure of the PMOS for SET The parameters of the two diffusion capacitors Voltage(V) Capacitance(fF)

4 772 J Electron Test (217) 33: Simulation Results and Discussion By the TCAD-HSPICE mixed-mode simulation, the transient characteristics of the PMOS on SET are observed. Fig. 5 shows the drain voltage (V drain ) and the substrate voltage (V base ) waveforms of the PMOS in TCAD-HSPICE mixedmode simulation. The width of the output voltage pulse (V drain ) is about 2 ps, which is consistent with the test data of National University of Defense Technology [5]. It is obvious that the maximal bias voltage (V drain -V base ) of the parasitic PN junction can reach 8 mv or more during the heavy ion bombardment process. For PN junction, there is only a small reverse bias capacitor when it is in states of reverse bias, zero bias or slightly positive bias, and a larger positive partial diffusion capacitance is formed when it is in a state of strongly positive bias [1]. When the PMOS is bombarded by a heavy ion, the two parasitic PN junctions form two diffusion capacitors. Together with the well resistor, they form a RC network, and the substrate voltage V base waveform in Fig. 5 is exactly the characteristics of the RC discharge network. As the voltage is recovered, the two parasitic PN junctions recover to negative and zero bias states, respectively, and the diffusion capacitance disappears. The simulation of normal sub-circuit and sub-circuit without these two diffusion capacitors C1 and C2 is done, and the results of these sub-circuits HSPICE simulations are compared with the results of the TCAD-HSPICE mixed-mode simulation. Fig. 6a and b show the substrate voltage and drain current waveforms of the PMOS in TCAD-HSPICE simulation and different sub-circuits simulations. By comparing the results of different simulations, it is obvious from Fig. 6athat the tail of the substrate voltage waveform of the PMOS in the sub-circuit without the two diffusion capacitors C1 and C2 HSPICE simulation is much shorter than that in normal subcircuit HSPICE simulation and in TCAD-HSPICE mixedmode simulation. In Fig. 6b, for the case without diffusion capacitors C1 and C2, there is a clear overshoot at the beginning of the drain current waveform in the sub-circuit HSPICE Voltage (V) V drain V base t*1-1 (s) Fig. 5 The drain voltage (V drain ) and the substrate voltage (V base ) waveforms of the PMOS in TCAD-HSPICE mixed-mode simulation V base (V) I drain (Am) simulation. Thus, the mechanism of the diffusion capacitance is verified, and a SEE equivalent sub-circuit model is established. 5 Conclusion The sub-circuit with Cap fits better Mixed Mode HSPICE With Cap. HSPICE Without Cap t * 1-1 (s) (a) The voltage characteristic curves Mixed Mode HSPICE With Cap HSPICE Without Cap An Overshoot t *1-11 (s) (b) The current characteristic curves Fig. 6 The substrate voltage waveforms and drain current waveforms of the PMOS in different sub-circuits HSPICE simulations and TCAD- HSPICE mixed-mode simulation The mechanism of PN junction diffusion capacitance of MOSFET with SET is discussed based on TCAD-HSPICE mixed-mode simulation. It is verified by comparing TCAD- HSPICE mixed-mode simulation and different sub-circuit HSPICE simulation results. With the introduction of the PN junction diffusion capacitances in equivalent sub-circuit, an RC network is formed. Thus, the tail of the substrate voltage waveform is extended, which fits well with TCAD-HPICE

5 J Electron Test (217) 33: mixed-mode simulation results. This study establishes an HSPICE model of MOS device for SET effects and the study supports the circuit level simulation. In the future, a more comprehensive HSPICE model need to be established, and many other factors need to be considered. The HSPICE model approaches of MOS devices with different particle parameters (incident position, incident angle, trajectory length, LET, etc.) and different layout styles remain to be further studied. Acknowledgment This research was partially supported by Equipment Pre-research Project of China. References 1. Artola L, Gaillardin M, Hubert G, Raine M, Paillet P (215) Modeling Single Event Transients in Advanced Devices and ICs. IEEE Trans Nucl Sci 62(4): Black DA, Robinson WH, Wilcox IZ, Limbrick DB, Black JD (215) Modeling of Single Event Transients With Dual Double- Exponential Current Sources: Implications for Logic Cell Characterization. IEEE Trans Nucl Sci 62(4): Ferlet-Cavrois V, Massengill LW, Gouker P (213) Single Event Transients in Digital CMOS A Review. IEEE Trans Nucl Sci 6(3): GSEAT 1.9.: User s Guide (217) Cogenda Pte Ltd. Su Zhou, China 5. He YB, Chen SM (212) Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology. IEEE Trans Nucl Sci 59(6): HSPICE Reference Manual: Elements and Device Models (213) Synopsys. California, USA 7. HSPICE User Guide: Basic Simulation and Analysis (213) Synopsys. California, USA 8. Kauppila JS, Massengill LW, Ball DR, Alles ML, Schrimpf RD, Loveless TD, Maharrey JA, Quinn RC, Rowe JD (215) Geometry- Aware Single-Event Enabled Compact Models for Sub-5 nm Partially Depleted Silicon-on-Insulator Technologies. IEEE Trans Nucl Sci 62(4): Kerns SE, Massengill LW, Kerns DV, Alles ML, Houston TW, Lu H, Hite LR (1989) Model for CMOS/SOI Single-Event Vulnerability. IEEE Trans Nucl Sci 36(6): Laux SE, Hess K (1999) Revisiting the Analytic Theory of p-n Junction Impedance: Improvements Guided by Computer Simulation Leading to a New Equivalent Circuit. IEEE Trans Electron Devices 46(2): Liu Z, Chen SM, Liang B, Liu BW, Zhao ZY (29) Research on bipolar effect in single-event transient. Acta Phys Sin 59(1): MacSweeney D, McCarthy KG, Mathewson A, Mason B (1998) A SPICE Compatible Subcircuit Model for Lateral Bipolar Transistors in a CMOS Process. IEEE Trans Electron Devices 45(9): VisualTCAD 1.7.2: VisualTCAD User s Guide (217) Cogenda Pte Ltd. Su Zhou, China 14. Wang H-B, Mahatme N, Chen L, Newton M, Li Y-Q, Liu R, Chen M, Bhuva BL, Lilja K, Wen S-J, Wong R, Fung R, Baeg S (216) Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology. IEEE Trans Nucl Sci 63(1): Ziren L, Minxuan Z (213) Research on SETand Charge Collection in Nano Integrate Circuits. Changsha China. Graduate School of National University of Defense Technology Tengyue YI was born in Anhui, China, in 199. He received the B.S. degree from Xi an University of Posts & Telecommunications in 212 and M.S. degrees from the Xidian University in 215. Now, he is pursuing the Doctor s degree in Microelectronics and Solid State Electronics at the Xidian University. His research interests include mechanisms and model technologies of MOSFET on single event effects. Yi LIU was born in Shaanxi, China, in He received the B.S., M. S. and Ph.D. degrees from Xidian University in 1992, 1997 and 21, respectively. He has been a Professor with the School of Microelectronics, Xidian University, since 212. Yintang YANG was born in Hebei, China, in He received the B.S. and M.S. degrees in microelectronics and solid state electronics from Xidian University, Xi an, China, in 1982 and 1984, respectively, and the Ph.D. degree in electronic science and technology from Xi an Jiaotong University, Xi an. He has been a Professor with the School of Microelectronics, Xidian University, since 1997.