Feature-level Compensation & Control

Transcription

1 Feature-level Compensation & Control

2 2 Lithography Andy Neureuther and Costas Spanos, UCB Workshop 11/19/ /19/ Lithography

3 3 Lithography: Andy Neureuther, UCB Research Themes: Blowing the horn for CAL Linking Process and EDA through multi-student test structure design, patternmatching and experiment Photomasks as precision instruments for monitoring projection printing Fast EM Analysis methods to attain speeds required for OPC and die-todatabase inspection 11/19/ Lithography Zernike.txt Mask Layout Aerial Image Simulator IFT SPLAT Pattern Matcher Match Location(s) Pattern (coma)

4 4 Program Goals Year I Establish multi-student project Process-EDA test-structure Combine multiple feature size, proximity spacing and field polarity teststructures with circuit design elements into a mask layout. Use mask to study feature level scale and layout dependent effects in mask making, lithography (ASML-DUV), etching (Centura) and CMP (Berkeley apparatus). Understand impact of these effects on circuit designs. Establish Practical PSM-Precision Instrument Implementation Develop mask layout descriptions for aberration, illumination, and phaseetch depth monitors that mitigate mask making and quantitative interpretation issues (writing tolerance, writing time, and maximize simplicity in quantitative interpretation). Develop, benchmark and utilize the fast-cad Combine domain decomposition using edges (DDE) with libraries of scattering analysis of small regions to evaluate the speed and accuracy and utilize the simulation tool to establish guidelines for PSM printing issues. 11/19/ Lithography

5 5 APPLY SRC DEVELOPED CODE: Pattern Matching Methods for Linking TCAD and EDA Frank Gennari AB-CAD prototype linking TCAD and EDA Extended to residual effects of plasma-etch, laser thermal annealing and CMP New data structures and algorithms give OPC speed PATTERN SPLAT AB-CAD.gds Extracted Match Region LAYOUT Aberrations Alignment Defects PSM Reflective Notching Reflection from Slope Multilayer Laser Assisted Thermal Processing Thermal Conduction Image CMP Dishing Procedural based on distances and density Large Areas 3x3mm abacus IC 11/19/ Lithography An entire layer of a 417mm µm microprocessor can be processed in less than an hour on a 1GHz PC

6 6 Test Structures for Linking Process and EDA Invented illumination monitors: Linear-phase grating illumination steering and Concentric-spillover Greg McIntyre 90 probe Invented PSM performance monitor Greg will lead the development of multistudent project photomasks with test patterns and circuit layout snipits. 11/19/ Lithography

7 7 Multi-Student Process-EDA Test-Mask Edward Hwang Garth Robins Greg McIntyre Jason Cain Jihong Choi Ling Wang CMP Aberration Illumination, PSM phase error, plasma etch Metrology CMP CMP Point of Contact: Greg McIntyre, EECS, UC Berkeley office (510) , Mask info: All dimensions are for mask in um (unless otherwise noted) ; Wavelength = 248nm; 4 phase etches (0,90,180,270); Main field size = 105 x 105 mm (noted by border); Dark field mask; Alignment markers are for ASML PAS 5500/90 (our microlab stepper); Will also be used on ASML: 4x.63na, 4x.7na, & 4x.8na 11/19/ Lithography

8 11/19/ Lithography 8 PC Layout Viewer for GDSII on CD-ROM Creator: Frank Gennari, UC Berkeley EECS/TCAD Named simpl_display because it originally displayed simpl-dix files Default view of layout PC/Windows layout tool OpenGL interactive graphical support Performance optimized for large layouts Inputs: GDS, GDSII, CIF, patterns Outputs: GDSII, JPEG, RAW, BMP User-defined layer colors and patterns Operations: Display, measure, flatten, image capture Send questions and feedback to gennari@eecs.berkeley.edu

9 9 Master Layout I2 I2 A2 A2 P MB I1: Illumination 1 C1 C1 A2 P: Phase error E A2I2 MB A1: Aberration (4tools) A2 E A2 A2: Aberration (1tool) P P P MA: Metrology (A) A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 R I R R I MB: Metrology (B) MA MA MA MA MA MB MB R: Resist E: Etch (plasma) A2 A2 C1, C3: CMP C3 C1 C1 I2A2 11/19/ Lithography A2 E P A2I2

10 10 Illumination Example LPR, 10C (6-7rings, sigma_c = 1.0) Diameter = 12.94um (mask) Pitch = 1.57um ; Pitch/4 = nm Example LPG Pupil shift = 315 deg 11/19/ Lithography

11 11 Phase-Shift Self-Testing Phase and Intensity Probe size: 1um (A) 0-180,90 : patterns with 90 probe 11/19/ Lithography

12 12 Aberrations: Pattern-and-Probe 11/19/ Lithography

13 13 Metrology 11/19/ Lithography

14 14 Resist: Double-Exposure with Dipole 11/19/ Lithography

15 15 CMP: Serpentine, Orientation, Loading Serpentine wires 5x) Linewidth / spacewidth a).25um /.25um b).25um / 25um c) 100um /100um d) 100um / 10um 11/19/ Lithography

16 16 Plasma Etch: Surround Loading 11/19/ Lithography

17 17 Experimental Verification of Layout Effects LAVA website applets Chemically Amplified Resists Partial coherence Hideaki Oshima Undergraduate Hideaki will assist in processing test-patterns on the Applied Centura etcher and the ASML DUV stepper. 11/19/ Lithography

18 18 Using previously developed diagnostics in Centura TM The On-Wafer Ion Flux Probe for Uniformity Poly-Si etch rate T. W. Kim, S. J. Ullal, V. Vahedi, and E. S. Aydil, An On-Wafer Probe Array for Measuring Two-Dimensional Ion Flux Distributions in Plasma Reactors, Rev. Sci. Instrum. 73, 3494 (2002). 11/19/ Lithography

19 11/19/ Lithography 19 Sub-65nm CMOS: Tsu-Jae King, UCB Interests: Dry Etching, and Silicon-Germanium Formation of high-aspectratio lines and contact holes for advanced transistor structures (e.g. ultra-thin SOI FETs, FinFETs); plasma-induced damage Carrier transport and dopant diffusion in SiGe for enhanced CMOS Research Themes: GATE FinFET Transistor 10 nm 20 nm SOURCE Impact of aggressive etch processes on performance and reliability of advanced transistor structures DRAIN Application of Si-Ge for enhancing carrier transport and controlling dopant diffusion in advanced transistor structures

20 20 Future Goals on Process-EDA Test-Structure Masks Year 1: Broad set of processes on tools at Berkeley: layouts; screening for effects and length scale; correlation with EDA Year 2: Identify and quantify key parameters: modeling to design patterns and interpret results; EDA predictability Year 3: Industry acceptable: mitigate area, write-time; simulation calibrated interpretation, EDA calibration data Year 4: Emerging processes: screening; modeling; EDA calibration data 11/19/ Lithography

21 21 Pattern-And-Probe Characterization Technology (λ/na) (λ/na) (λ/na) Defocus Spherical HO Spherical Garth Robins Developed pattern-and-probe aberration monitors on SFR including target operation and relate sensitivity, cross-talk, overdrive, etc. to discretization in space and phase through theory and simulation. Mask phases yellow = 0 green = 90 red = /19/ Lithography Coma (λ/na) HO Coma Experimentally demonstrate and develop the quantitative usefulness of targets in industrial practice and science in collaboration with industry and colleagues. (λ/na)

22 22 σ = Target Operation: Defocus Add electric fields from probe & rings, taking into account the coherence at the probe position Intenisty (100%CF) X-position (λ/na) 0 RU = 0.43 ½ RU = 0.42 Intenisty (100%CF) + 11/19/ Lithography Intenisty (100%CF) X-position (λ/na) X-position (λ/na) 0 RU = 0.70 ½ RU = RU = 0.56 ½ RU = 0.72

23 23 Target Response: Defocus 11/19/ Lithography

24 Defocus Results for Focus-Exposure 24 +f Die center f-steps: 100nm (~1/2 RU) -f +E 9.1mJ A higher exposure could re-center at best focus Can be read to 25nm (4 more change) May be sufficient to see effects of inter-die wafer shape 11/19/ Lithography -E E-steps: 0.3mJ/cm 2

25 25 Future Goals on PSM as Precision Instruments Year 1: Broad set of applications in addition to aberrations: demonstrate sensitivity and orthogonality; simulation and modeling calibration Year 2: Industry acceptable versions and compare with existing alternatives: mitigate area, write-time, interpretation Year 3: Combine with zero foot print sensor technology and demonstrate for projection printing Year 4: Application to emerging technologies (immersion) and multi-step process issue (flare-plasma loading) 11/19/ Lithography

26 26 Fast-CAD for Phase-Shifting Masks and Defects clear polygon E y. y z x L x edges subject to TE(//) polarization edges subject to TM( ) L polarization unaffected y field through Cr-layer edge shadow regions z E z y y x 50nm 180deg 80nm Cr. E 180deg y y 50nm x Michael Lam SFR work on polarization effects of masks and the design of masks for monitoring polarization. 11/19/ Lithography Domain Decomposition Using Edges from K. Adam on SFR Extend Domain Decomposition by Edges (edge-ddm) to attain speeds required for optical proximity comparison (OPC) and die-to-data base inspection. 80nm Cr

27 27 MatLab to C Transition Successful transfer of DDE algorithm to the C platform: Old version: MatLab Cluttered mass of pattern specific MatLab scripts and functions. New Version: C platform Consolidated algorithm to a few files Increased flexibility by allowing generation of any Manhattan pattern Increased Speed of at least 3-4X on simple contact patterns 11/19/ Lithography

28 28 Testing:Manhattan Layout TM Polarization 10µm x 10µm 11/19/ Lithography

29 29 Future Goals on Fast-CAD Year 1: Domain Decomposition Edges plus libraries of small geometries; evaluate speed-accuracy issues Year 2: Inspection; adapt to larger illumination angles and high-na Year 3: Die-to-database; characterize trade-offs in accuracy and speed Year 4: Emerging processes: mask-less lithography and laser assisted processing 11/19/ Lithography

30 30 Manufacturing Issues in Extreme Ultraviolet Lithography Jason P. Cain, Prof. Costas J. Spanos, UC Berkeley Performed experiment and simulation-based research into use of scatterometry for measuring line edge roughness. Results showed that the method was infeasible at DUV wavelengths. Conduct initial experiments on characterization of the EUV lithography setup at LBNL. 11/19/ Lithography

31 31 Measuring Flare in the MET Optic Flare (scattering due to mid-spatial frequency lens imperfections) is a serious concern for EUVL Test patterns placed on current EUV mask to measure flare at nine different points in the field To measure flare, an experiment is required which controls for important processing parameters Cross patterns for flare measurement 11/19/ Lithography

32 32 Characterizing PEB Sensitivity of EUV Resists Careful characterization of PEB plate uniformity is required to separate PEB effects from other effects of interest Use wireless sensor wafers: Developed under SFR program and commercialized Able to measure spatial and temporal temperature uniformity Initial work under way to characterize plates used at LBNL. 11/19/ Lithography

33 33 Scatterometry for Small-Feature Metrology Source Detector Sample Can scatterometry at DUV wavelengths be successful at EUV technology nodes? Periodic gratings with 40 and 65 nm linewidths placed on current test mask for scatterometry Current work: n, k measurements for EUV resists Library building 11/19/ Lithography

34 34 Future Goals on EUV Control Complete initial characterization experiments Flare PEB plate characterization Aberration measurements Investigate scatterometry as a metrology tool for feature sizes required at EUV nodes Design novel test structures for EUVL system characterization (e.g., aberration measurements using PSM) 11/19/ Lithography