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1 doi:.8/nture9749 Progrmmle nnowire circuits for nnoprocessors Ho Yn *, Hwn ung Choe 2 *, ungwoo Nm *, Yongjie Hu, hmik s 4, Jmes F. Klemic 4, Jmes C. Ellenogen 4 & Chrles M. Lieer, A nnoprocessor constructed from intrinsiclly nnometre-scle uilding locks is n essentil component for controlling memory, nnosensors nd other functions proposed for nnosystems ssemled from the ottom up. Importnt steps towrds this gol over the pst fifteen yers include the reliztion of simple logic gtes with individully ssemled semiconductor nnowires nd cron nnotues,4 8, ut with only 6 devices or fewer nd single function for ech circuit. Recently, logic circuits lso hve een demonstrted tht use two or three elements of one-dimensionl memristor rry 9, lthough such pssive devices without gin re difficult to cscde. These circuits fll short of the requirements for sclle, multifunctionl nnoprocessor, owing to chllenges in mterils, ssemly nd rchitecture on the nnoscle. Here we descrie the design, friction nd use of progrmmle nd sclle logic tiles for nnoprocessors tht surmount these hurdles. The tiles were uilt from progrmmle, non-voltile nnowire trnsistor rrys. e/i core/shell nnowires 2 coupled to designed dielectric shells yielded single-nnowire, non-voltile field-effect trnsistors (FETs) with uniform, progrmmle threshold voltges nd the cpility to drive cscded elements. We developed n rchitecture to integrte the progrmmle nnowire FETs nd define logic tile consisting of two interconnected rrys with 496 functionl configurle FET nodes in n re of 96 mm 2. The logic tile ws progrmmed nd operted first s full dder with mximl voltge gin of ten nd input output voltge mtching. Then we showed tht the sme logic tile cn e reprogrmmed nd used to demonstrte full-sutrctor, multiplexer, demultiplexer nd clocked -ltch functions. These results represent significnt dvnce in the complexity nd functionlity of nnoelectronic circuits uilt from the ottom up with tiled rchitecture tht could e cscded to relize fully integrted nnoprocessors with computing, memory nd ddressing cpilities. The progrmmle nnowire FETs (NWFETs) incorported topgted geometry (Fig., left pnel) using e/i core/shell nnowires s the semiconductor chnnel ecuse previous work 2 hd shown tht this provided high yields of devices with uniform threshold voltges nd on-current chrcteristics. To relize progrmmle, non-voltile NWFETs, we implemented trilyer Al 2 O ZrO 2 Al 2 O dielectric structure (Fig., right-hnd pnels) for chrge trpping. For p-type e/i nnowire chnnel, negtive trpped chrges increse the hole density (Fig., top right) nd positive trpped chrges decrese the hole density (Fig., ottom right) in the chnnel. The modultion of crrier density y trpped chrges shifts the threshold of the NWFET in predictle nd non-voltile mnner. We grew the Al 2 O ZrO 2 Al 2 O dielectric structure y tomic-lyer deposition fter friction of metllic source nd drin nnowire contcts (Methods). A cross-sectionl trnsmission electron microscopy imge recorded from representtive device (Fig. ) shows tht our NWFET device consists of the designed structure with -nm-dimeter germnium nnowire core, 2-nm-thick concentric silicon shell nd conforml 2-nm Al 2 O,5-nmZrO 2 nd 5-nm Al 2 O lyers. The gte response of NWFET with trilyer dielectric ws chrcterized in device with six gte lines, 6 node element (Fig. c, inset). For these mesurements, we used one gte line s the ctive gte nd the other gte lines were grounded. The drin source current, I ds, recorded s function of drin source voltge, V ds, for different vlues of gte voltge, V gs (Fig. c), hs the ehviour expected of p-type depletion-mode FET 4. The conductnce V gs curves of the sme device with 66-V (Fig. d, lue) nd 69-V (Fig. d, red) sweeps in V gs show nticlockwise hysteresis loops tht gree well with the chrge-trpping mechnism 5. The hysteresis window increses y,2 V in the 66 to69-v V gs sweeps, which is consistent with more chrge eing trpped t lrger voltges nd the chrge-trpping model. ignificntly, these dt demonstrte tht two distinct sttes re oserved. After gte is of 26 V, the conductnce of the NWFET chnged y. s V gs vried etween nd 2 V; in contrst, fter c I ds (μa) Al 2 O ZrO V ds (V) d Conductnce () Cr Au e O ZrO 2 io 2 i V gs (V) Al 2 O Figure tructure nd chrcteriztion of the progrmmle NWFET., Left: schemtic of the top-gted NWFET;, nd correspond to source, drin nd gte, respectively. Right: representtive hole concentrtion in p-type e/i NWFET for two chrge-trpping sttes illustrting crrier ccumultion for negtive trpped chrge (top right) nd depletion for positive trpped chrge (ottom right) in the ZrO 2 lyer., Cross-sectionl trnsmission electron microscopy imge of representtive nnowire device, with sustrte surfce (io 2 ) nd gte (Cr Au) t the ottom nd the top of the imge, respectively. Other components of the nnowire nd dielectric lyers re lelled, nd dshed lines define the oundry etween different components. cle r, nm. c, I ds V ds curves recorded from six-gte NWFET with V gs 5 8 (lck), (red), (lue) nd 28 V (mgent) (), nd, 2, nd 4 6 grounded. Inset, scnning electron microscopy imge of the device. The smll lck rrow indictes. cle r, mm. d, emi-logrithmic plot of conductnce versus V gs for the sme device s in c, recorded for 66-V (lue) nd 69-V (red) sweeps t V ds 5.5 V; rrows represent sweep/hysteresis direction. eprtment of Chemistry nd Chemicl iology, Hrvrd University, Cmridge, Msschusetts 28, UA. 2 eprtment of Physics, Hrvrd University, Cmridge, Msschusetts 28, UA. chool of Engineering nd Applied ciences, Hrvrd University, Cmridge, Msschusetts 28, UA. 4 Nnosystems roup, The MITRE Corportion, McLen, Virgini 222, UA. *These uthors contriuted eqully to this work. 2 4 N AT U R E V O L 4 7 F E R U A RY 2 Mcmilln Pulishers Limited. All rights reserved 2

2 REEARCH gte is of 6 V, the conductnce chnge ws less thn 5% over the sme V gs rnge. We thus define the former stte s ctive, ecuse the NWFET ehves like n ctive trnsistor, nd define the ltter stte s inctive, ecuse the device ehves like pssive interconnection. Neither progrmmed stte shows degrdtion on the timescle of dy (upplementry Fig. ). The stle progrmmility of individul NWFETs etween the ctive nd inctive sttes llows distinct functionl circuits to e relized from rrys s descried elow. We initilly investigted the potentil of these multi-input progrmmle NWFETs for uilding integrted circuits with two coupled nnowire elements (Fig. 2, left pnel), where the first element, NW, hd four independently configurle input gtes, 4, nd the second element,, hd singleinput gte connectedtothe output(drin) of NW. In this demonstrtion, the first nd third gte nodes of NW nd thegtenode ofweresettothectivestte(fig. 2, greendots), nd theothergtenodesweresettotheinctivestte(methods). Withsource voltgesof2.5nd VppliedtoNWnd,respectively,input ws switched etween nd V while 2 4 were held t V (Fig. 2, 2 4 NW V out V I V in (V) V out (V) Figure 2 Coupled NWFET devices nd PNNTA rchitecture., Chrcteriztion of nnowire nnowire, coupled multigte device. Left: schemtic of the device. reen dots indicte the gte nodes tht were progrmmed s n ctive stte. Top right: input signls to 4. ottom right: output signls from NW (V I, lue) nd (V out, red)., esign of the unit logic tile for integrted nnoprocessors contining two PNNTAs, lock (upper left) nd lock 2 (lower right), comprising chrge-trpping nnowires (pink) nd metl gte electrodes (grey). The PNNTAs re connected to two sets of lod devices (red). Lithogrphic-scle electrodes (lue) re integrted for input nd output. Ech PNNTA provides progrmmle logic functionlity of up to pproximtely eight distinct logic gtes. More-complex logic functions cn e computed through the hierrchicl interconnection of unit logic tiles in liner rrys (upplementry Fig. 2). V I (V) top right). Notly, simultneous mesurements of the output voltge from NW, V I, nd, V out, with the - nd -V input vritions (Fig. 2, lower right), show tht V I is switched etween high (2.2-V) nd low (.2-V) levels nd tht V out is toggled etween low (.6-V) nd high (.-V) levels. imilr switching of the V I nd V out levels ws recorded when the input to the other ctive node,, ws vried nd, 2, 4 held t V. However, no switching of the V I nd V out levels ws oserved when the input voltge on either of the inctive input nodes, 2 nd 4, ws chnged from to V. These results show tht our progrmmle NWFET functions s trnsistor switch in its ctive stte nd tht multiple switches cn e coupled together y feeding the output of one FET into the input gte of nother, nd thus suggest tht ssemly of progrmmle NWFETs into suitle rchitecture could yield integrted circuits cple of processing. To exploit the unique properties of our progrmmle NWFETs, while simultneously recognizing ssemly limittions, we hve developed sclle system rchitecture in which oth the loctions nd the interconnections of trnsistors re decided fter friction. This rchitecture ws formulted with the concept of uilding extended nnoprocessor systems consisting of rrys of interconnected logic tiles,6 (upplementry Fig. 2). The unit logic tile (Fig. 2), refined oth y extensive simultion nd y experiment, consists of two progrmmle, non-voltile nnowire trnsistor rrys (PNNTAs). The tile is sized to e le to execute progrm equivlent to smll numer of logic gtes, nd functions s follows. Metl electrodes re used to gte nnowires in the lock- PNNTA (Fig. 2, upper left), nd the output of the nnowires is connected y metl electrodes to sttic lod devices. y progrmming selected nnowire gte nodes to the ctive trnsistor stte, NOR logic gtes 5 cn e mpped into lock. The outputs of this NOR logic circuit re pssed over nd used s gte inputs to the lock-2 PNNTA (Fig. 2, lower right) tht is lso progrmmed with NOR logic gtes. In this wy, the outputs of the logic circuits in lock cn e used to drive the circuit in lock 2, thus mking it possile to form two-level networks of logic gtes in the unit tile tht represent ritrry oolen functions. We relized the key rchitecturl tile y fricting PNNTAs s shown schemticlly in Fig. (Methods). riefly, prllel rry of e/i nnowires ws ssemled y sher-printing 5, source nd drin electrodes were defined y electron em lithogrphy (EL), tomiclyer deposition ws used to deposit the Al 2 O ZrO 2 Al 2 O chrgetrpping structure nd then second step of EL ws used to define input gte lines. In this wy, two locks of NWFETs were fricted, nmely lock (Fig., left) nd lock 2 (Fig., right), which correspond to the unit tile of our PNNTA rchitecture (Fig. 2). rk-field opticl microscopy nd scnning electron microscopy imges (upplementry Fig. ) revel totl of 496 progrmmle NWFET devices lid out in two seprte rrys with totl re of,96 mm 2, where ech device node consists of single nnowire crossed y gte line. The verge re per node,,.9 mm 2, is reltively lrge in these proofof-concept studies ut does not represent lower limit, s previous studies demonstrting close-pcked nnowire ssemly 7 nd the scling of chrge-trpping devices 8 indicte tht n re -fold smller,,.7 mm 2, is chievle. To relize functionl logic with the PNNTA tile requires uniform device chrcteristics mong individul nnowire elements. pecificlly, the devition of the threshold voltge, V th, in oth the ctive nd the inctive stte must e smller thn the difference in V th etween the two sttes. We chrcterized the V th vlues of 7 NWFET nodes from lock of the fricted PNNTA structure in oth the ctive nd the inctive stte (Fig. ). Notly, we found tht 6 of 7 nodes (86%) in the ctive stte hd V th vlues #2 V nd tht 6 of 7 nodes (87%) in the inctive stte hd V th vlues $.5 V (Fig. ). The high yield of NWFET devices reflects the uniformity of the e/i nnowire uilding lock 2,nd controlled ssemly 5 llows ny defective elements to e excluded redily from the functionl circuit. For the demonstrtion of logic FERUARY 2 VOL 47 NATURE 24 2 Mcmilln Pulishers Limited. All rights reserved

3 REEARCH LETTER Count c e (V) Input gtes A /A /C /C NW NW V th (V) d V /A, V /, V /C (V) 2 (A,, C) (,, ) (,, ) (,, ) (,, ) (,, ) (,, ) (,, ) Input stte, (A,, C) Figure Friction, structure nd logic function of PNNTA tile., chemtic of key components of the two-lock PNNTA tile, including ssemled nd ptterned e/i nnowires (cyn) with source nd drin electrodes (lue), nd chrge-trpping trilyer gte dielectric (purple) nd metl gte lines (grey). The fricted structure consists of two locks of NWFETs, lock (left) nd lock 2 (right)., istriution of V th from 7 NWFET nodes in lock in the PNNTA tile. The lue nd red rs represent the V th vlues of devices in inctive nd ctive sttes, respectively, with C out Cout (V) (V) 2 f (A,, C) (,, ) 2 V A, V, V C (V) A C in ( V) (2.5 V) (2.4 V) (. V) (.V) (2. V) C out ( V) (.6 V) (.6 V) (2. V) (2.5 V) (2.7 V) V ds 5.5 V. c, Circuit design implementing one-it full dder. /A,/ nd /C denote the complementry inputs of A, nd C, respectively. The left- nd right-hnd dshed oxes outline lock nd lock 2, respectively. d, Voltge trnsfer function for (red) nd C out (lue) from input sttes (,, ) to (,, ). The dshed tngent lines show the mximl voltge gins of the outputs. e, Output voltge levels for nd C out for six typicl input sttes. f, Truth tle of full-dder logic for the six input sttes in e. The mesured output voltges re shown in rckets. 2 Cout (V) circuits, we selected devices with verge V th vlues of. 6.4 nd V for ctive nd inctive sttes, respectively (upplementry Fig. 4). imilrly, the chosen NWFET nodes in lock 2 hd V th vlues of nd V for ctive nd inctive sttes, respectively. The distinction etween V th vlues for oth sttes in oth locks of the PNNTAtileprovidereltivelywide,,2-V, windowforcircuitopertion. The two-lock PNNTA tile ws initilly progrmmed to function s full dder, n importnt comintionl circuit in the rithmetic logic unit in modern digitl computers. Figure c illustrtes the configurtion of the one-it full-dder logic circuit comprising two locks with the output of lock (Fig. c, left-hnd ox) fed into lock 2 (Fig. c, right-hnd ox) s input through externl wiring. The progrmmed ctive node pttern (Fig. c, green dots) determines the circuit function, nd in this cse the outputs nd C out represent the sum nd crry-out of the summtion of inputs A C, respectively, with ~A++C nd C out ~A : za : Cz : C. The symols +, : nd represent logicl XOR, AN nd OR, respectively. Typicl voltge trnsfer functions of the resulting circuit for power-supply voltge,, of. V (Fig. d) show tht s the input levels of A, nd C re swept from logic stte ( V) to logic stte (.5 V), the outputs nd C out switch from logic (oth V) to logic (2. nd 2.7 V, respectively). From this dt, the pek voltge gins of C out nd (Fig. d, lines tngentil to dt) re found to e nd 4, respectively. The lrger-thn-unity gin nd the mtching of input output voltge levels re crucil for potentilly cscding the logic tiles (upplementry Fig. 2). Further tests showed tht the output of nd C out for six typicl input comintions (Fig. e) ll hd similr output rnges:.6 V for logic stte nd V for logic stte. The expected nd experimentl results for full dder re summrized in truth tle (Fig. f), which shows good consistency for this fundmentl logic unit. The V th vlue of some ctive NWFET nodes shifted with the -V source is nd precluded switching ehviour for the (A,, C) 5 (,, ) nd (,, ) inputs for consistent input voltge rnge (.5 V). We note tht optimiztion of logic opertions cn e chieved y tuning nd the lod resistnce, together with djustment of V th through the choice of top-gte metl 2. Nonetheless, the lrge voltge gin nd mtching of input output voltge levels descried here show the potentil to integrte the prototype device into lrge-scle integrted circuits such s multi-it dder in cscde configurtion. Notly, the sme PNNTA tile cn e used to perform rnge of distinct logic opertions ecuse we cn reproducily nd independently reprogrm the ctive nd inctive nodes in oth locks (Methods nd upplementry Fig. 5). To illustrte this key point, we first reprogrmmed the sme tile shown in Fig. to function s full sutrctor (Fig. 4). The two outputs of the reprogrmmed circuit, nd out, 242 NATURE VOL 47 FERUARY 2 Mcmilln Pulishers Limited. All rights reserved 2

4 REEARCH c.. Input gtes X /X Y /Y / NW NW out (V) (,, ) (,, ) (,, )(,, ) (,, ) (,, ) (,, )(,, ) Input stte, (X, Y, ) out (V) X Y ( V) (.59 V) (.68 V) ( V) (.7 V) ( V) ( V) (.6 V) out (.9 V) (.72 V) (.4 V) (.76 V) (.2 V) (.2 V) (.2 V) (.74 V) d e 4. f /E. 2 4 Q 2.. E E E E E E E. E (V) E (V) E E E E E E Input gtes E /E NW NW Q (V) (V) Q (V). Q (V). Figure 4 Multifunctionl PNNTA rchitecture., chemtic of circuit implementing full sutrctor., Output of (red) nd out (lue) of the full sutrctor implemented with the sme PNNTA structure shown in Fig. with eight input sttes. c, Truth tle of the full sutrctor with mesured output voltges shown in rckets. d, chemtics of logic (upper) nd circuit design (lower) of ltch implemented with the sme PNNTA tile used in c. e, f, Output, Q, wveforms (green) t two sets of clock (E, red) nd dt (, lue) inputs. represent the difference nd orrow, respectively, of the sutrction of inputs X 2 Y 2, with~x+y+ nd out ~ : (X+Y)zX : Y, where X represents the logicl negtion of X (tht is, the complementry input). Mesurements of nd out for different X 2 Y 2 input comintions (Fig. 4) show tht the output voltge levels for logic stte (. V) nd logic stte (.4.8 V) re well seprted nd represent roust sttes. Moreover, the truth tle summrizing the expected nd experimentl results for the full sutrctor (Fig. 4c) shows full nd correct logic for this processing unit. In ddition, we used the sme tile to progrm nd demonstrte multiplexer nd demultiplexer circuits (upplementry Fig. 6), showing the cpility nd flexiility of the PNNTA to fulfil the core functions of comintionl circuit elements. ignificntly, we cn lso use our nnowire tile s sequentil circuit element, which represents nother criticl component eyond the scope of comintionl elements. To do so, we mpped ltch 9, sequentil logic circuit cple of informtion storge, onto the unit tile (Fig. 4d). The -ltch circuit (Fig. 4d, upper pnel) is composed of four NOR gtes with positive-feedck connection etween the output, Q, nd inputs to NOR gtes 2 nd (Fig. 4d, upper pnel). As consequence, Q equls input dt,, when clock, E, is in logic stte ut retins its previous vlue when E is switched into logic stte. We implemented the NOR gtes in the tile using NW NW in lock nd in lock 2 (Fig. 4d, lower pnel), nd formed the positive feedck y connecting the output to n input gte in lock. An importnt constrint on relizing the -ltch logic is tht there must e successful feedck loop (output Q of lock 2 ck to lock ; Fig. 4d), which requires mtching of input nd output voltge levels. Mesurement of Q s function of repetitive E nd pulses (Fig. 4e) shows tht Q follows when E is switched to logic (.6 V) t time points 6 nd s ut retins its previous vlue when E is switched to logic ( V) t 7, 24 nd 4 s, s expected for ltch. The roustness of this sequentil logic circuit ws tested further y inputting more complex dt wveform (Fig. 4f), where mesurements of Q demonstrted shrp logic opertion y following with high fidelity in the time intervls 6 24 nd 4 s. Moreover, the voltge rnge of output, Q ( 2.2 V), closely mtches tht of input dt,, nd clock, E. Our nnowire logic tile hs novel fetures in comprison with previous circuits sed on ottom-up nnoscle elements,2,4 9.First,the rchitecture enles us to enhnce y fctor of t lest three the complexity of nnoelectronic circuits ssemled from the ottom up (56 devices of two-lock, coupled logic rther thn #6 uncoupled devices in single lock in previous work 4 6 ), nd correspondingly hs led to circuits exceeding simple logic relized using nnowires 4 6,cron nnotues 7,8 nd memristors 9. econd, our circuits show mximl voltge gin of ten, which is comprle to previous reports on simple nnowire nd cron nnotue logic devices 4 8 nd represents significnt dvntge over pssive memristor devices 9, where gin is #. in is crucil for signl restortion, nd mkes the PNNTA rchitecture suitle for lrger-scle processors. Third, the reversile progrmming of individul NWFET nodes in the tile provides gret verstility, s shown y the comintionl nd sequentil circuit elements reported ove. Reconfigurle logic hs een relized using memristor complementry metl oxide semiconductor (CMO) hyrid circuits 2, where the microscle CMO lyer is responsile for logic opertion nd memristors re responsile for reconfigurle signl routing. Our FERUARY 2 VOL 47 NATURE 24 2 Mcmilln Pulishers Limited. All rights reserved

5 REEARCH LETTER rchitecture, however, represents the first exmple of system integrting nnoscle devices tht comine oth logic nd progrmmility functions. These ottom-up nnowire circuits lso hve limittions in comprison with conventionl CMO circuits, lthough projections suggest tht the density, speed nd power consumption cn e further improved for our rry rchitecture (upplementry Informtion). In summry, we hve demonstrted progrmmle nd sclle rchitecture sed on unit logic tile consisting of two interconnected, progrmmle, non-voltile nnowire trnsistor rrys. Ech NWFET node in n rry cn e progrmmed to ct s n ctive or n inctive trnsistor stte, nd y mpping different ctive-node ptterns into the rry, comintionl nd sequentil logic functions including full dder, full sutrctor, multiplexer, demultiplexer nd -ltch cn e relized with the sme progrmmle tile. Cscding this unit logic tile into liner or tree-like interconnected rrys, which will e possile given the demonstrted gin nd mtched input output voltge levels of NWFET devices, provides promising ottom-up strtegy for developing incresingly complex nnoprocessors with heterogeneous uilding locks 2,2. In the ner term, prticulrly promising for this rchitecture nd the low-power devices it contins re simpler, tiny, ppliction-specific nnoelectronic control processors ;such nnocontrollers might mke possile very smll emedded electronic systems nd new types of therpeutic device. METHO UMMARY We synthesized the e/i core/shell nnowires using nnocluster-ctlysed methodology descried previouly 2. rowth of the chrge-trpping gte dielectric shells y tomic-lyer deposition ws crried out in vcuum system (vnnh-, Cmridge NnoTech) t 2 uc, using trimethylluminium, tetrkis (dimethylmino)zirconium nd wter s precursors. The three lyers were deposited without interruptions in etween. tndrd EL nd therml evportion were used to form metl electrodes (Ni for source nd drin nd Cr Au for top gte). We used the focused ion em technique to prepre cross-sectionl smple of the NWFET device, nd used luricnt-ssisted contct printing to prepre xilly ligned e/i nnowire rrys. EL nd inductively coupled plsm rective ion etching were used to pttern the nnowires. Electricl mesurements were mde with computercontrolled, nlogue input output system (Ntionl Instruments). A customdesigned 96-pin proe crd (Accuproe) ws used to ccess devices in the PNNTA rry electriclly. Received 6 August; ccepted 6 ecemer 2.. Lu, W. & Lieer, C. M. Nnoelectronics from the ottom up. Nture Mter. 6, (27). 2. Lu, W., Xie, P. & Lieer, C. M. Nnowire trnsistor performnce limits nd pplictions. IEEE Trns. Electron. ev. 55, (28).. s,. et l. esigns for ultr-tiny, specil-purpose nnoelectronic circuits. IEEE Trns. Circuits yst. Regul. Pp. 54, (27). 4. Cui, Y. & Lieer, C. M. Functionl nnoscle electronic devices ssemled using silicon nnowire uilding locks. cience 29, (2). 5. Hung, Y. et l. Logic gtes nd computtion from ssemled nnowire uilding locks. cience 294, 7 (2). 6. Zhong, Z. H., Wng,. L., Cui, Y., ockrth, M. W. & Lieer, C. M. Nnowire crossr rrys s ddress decoders for integrted nnosystems. cience 2, (2). 7. chtold, A., Hdley, P., Nknishi, T. & ekker, C. Logic circuits with cron nnotue trnsistors. cience 294, 7 2 (2). 8. Jvey, A. et l. High-k dielectrics for dvnced cron-nnotue trnsistors nd logic gtes. Nture Mter., (22). 9. orghetti, J. et l. Memristive switches enle stteful logic opertions vi mteril impliction. Nture 464, (2).. ehon, A. Arry-sed rchitecture for FET-sed, nnoscle electronics. IEEE Trns. Nnotechnol. 2, 2 2 (2).. s,., Rose,.., Ziegler, M. M., Piccontto, C. A. & Ellenogen, J. C. Architectures nd simultions for nnoprocessor systems integrted on the moleculr scle. Lect. Notes Phys. 68, (25). 2. Xing, J. et l. e/i nnowire heterostructures s high-performnce field-effect trnsistors. Nture 44, (26).. Liu, J., Wng, Q., Long,.., Zhng, M. H. & Liu, M. A metl/al 2 O /ZrO 2 /io 2 /i (MAZO) structure for high-performnce non-voltile memory ppliction. emicond. ci. Technol. 25, 55 (2). 4. ze,. M. Physics of emiconductor evices (Wiley, 98). 5. Jvey, A., Nm,., Friedmn, R.., Yn, H. & Lieer, C. M. Lyer-y-lyer ssemlyof nnowires for three-dimensionl, multifunctionl electronics. Nno Lett. 7, (27). 6. nider,., Kuekes, P. & Willims, R.. CMO-like logic in defective, nnoscle crossrs. Nnotechnology 5, (24). 7. Whng,., Jin,., Wu, Y. & Lieer, C. M. Lrge-scle hierrchicl orgniztion of nnowire rrys for integrted nnosystems. Nno Lett., (2). 8. kmoto, W. et l. in Proc. Electronic evices Meeting 29, doi:.9/ IEM (IEEE, 29). 9. edr, A.. & mith, K. C. Microelectronics Circuits 4 2 (OxfordUniv. Press, 24). 2. Xi, Q. F. et l. Memristor-CMO hyrid integrted circuits for reconfigurle logic. Nno Lett. 9, (29). 2. Nm,., Jing, X. C., Xiong, Q. H., Hm,. & Lieer, C. M. Verticlly integrted, threedimensionl nnowire complementry metl-oxide-semiconductor circuits. Proc. Ntl Acd. ci. UA 6, (29). upplementry Informtion is linked to the online version of the pper t Acknowledgements We thnk. ell nd N. Antoniou for trnsmission electron microscopy smple preprtion nd imging, Q. Qing for ssistnce with electricl mesurements nd J. L. Hung, X. un nd X. Jing for helpful discussions. C.M.L. cknowledges support from Ntionl ecurity cience nd Engineering Fculty Fellow wrd nd contrct from the MITRE Corportion..., J.F.K. nd J.C.E. cknowledge support y the U government s Nno-Enled Technology Inititive nd the MITRE Innovtion Progrm. Author Contriutions C.M.L., J.C.E.,.., H.Y., H..C. nd.n. designed theexperiments. H.Y., H..C.,.N., Y.H. nd J.F.K. performed the experiments... performed simultions. H.Y., H..C.,.N.,.., J.F.K., J.C.E. nd C.M.L. nlysed the dt nd wrote the pper. All uthors discussed the results nd commented on the mnuscript. Author Informtion Reprints nd permissions informtion is ville t The uthors declre no competing finncil interests. Reders re welcome to comment on the online version of this rticle t Correspondence nd requests for mterils should e ddressed to.. (sds@mitre.org) or C.M.L. (cml@cmliris.hrvrd.edu). 244 NATURE VOL 47 FERUARY 2 Mcmilln Pulishers Limited. All rights reserved 2