FD-SOI Technology. Bich-Yen Nguyen Soitec

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1 FD-SOI Technology Bich-Yen Nguyen Soitec

2 Agenda 1 FD-SOI technology overview 2 Markets, foundries offers & ecosystems 3 FD-SOI material & roadmap 4 Summary 10/10/ SOITEC Confidential FD-SOI technology

Challenge of Traditional Planar Bulk Transistor

Impact Yield Limit Vdd scaling new transistor

3 Challenge of Traditional Planar Bulk Transistor Scaling Increased standby power dissipation Source: IBM, T.C. Chen, ISSCC 2006 Amplified V th variability Impact Yield Limit Vdd scaling new transistor architectures and materials are needed 10/10/ SOITEC Confidential FD-SOI technology

Continue Moore Law with New Materials & Device

Introduction of New Device Architecture Fully

4 Continue Moore Law with New Materials & Device Architectures nm 45 nm 22nm Hartmann, GSA12 65nm 32nm Strained Silicon Introduction of New Materials High-K / Metal Gate Introduction of New Device Architecture Fully Depleted Devices 10/10/ SOITEC Confidential FD-SOI technology

Leakage Power is still a Major Issue Despite the Use of Hi-K Dielectric High-K/Metal Gate Stack Source: IBS SiON/Poly Gate Stack Technology node Leakage power is still

5 Leakage Power is still a Major Issue Despite the Use of Hi-K Dielectric High-K/Metal Gate Stack Source: IBS SiON/Poly Gate Stack Technology node Leakage power is still tremendously growing after insertion of the High- K/MG gate stack at 28nm node as demands for more performance and functionality 10/10/ SOITEC Confidential FD-SOI technology

6 New Device Architecture: Planar FDSOI or Multi-Gate Transistor S G D Minimum Design Disruption S G D Buried OX Max scalability S G D Bulk Si Conventional Planar Bulk Transistor Bulk Si Planar Single-or double Gate FDSOI FDSOI : Fully Depleted Silicon-on Insulator Buried oxide Multiple-Gate, FinFET or Nanowire Transistor Thin channel (Fully Depleted) with multi gates for better gate or short channel (SCE) control Better gate control better transistors scaling 10/10/ SOITEC Confidential FD-SOI technology

7 FD-SOI Transistor Advantages UTBB FDSOI Transistor Advantages Courtesy of STM Body Biasing Knobs to control Perf/Power: Gate bias Back Bias Total dielectric isolation Ultra thin Body No channel doping Ultra thin BOX option Channel mobility boost Conventional planar processing Lower S/D capacitances Lower S/D leakage Latch-up immunity Excellent SCE (SS, DIBL) No History Effect Lower SER Improved V T variability Improved mismatch (SRAM & analog) Better analog gain Reduced process cost Enables Extended body biasing Scalable down to 10nm Lower manufacturing risk Equivalent bulk design UTBB: Ultra-Thin Body and BOX 10/10/ SOITEC Confidential FD-SOI technology

8 FDSOI Device Physics FDSOI Coxf Csi Coxb Vg F s1 F s2 Body factor: n = 1.05 in FDSOI; 1.5 in Bulk G Bulk/PDSOI Vg G S D Cox S Oxide F Silicon Cdepl s D Linear current: Saturation current: Sub-threshold slope: W I D = µ C ox L I Dsat = 1 2n µ C ox S = n kt q ln(10 ) ( ) V D 1 2 n V D 2 V G V TH W L ( V G V TH ) 2 ) Gain (strong inversion): g m I D V A = 2 µ C ox W L n I D V A 10/10/ SOITEC Confidential FD-SOI technology

9 FD-SOI Transistor Advantages UTBB FDSOI Transistor Advantages Courtesy of STM Body Biasing Knobs to control Perf/Power: Gate bias Back Bias Total dielectric isolation Ultra thin Body No channel doping Ultra thin BOX option Channel mobility boost Conventional planar processing Lower S/D capacitances Lower S/D leakage Latch-up immunity Excellent SCE (SS, DIBL) No History Effect Lower SER Improved V T variability Improved mismatch (SRAM & analog) Better analog gain Reduced process cost Enables Extended body biasing Scalable down to 10nm Lower manufacturing risk Equivalent bulk design UTBB: Ultra-Thin Body and BOX 10/10/ SOITEC Confidential FD-SOI technology

FD-SOI Transistor Level Benefits BULK Gate Thin and excellent uniformity SOI defined channel FD-SOI Gate Source Drain Source Top Si BOX Drain Bulk wafer 2 nd gate through ultra thin BOX FD-SOI base

Large junction capacitance (Cj), GIDL and Didode leakage Limited well bias capability Vertical transistor layout determined by FD-SOI engineered substrate and undoped channel Significant improved Vt

10 FD-SOI Transistor Level Benefits BULK Gate Thin and excellent uniformity SOI defined channel FD-SOI Gate Source Drain Source Top Si BOX Drain Bulk wafer 2 nd gate through ultra thin BOX FD-SOI base wafer Vth and SCE defined by complex and heavily channel and halo doping techniques Large Vt mismatch due to random dopant fluctuation => limit Vdd scaling Strong sensitivity to short channel effect Large junction capacitance (Cj), GIDL and Didode leakage Limited well bias capability Vertical transistor layout determined by FD-SOI engineered substrate and undoped channel Significant improved Vt mismatch due to minimize random dopant fluctuation => enable Vd scaling down to 0.4V or lower Excellent SCE Minimum Cj, GIDL & diode leakages Extensive back bias capability 10/10/ SOITEC Confidential FD-SOI technology

FD-SOI superior SER enables high reliability required applications Attractive SEU resistance due to very low

Alles Vanderbilt University, S3S conference, 2015 Neutron-SER in FT/Mb ST Vendor A ST 65nm 45nm 45nm Bulk

bulk Vendor A 28nm Bulk ST 28nm Bulk 28nm FD-SOI ST 28nm FD-SOI Mobileye using STM FD-SOI 28nm technology for

11 FD-SOI superior SER enables high reliability required applications Attractive SEU resistance due to very low charge collection volumes in FD-SOI Michael L. Alles Vanderbilt University, S3S conference, 2015 Neutron-SER in FT/Mb ST Vendor A ST 65nm 45nm 45nm Bulk Bulk Bulk FD-SOI = 20x SER improvement vs. bulk Vendor A 28nm Bulk ST 28nm Bulk 28nm FD-SOI ST 28nm FD-SOI Mobileye using STM FD-SOI 28nm technology for their 4th gen chipset CPU#1 CPU#2 CPU#1 CPU#2 CPU#1 CPU#2 Memory Memory Memory ST, P. Magarshack, Shanghai FDSOI forum, /10/ SOITEC Confidential FD-SOI technology Source: Automotive Product Group (APG) presentation,, Marco Monti

12 FD-SOI Transistor Advantages UTBB FDSOI Transistor Advantages Courtesy of STM Body Biasing Knobs to control Perf/Power: Gate bias Back Bias Total dielectric isolation Ultra thin Body No channel doping Ultra thin BOX option Channel mobility boost Conventional planar processing Lower S/D capacitances Lower S/D leakage Latch-up immunity Excellent SCE (SS, DIBL) No History Effect Lower SER Improved V T variability Improved mismatch (SRAM & analog) Better analog gain Reduced process cost Enables Extended body biasing Scalable down to 10nm Lower manufacturing risk Equivalent bulk design UTBB: Ultra-Thin Body and BOX 10/10/ SOITEC Confidential FD-SOI technology

13 FDSOI Structure by IBM- VLSI 2009 Insitu doped SiGe S/D: Lower S/D resistance Reduces parasitic capacitance B - SiGe Lg= 25nm Tsi= 6nm Tinv=1.6nm Ioff= 3nmA/um Ion-N=570um/um Ion-P=550uA/um Vdd=0.9v 13 BY Nguyen, Soitec Apr. 22, 2011

14 IBM: 28LP Bulk vs. FDSOI 20LP Parameter 28LP Bulk IBM et al. (*) ETSOI IBM et al. (**) Lg 30nm 22nm VDD 1V 1V nfet pfet nfet pfet Ioff=300pA/um Ioff = 1nA/um 660µA/µm 380µA/µm 760µA/µm 590µA/µm 740µA/µm 420µA/µm 920µA/µm 880µA/µm DIBL 120mV/V 130mV/V 85 mv/v 90 mv/v AVt 2mV.µm 1.25mV.µm VDD 1.1V Ioff=1nA/um, 920µA/um 525nA/µm 1100µA/µm 1050µA/µm (*): IBM Alliance 28LP technology as reported at IEDM 09, F Arnaud et al. (**): ETSOI technology for 22/20LP from IBM Research, as reported at FDSOI workshop dec /10/ SOITEC Confidential FD-SOI technology

15 FD-SOI Transistor Advantages UTBB FDSOI Transistor Advantages Total dielectric isolation Lower S/D capacitances Lower S/D leakage Latch-up immunity Ultra thin Body Excellent SCE (SS, DIBL) No History Effect Lower SER improvement No channel doping Improved V T variability Improved mismatch (SRAM & analog) Better analog gain Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option Enables Extended body biasing Knobs to control Perf/Power: Gate bias Back Bias Channel mobility boost Conventional planar processing Scalable down to 10nm Lower manufacturing risk Equivalent bulk design UTBB: Ultra-Thin Body and BOX 10/10/ SOITEC Confidential FD-SOI technology

SOI value: part of device integrated by substrate engineering Optimized SOI wafers provide excellent silicon geometry control To make the best of FD technology Soitec FD-2D wafer Ultra-Thin Top

16 SOI value: part of device integrated by substrate engineering Optimized SOI wafers provide excellent silicon geometry control To make the best of FD technology Soitec FD-2D wafer Ultra-Thin Top Silicon Layer FD-SOI transistor S G D Ultra-Thin Buried Oxide Base Silicon Critical dimension: Top Si thickness Enables: Critical dimension: channel thickness 10/10/ SOITEC Confidential FD-SOI technology

17 FDSOI Uniformity: Lowest VT variability A vt (mv.µm) ±2.6A, 2mm EE- 721 pts F5X inspection Gate Length (nm) Cheng et. Al. IBM IEDM 2009 Record and reproducible low A VT of Lg=25nm (32/28nm GR) B.Doris et al., FD Workshop at SFO, /10/ SOITEC Confidential FD-SOI technology

18 Planar Bulk vs FDSOI Vt Variation 0.03 V t V ariation Retrograde Bulk sigma Vt (V) FDSOI L g (n m ) S O I Retro B ulk Uniform B ulk FDSOI shows best results in variation (throughout gate length) Source: UCB/Soitec, SOI 2009 Conference 50-60% Vt variation improvement by using undoped channel retains with technology scaling 10/10/ SOITEC Confidential FD-SOI technology

19 Single Port 4Mb SRAM: No Back Bias Improved memory minimum voltage 28nm LP Bulk vs 28nm FDSOI from STMicroelectronics (gate-first HKMG Technology) 10/10/ SOITEC Confidential FD-SOI technology

20 10/10/ SOITEC Confidential FD-SOI technology C2 - Confidential

FDSOI for RF & Analog Beyond 28nm Bulk FDSOI key

vs Bulk Lower variability than bulk Lower

noise Remaining planar On the fly Vt tuning New

transceivers and SoC Vgs Gain @ Lmin Gain @ Id

21 FDSOI for RF & Analog Beyond 28nm Bulk FDSOI key analog differentiations Higher Analog Performance vs Bulk Lower variability than bulk Lower Capacitance enabling higher frequency Lower Phase noise Remaining planar On the fly Vt tuning New circuit topology enabler : double gate transistor Analog : VT, Fmax, Gm, Ioff,. FDSOI Bulk CMOS Ideal for next generations transceivers and SoC Vgs Lmin Id Variability (Undoped Channel) Fmax > 300Ghz 10/10/ SOITEC Confidential FD-SOI technology

22 FD-SOI Transistor Advantages UTBB FDSOI Transistor Advantages Courtesy of STM Body Biasing Knobs to control Perf/Power: Gate bias Back Bias Total dielectric isolation Ultra thin Body No channel doping Ultra thin BOX option Channel mobility boost Conventional planar processing Lower S/D capacitances Lower S/D leakage Latch-up immunity Excellent SCE (SS, DIBL) No History Effect Lower SER Improved V T variability Improved mismatch (SRAM & analog) Better analog gain Reduced process cost Enables Extended body biasing Scalable down to 10nm Lower manufacturing risk Equivalent bulk design UTBB: Ultra-Thin Body and BOX 10/10/ SOITEC Confidential FD-SOI technology

23 Electrostatic Scaling Rule of FDSOI down to Lg~10nm 5nm Electrostatic control improved by thinning T box and T Si Superior short-channel control maintained with scaling Scalability possible down to Lg~10nm, thanks to UTBB FDSOI 10/10/ SOITEC Confidential FD-SOI technology

Threshold voltage (V) Multi-VT Solution for FD-SOI with Dual Metal Gate/Ground Plane 0,8 0,6 0,4 0,2 0-0,2-0,4-0,6 LVT RVT HVT SHVT nmos GP-N GP-P pmos Logic GP change GP-P GP-N SRAM metal change

24 Threshold voltage (V) Multi-VT Solution for FD-SOI with Dual Metal Gate/Ground Plane 0,8 0,6 0,4 0,2 0-0,2-0,4-0,6 LVT RVT HVT SHVT nmos GP-N GP-P pmos Logic GP change GP-P GP-N SRAM metal change GP-N GP-P GP-P GP-N nmos TiN BOX N-GP nmos TiN BOX P-GP LVT RVT pmos TaAlN BOX P-GP pmos TaAlN BOX N-GP GP change Metal change nmos TaAlN BOX N-GP nmos TaAlN BOX P-GP HVT SHVT pmos TiN BOX P-GP pmos TiN BOX N-GP -0,8 TiN TaAlN/TaN O. Weber et al., IEDM 10 Multi Vt requirement for SoC can be achieved for FDSOI device using dual WF metal-gate and ground-plane approach without back-bias 10/10/ SOITEC Confidential FD-SOI technology

VT modulation of 200mV for 10nm BOX No degradation of Ion-Ioff

25 Multi-VT Modulation for FDSOI with Back Bias Leti- VLSI 2010 Q. Liu, ST, VLSI 2010 VT tuning with BOX = 10nm and VBB, GP N and PMOS: VT modulation of 200mV for 10nm BOX No degradation of Ion-Ioff trade-off with back-bias up to +/-2V 10/10/ SOITEC Confidential FD-SOI technology

26 Body-Bias enabling wider dynamic operating range NXP example (BB level 0) Source: NXP presentation at SOI Consortium, Santa Clara, April /10/ SOITEC Confidential FD-SOI technology

FD-SOI with Back Bias enables 0.4v Operation for IoT FDSOI 0.

IEDM 2007 SRAM remains functional down to V DD =0.

27 FD-SOI with Back Bias enables 0.4v Operation for IoT FDSOI 0.08um2 SRAM (80nm CPP) V BB 10/10/ SOITEC Confidential FD-SOI technology Q. Liu, et. al. VLSI Symposium 2011 R. Tsuchiya, et. al. IEDM 2007 SRAM remains functional down to V DD =0.4V Clear SNM modulation from back bias Both Stability and Vt variation improved with RBB Lower Vdd for logic operation with software controlled Back-bias enables SoC Product with tremendous power saving (>70%)

28 22nm FDX Platform Features: ULL, ULP & RF Source : R. Carter, GlobalFoundries, IEDM /10/ SOITEC Confidential FD-SOI technology

29 22nm FDX Platform Features: ULL, ULP & RF 10/10/ SOITEC Confidential FD-SOI technology

30 10/10/2017 SOITEC Confidential FD-SOI technology C2 - Confidential 30

31 FD-SOI Transistor Advantages UTBB FDOI Transistor Advantages Total dielectric isolation Lower S/D capacitances Lower S/D leakage Latch-up immunity Ultra thin Body Excellent SCE (SS, DIBL) No History Effect Lower SER No channel doping Improved V T variability Improved mismatch (SRAM & analog) Better analog gain Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option Enables Extended body biasing Knobs to control Perf/Power: Gate bias Back Bias Channel mobility boost Conventional planar processing Scalable down to 10nm Lower manufacturing risk Equivalent bulk design UTBB: Ultra-Thin Body and BOX 10/10/ SOITEC Confidential FD-SOI technology

32 FDSOI Scalability: Boosters Roadmap 28nm FDSOI 22/14nm FDSOI 12/10nm FDSOI 2nd gen RSD + csige 10/10/ SOITEC Confidential FD-SOI technology

33 FDSOI Performance Booster: local Ge Condensation for PMOS 10/10/ SOITEC Confidential FD-SOI technology

Strain SiGeOI by Ge Condensation of SOI Source: S.

condensation with various Ge content/strain level has been used

34 Strain SiGeOI by Ge Condensation of SOI Source: S. Nakaharai, Appl. Phys. Lett. 83, 3516 (2003); S. Nakaharai et al, MIRAI, APL, V83, no17, 2003 I Ion= WC v DSAT ox sat µ ( V V ) eff G T µ + 2 v L/( V V ) eff sat G T Local Ge condensation with various Ge content/strain level has been used to boost hole mobility or P-type MOSFET performance 10/10/ SOITEC Confidential FD-SOI technology

al, IEDM-2012 35% NMOS does not degrade with local Ge condensation

35 Performance of PMOS using csige channel formed by Local Ge Condensation Source: IBM, Cheng et. al, IEDM % NMOS does not degrade with local Ge condensation process Compressive SiGechannel PMOS improved by 35% over unstrained Si FDSOI 10/10/ SOITEC Confidential FD-SOI technology

ARM says 22nm FD-SOI with proper BB optimization outperforms FinFET at pure performance standpoint Selective back-gate biasing is developed by ARM Total Power 14FinFET 22FD-SOI Using proper BB on

36 ARM says 22nm FD-SOI with proper BB optimization outperforms FinFET at pure performance standpoint Selective back-gate biasing is developed by ARM Total Power 14FinFET 22FD-SOI Using proper BB on 22nm FD-SOI can achieve higher performance/power tradeoff as those of 14 FinFET technology for ARM HP CPU (Cortex- A72) Performance Source : ARM, SOI Consortium San Jose /10/ SOITEC Confidential FD-SOI technology

37 FDSOI Performance Booster: Tension Strain Si Channel for NMOS 10/10/ SOITEC Confidential FD-SOI technology

38 Strained Si on Insulator (ssoi) for boosting NMOS Performance 75% 27% 10/10/ SOITEC Confidential FD-SOI technology Source: IBM, Khakifirooz et. al, VLSI- 2012

39 10nm FD-SOI and DC Performance Comparison 10/10/ SOITEC Confidential FD-SOI technology Source: Q. Liu et. al, IEDM 2014

FD-SOI Transistor Advantages UTBB FDOI Transistor Advantages Total dielectric isolation Lower S/D capacitances Lower S/D leakage Latch-up immunity Ultra thin Body Excellent SCE (SS, DIBL) No History

40 FD-SOI Transistor Advantages UTBB FDOI Transistor Advantages Total dielectric isolation Lower S/D capacitances Lower S/D leakage Latch-up immunity Ultra thin Body Excellent SCE (SS, DIBL) No History Effect Lower SER No channel doping Improved V T variability Improved mismatch (SRAM & analog) Better analog gain Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option Enables Extended body biasing Knobs to control Perf/Power: Gate bias Back Bias Channel mobility boost Conventional planar processing Scalable down to 10nm Lower manufacturing risk Equivalent bulk design UTBB: Ultra-Thin Body and BOX 10/10/ SOITEC Confidential FD-SOI technology

41 Simplicity of the FDSOI Integration Shallow Trench isolation Si BOX Si substrate Gate Process SEG of SD region Spacer and NiSi for SD contact 1- Isolation: Shallow Trench Isolation Define the bulk/soi area (hybrid option) Ground plane implant 2- Gate Stack: Sac Ox and High-K deposition Metal gate & poly Si deposition Gate stack patterning, etch, HfO2 removal 3- Source/Drain formation Selective epitaxy growth (insitu doped or undoped with extension & S/D implant Salicidation 4- MOL and BEOL ILD/Via/Metal Interconnect Backend 10/10/ SOITEC Confidential FD-SOI technology

42 28nm FDSOI Process Migration Process steps 10/10/ SOITEC Confidential FD-SOI technology

43 Global Foundries 22nm FD-SOI Process Flow 38 Masks and 8 metal Levels 10/10/ SOITEC Confidential FD-SOI technology

65/45/28nm FDSOI UTBB substrate Elevated Si EPI S/D N+ Si Epi NMOS PMOS N+ Si Epi P+ Si Epi P+ Si Epi Ground Plane Ground Plane 22/14nm FDSOI UTBB substrate SiGe Channel for PMOS Insitu doped SiGe

44 65/45/28nm FDSOI UTBB substrate Elevated Si EPI S/D N+ Si Epi NMOS PMOS N+ Si Epi P+ Si Epi P+ Si Epi Ground Plane Ground Plane 22/14nm FDSOI UTBB substrate SiGe Channel for PMOS Insitu doped SiGe and SiC EPI for S/D P-Si(C) NMOS P-Si(C) B-SiGe PMOS B-SiGe Ground Plane 10nm FDSOI ssoi substrate SiGe Channel for PMOS Insitu doped SiGe & Si(C) EPI for S/D NMOS PMOS P-Si(C) P-Si(C) B-SiGe B-SiGe Ground Plane Ground Plane 10/10/2017

45 FD-SOI: FinFET performance at lower manufacturing cost 10/10/ SOITEC Confidential FD-SOI technology

46 Agenda 1 FD-SOI technology overview 2 Markets, foundries offers & ecosystems 3 FD-SOI material & roadmap 4 Summary 10/10/ SOITEC Confidential FD-SOI technology

FD-SOI brings many differentiation in Mobile, IoT, 5G &

Low-mid tier Baseband + AP 4G transceiver integration 5G mmwave

single chip solution with integrated PA <6GHz applications w/

ULP / ULL IoT clients in need of : On-demand processing

advantages in low power/ high reliability (SER) ADAS (<5W) for

Infotainment MCU for Body Electronics FD-SOI global wafers

47 FD-SOI brings many differentiation in Mobile, IoT, 5G & Automotive markets Mobility Best Power/Perf/Cost solution for Low-mid tier Baseband + AP 4G transceiver integration 5G mmwave design 5G & Radars Ideal technology for 5G mmwave low power single chip solution with integrated PA <6GHz applications w/ 35-50% die shrink (LTE, Wifi, ) IoT Perfect fit for wireless & ULP / ULL IoT clients in need of : On-demand processing performance Integrated RF Embedded memory Automotive Unique advantages in low power/ high reliability (SER) ADAS (<5W) for autonomous driving Radar - Mid to long range single chip Infotainment MCU for Body Electronics FD-SOI global wafers estimate: 10/10/ SOITEC Confidential FD-SOI technology 2021 (est.): 1-3M wafers/y. Source : Soitec estimates

The FD-SOI Revolution has started in Consumer & Automobile Consumer: a game

battery-powered device potential Automotive : best power efficiency allowing

ADAS level 3 applications Next generation e-cockpit solution with full management

5 to 10x Now, more than a day autonomy with GPS ON i.

48 The FD-SOI Revolution has started in Consumer & Automobile Consumer: a game changer technology for better battery life FD-SOI technology unlocks battery-powered device potential Automotive : best power efficiency allowing simpler integration and enhanced reliability FD-SOI - reference technology for ADAS level 3 applications Next generation e-cockpit solution with full management of car infotainment FD-SOI based Sony GPS to cut standard GPS power consumption by 5 to 10x Now, more than a day autonomy with GPS ON i.mx based reference platform developed by NXP for Amazon s Alexa FD-SOI is a key enabler of the i.mx reference platform for always-on applications Level 3 autonomous driving only 3W Advanced features - object recognition through neural network 10/10/ SOITEC Confidential FD-SOI technology

49 FD-SOI: Strong traction from foundries Samsung GlobalFoundries 10/10/ SOITEC Confidential FD-SOI technology

50 28nm FD-SOI cheaper cost per gate & design cost 10/10/ SOITEC Confidential FD-SOI technology

51 FD-SOI A mainstream solution with many choices Performance & density at any cost - for Servers, networking & High-end Mobile FinFET 7nm FinFET 10 nm FinFET 16/14nm HK, PolySi 28nm Bulk 90/65/45 nm R.Martino - Shanghai FD SOI Forum Sept /10/ SOITEC Confidential FD-SOI technology

FinFET 7nm FinFET 10 nm Cost-effective & performance for

16/14nm FD-SOI 22 nm emram HK, PolySi 28nm FD-SOI 28 nm emram

52 FD-SOI A mainstream solution with many choices Performance & density at any cost - for Servers, networking & High-end Mobile FinFET 7nm FinFET 10 nm Cost-effective & performance for Low-power applications FD-SOI 12 nm FD-SOI 18 nm emram FinFET 16/14nm FD-SOI 22 nm emram HK, PolySi 28nm FD-SOI 28 nm emram Bulk 90/65/45 nm FD-SOI 65 nm 10/10/ SOITEC Confidential FD-SOI technology

FD-SOI: ecosystem getting stronger Latest Announcements GLOBALFOUNDRIES Research Technology & IP A rapidly

Chengdu municipality to invest 100M$ to build a world-class FD-SOI ecosystem including multiple design centers

Design Services SAMSUNG Extension of current 28 nm FD-SOI platform by incorporating RF and embedded MRAM 18 nm

53 FD-SOI: ecosystem getting stronger Latest Announcements GLOBALFOUNDRIES Research Technology & IP A rapidly growing FD-SOI ecosystem Substrates Foundries&IDM Fabless & OEMs Consumer Products GLOBALFOUNDRIES and the Chengdu municipality to invest 100M$ to build a world-class FD-SOI ecosystem including multiple design centers and accelerate adoption of 22 FD-SOI (FDX) in China Increasing 22 FD-SOI capacity: +40% est. in Germany by 2020 New 300 mm fab. in China with expected volume production in 2019 Focus on 12 FD-SOI development & Licensees Tools & EDA IP & Design Services SAMSUNG Extension of current 28 nm FD-SOI platform by incorporating RF and embedded MRAM 18 nm FD-SOI process technology targeted for risk production in fabless under development CEA - LETI Presented path to 10nm FD-SOI IP/ EDA Vendors Active position in promoting FD-SOI 10/10/ SOITEC Confidential FD-SOI technology

54 Agenda 1 FD-SOI technology overview 2 Markets, foundries offers & ecosystems 3 FD-SOI material & roadmap 4 Summary 10/10/ SOITEC Confidential FD-SOI technology

FD-SOI Substrate Maturity Long collaborative history on FD-SOI Smart Cut & device experts

foundry offer 2005 2005 2005 2008 2010 2014 2015 FD-SOI substrate reached production maturity

uniformity specification met with CpK>1: all wafers, all points Differential Reflective

requirements >95% device wafer yield demonstrated at foundry Top silicon thickness Full wafer

55 FD-SOI Substrate Maturity Long collaborative history on FD-SOI Smart Cut & device experts Research Institute Donor substrate Advanced R&D Industrialisation 28FD foundry offer 22FD foundry offer FD-SOI substrate reached production maturity since 2013 Proven manufacturing capability on more than wafers +/-5Å top silicon uniformity specification met with CpK>1: all wafers, all points Differential Reflective Metrology defined to predict / protect variability on device Defectivity in line with foundry requirements >95% device wafer yield demonstrated at foundry Top silicon thickness Full wafer thickness deviation(å) (41 points per wafer, ~15k wafers) 10/10/ SOITEC Confidential FD-SOI technology

56 Thickness control > ± 1 Atomic Layer! Silicon thickness uniformity is guaranteed to within just a few atomic layers: +5Å Target -5Å Soitec FD-SOI wafer ±5Å ±1,4cm 10/10/ SOITEC Confidential FD-SOI technology

57 Standard Smart-Cut process flow and FD-SOI specifics enabling ultra thin SOI film and BOX High qualitytop wafer for thin SOI film compatibility Adapted to thin BOX Adaptedto thinsoi film Adapted to thin BOX Adaptedto thinsoi film 10/10/ SOITEC Confidential FD-SOI technology

Efficient collaboration with equipment makers Example of FD-SOI roughness management Enhanced

Local Thickness Variability Within Wafer Uniformity DRM 6σ (A) < 3.0 < 3.5 < 4.0 < 4.5 < 5.0 < 5.

0 Tool customized with new deposit management for SOI manufacturing New tool redesign ongoing

58 Efficient collaboration with equipment makers Example of FD-SOI roughness management Enhanced smoothing with Kokusai batch anneal technology Unique chip scale thickness measurement developed with HSEB F.De Crecy CEA/LETI Simulation of silicon smoothing under high temp anneal HSEB Baldur tool FD-SOI Local Thickness Variability Within Wafer Uniformity DRM 6σ (A) < 3.0 < 3.5 < 4.0 < 4.5 < 5.0 < 5.5 < 6.0 < 6.5 < 7.0 > 7.0 Tool customized with new deposit management for SOI manufacturing New tool redesign ongoing for enhanced flow managment to achieve ultimate FD-SOI roughness & uniformity Collaboration on Differential Reflective Metrology development Full map thickness measurement a critical parameter for FD-SOI 10/10/ SOITEC Confidential FD-SOI technology

59 A multi-nodes FD-SOI Product Roadmap Target node 65FD 28FD 22FD 12FD Beyond 12FD Box thick. 15nm 25nm 20nm 15 20nm 20nm FD-SOI substrate Top Si unif Top Si thick. Top Si Mob. ± 1.0 nm 30 nm Si unstrained ± 0.5 nm 12 nm Si unstrained ± 0.5 nm 12 nm Si unstrained ± 0.4 nm 12 nm Si unstrained tbd Pending device Si / SiGe Strained / relaxed Industrial status Prod. Prod. Prod. Dev. R&D 10/10/ SOITEC Confidential FD-SOI technology

SOITEC FD-SOI wafer capacity UP TO 1.5MWAFERS/YEAR CAPACITY WITHIN EXISTING FACTORY Phase 1 Phase 2 Phase 3 3Mw/y 1.5 Mw/y 100 Kw/y 500 Kw/y Soitec Capacity only.

60 SOITEC FD-SOI wafer capacity UP TO 1.5MWAFERS/YEAR CAPACITY WITHIN EXISTING FACTORY Phase 1 Phase 2 Phase 3 3Mw/y 1.5 Mw/y 100 Kw/y 500 Kw/y Soitec Capacity only. Not taking into account SOITEC licensees Detailed Capex and Operational plans are defined for Bernin 2 (up to 500kw) and Singapore (up to 1Mw) Will be triggered in coordination with foundries demand Phase 2: Singapore fab will get full qualification at customer level in first half 2019 Phase 3 (additional >1,5Mw) is in planning stage different options (locations, partners) are being considered estimated time to qualified fab: 24 months timing will be coordinated with foundries 10/10/ SOITEC Confidential FD-SOI technology Today +6 months +18 months Next Phase*

61 Summary FD-SOI enables far better scalability and transistor characteristics than planar bulk higher performance lower power better reliability wider operating range through its back-bias capability FD-SOI is a simpler and cost-efficient process/design than other fully depleted approaches FD-SOI allows very strong differentiation in low power & 5G markets FD-SOI roadmap down to 12nm is already definded by foundry The value of FD-SOI is now recognized by fabless and is about to be introduced in high volume consumer products FD-SOI is enabled by SOITEC engineered substrates SOITEC has the capacitity to support multi-million wafers/year supply chain FD-SOI ecosystem is getting ready 10/10/ SOITEC Confidential FD-SOI technology

62 THANK YOU SOITEC Confidential FD-SOI technology 10/10/

63 Disclaimer Exclusive property of Soitec. This document contains confidential information. Disclosure, redisclosure, dissemination, redissemination, reproduction or use is limited to authorized persons only. Disclosure to third parties requires a Non Disclosure Agreement. Use or reuse, in whole or in part, by any means and in any form, for any purpose other than which is expressly set forth in this document is forbidden. 10/10/ SOITEC Confidential FD-SOI technology

SOI technology platforms for 5G: Opportunities of collaboration

SOI technology platforms for 5G: Opportunities of collaboration Dr. Ionut RADU Director, R&D SOITEC MOS AK workshop, Silicon Valley December 6th, 2017 Sourcing value from substrate Robert E. White ISBN-13: