Highlights in Microtechnology HiM 2014, EPFL IMT-NE, June 18 th, 2014

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1 Highlights in Microtechnology HiM 2014, EPFL IMT-NE, June 18 th, 2014 CMOS scaling down for digital, analog & mixed signals in microelectronics circuits & systems EPFL STI IMT-NE ESPLAB Pierre-André Farine CMOS digital, analog & mixed microelectronics ICs 1 Content MOSFET Basics, CMOS, Memories CMOS Technology scaling Changes in CMOS and implications on digital and analog circuits Conclusions CMOS digital, analog & mixed microelectronics ICs 2

2 MOSFET Perspective view [Sze] CMOS digital, analog & mixed microelectronics ICs 3 MOS diode - Energy band diagram at V = 0 E 0 E g 2 [Sze] CMOS digital, analog & mixed microelectronics ICs 4

3 Ideal MOS diode - Energy Band diagrams and charge distributions 3 cases (a) accumulation (b) depletion (c) inversion qs q c1) Weak inversion: B S 2B c2) Strong inversion: 2 S B [Sze] CMOS digital, analog & mixed microelectronics ICs 5 n-mos FET Energy Band Profile Two-dimensional band diagram of an n-channel MOSFET: (a) Device configuration. (b) Flat-band zero-bias equilibrium condition. (c) Equilibrium condition (V DS = 0) under a positive gate bias. (d) Nonequilibrium condition under both gate and drain biases. [Sze] CMOS digital, analog & mixed microelectronics ICs 6

4 MOSFET - I D = f(v D ) & I D = f(v G ) Idealized drain characteristics I D = f(v D ) Transfer characteristics in linear region I D = f(v G ) [Sze] CMOS digital, analog & mixed microelectronics ICs 7 MOSFET operated in linear and saturation (a) in the linear region (low V,) (b) at onset of saturation, and (c) beyond saturation (effective channel length is reduced). [Sze] 2.1 CMOS digital, analog & mixed microelectronics ICs 8

5 CMOS digital, analog & mixed microelectronics ICs 9 D T G o n D V V V C L Z I MOSFET - The Main Equations I. Linear Region: Drain Current: for V D << (V D V T ) II. Triode region: Threshold Voltage: B O B A s T C qn V 2 ) ( D D T G o n D V V V V C L Z I V-I Characteristics: III. Saturation Region: Saturation Voltage: T G D V V V sat Drain Current: 2 2 T G o n D V V L C Z I sat Transconductance: ) (. T G ox n cst V G D m V V dl Z V I g D CMOS digital, analog & mixed microelectronics ICs 10 MOSFET Parameters [Baker]

6 Layout of a conventional MOS transistor CMOS digital, analog & mixed microelectronics ICs 11 Determining Threshold Voltage V T Graph showing the root of saturated drain current as a function of drain-source voltage Body Biasing CMOS digital, analog & mixed microelectronics ICs 12

7 I d (V ds, V gs ) characteristics Conventional operation (Strong inversion) Sub-threshold operation (Weak inversion) When the gate voltage is below the threshold voltage and the semi-conductor surface is only weakly inverted, the corresponding drain current is called the sub-threshold current. The sub-threshold region is particularly important when the MOSFET is used as a lowvoltage, low-power device such as a switch in digital logic and memory applications, because the sub-threshold region describes how the switch turns on and off. To reduce the sub-threshold current to a negligible value, we must bias the MOSFET a half-volt or more below V T. In the sub-threshold region, the I d (V ds, V gs ) characteristics of a MOSFET are similar to that of a BJT with high transconductance, low saturation voltage and high temperature sensitivity. CMOS digital, analog & mixed microelectronics ICs 13 Subthreshold characteristics of a MOSFET Inverse slope is subthreshold swing, S [mv/dec] (S~ 80 mv/dec) [Sze] CMOS digital, analog & mixed microelectronics ICs 14

8 MOSFET Operation: Gate Control [King Liu] 2.1 CMOS digital, analog & mixed microelectronics ICs 15 DIGITAL CMOS IC INVERTER: CIRCUIT LAYOUT Complementary MOS inverter. (a) Circuit diagram (b) Circuit layout. (c) Cross section along dotted A-A line of (b). [Sze] CMOS digital, analog & mixed microelectronics ICs 16

9 DIGITAL CMOS INVERTER TRANSFER CURVE [Baker] CMOS digital, analog & mixed microelectronics ICs 17 CMOS Logic Gates [R. Jacob Baker ] 7.18 CMOS digital, analog & mixed microelectronics ICs 18

10 Digital Model of MOSFET f T gm 2 C G VG V... n 2 2 L T V n L Dsat W g C V V L 0 m n G T 1 2 L [Baker ] CMOS digital, analog & mixed microelectronics ICs 19 Basic Common Source Amplifier: Analog Voltage Gain VDD R R Circuit Schematic Equivalent Circuit [Baker] CMOS digital, analog & mixed microelectronics ICs 20

11 CMOS n-mos Input Analog Differential Amplifier CMOS p-mos Input Analog Differential Amplifier Eliminates the body effect [Baker] CMOS digital, analog & mixed microelectronics ICs 21 Noise - CMOS differential amplifier (a) Noise sources added into the basic diff. (b) Modeling the amplifier noise at the input (c) Total output noise over a 1-Hz bandwidth CMOS digital, analog & mixed microelectronics ICs 22

12 SRAM Memory Cell Structure V DD V DD V DD WORD I WORD High Speed High Cost Low Density BIT I L H V DD Six-transistor full CMOS BIT I-I CMOS digital, analog & mixed microelectronics ICs 23 Impact of Variability on SRAM 2.1 CMOS digital, analog & mixed microelectronics ICs 24

13 Impact of V DD & size on SRAM RDF and VT DF fluctuations cause the SRAM s static noise margin to vanish! Impact of Vdd scaling Impact of bit cell scaling 03/22/2012 CMOS digital, analog & mixed microelectronics ICs 25 DRAM Memory Cell Structure Column WORD LINE Row Storage Capacitor PASS TRANSISTOR CAPACITOR CAPACITOR PLANAR WORD LINE PASS TRANSISTOR CAPACITOR WORD LINE PASS TRANSISTOR STACK TRENCH CMOS digital, analog & mixed microelectronics ICs 26

14 Row and Column Addresses CAS RAS DRAM Memory Architecture address multiplexing Row Address Buffer Column Address Buffer Row Decoder bandwidth Word-line Driver I/O line Memory Array Sense Amplifier Column Decoder Sense delay word line delay Refresh circuit Input Buffer Output Buffer D in D out CMOS digital, analog & mixed microelectronics ICs 27 DRAM Trench Cell Deep of >7 m Surface area is then large CMOS digital, analog & mixed microelectronics ICs 28

15 SRAM Layout size (140F 2 ) vs. DRAM (8F 2 ) CMOS digital, analog & mixed microelectronics ICs 29 EPROM, EEPROM & Flash Memory Basic Operation Principle Storage of charges Source Gate n + n + P -sub Q T Drain Darin Current Erased Sense voltage Programmed Gate Voltage, V GS CMOS digital, analog & mixed microelectronics ICs 30

16 Types of EEPROM (NVM) Floating Gate Charge-Trapping Control gate ONO Floating gate Si 3 N 4 Poly-gate Blocking Oxide Tunnel oxide EPROM EEPROM Flash SONOS CMOS digital, analog & mixed microelectronics ICs 31 EEPROM (Electrically Erasable Programmable Read Only Memory) Byte-Alterable Control gate Floating gate Bit line Source n + n + p-substrate Tunnel oxide Select- Line Word Line CMOS digital, analog & mixed microelectronics ICs 32

17 EEPROM Charge Transfer Mechanisms Hot-Electron Injection Avalanche Injection Channel Hot-Electron Injection Source-Side Electron Injection Substrate Injection Fowler-Nordheim Tunneling Ultraviolet Light Erase CMOS digital, analog & mixed microelectronics ICs 33 Comparison EEPROM vs. Flash CMOS digital, analog & mixed microelectronics ICs 34

18 Flash - Cell Architecture CMOS digital, analog & mixed microelectronics ICs 35 CMOS Technology Complementary Metal-Oxide-Semiconductor CMOS First proposed in the 1960s. Was not seriously considered (except by watchmakers!) until the severe limitations in power density and dissipation occurred in n-mos circuits Now the dominant technology in IC manufacturing Employs both p-mos and n-mos transistors to form logic elements The advantage of CMOS is that its logic elements draw significant current only during the transition from one state to another and very little current between transitions - hence power is conserved. CMOS digital, analog & mixed microelectronics ICs 36

19 CMOS Technology Scaling 1. CMOS scaling driven by digital applications Memories: high density and low power constraints Microprocessors: high performance and speed 2. Analog use a digital process as bare bones baseline 3. Huge implications on analog design, creating new challenges as silicon continues to scale down, including headroom, gain, leakage, variations, mismatches and automated CAD [Bergemont, 2012] 03/22/2012 CMOS digital, analog & mixed microelectronics ICs 37 CMOS Technology Scaling The Dilemma [Bergemont, 2012] CMOS digital, analog & mixed microelectronics ICs 38

20 MOSFET - Scaling Relations CMOS digital, analog & mixed microelectronics ICs 39 MOSFET - Scaling Relations CMOS digital, analog & mixed microelectronics ICs 40

21 MOSFET - Miniaturization Rules The consequences of applying the Constant-Field scaling rules 1. Depleted Region x' 2 s qkn d max 2 B B V K SB xd K max 2. Threshold Voltage V ' Q f KC Vs K 1 KC 2 qkn V K SB T ' ms 2 ' B s B2 ' B ~ ox ox VT K 3. Drain Current I' D Z L d K ox ox VG K VT K VD VD 2K K I D K CMOS digital, analog & mixed microelectronics ICs 41 International Technology Roadmap for Semiconductors ITRS for Deep Submicron CMOS Technologies Technology node (nm) Gate length L G (nm) Voltage supply (V) Dielectric equivalent thickness (nm) Threshold voltage V TH (V) Leakage current (µa/µm) On state current (µa/µm) NMOS delay CV/I (ps) CMOS digital, analog & mixed microelectronics ICs 42

22 MOSFET - Miniaturization Problems Standard Size L decreased (Holding all other parameters constant) CMOS digital, analog & mixed microelectronics ICs 43 Influence of the drain depletion region L DD : depleted region of drain L =L-L DD Depleted Region L DD 2 sv qn B dd V dd V D -V D,sat V D,sat V G -V To CMOS digital, analog & mixed microelectronics ICs 44

23 Consequences of an excessively large drain depletion region A. B. Miniaturized gate Standard gate Reduced Early voltage Reduced breakdown voltage Punch-through CMOS digital, analog & mixed microelectronics ICs 45 Reduction of threshold voltage V T Review: (std. channel lengths) V T V FB 1 2 B 2 sqn B (2 B VB ) C' Q d = q X dmax W N a L G At miniaturized scales, the depletion regions of S and D substitute an important part of Q d This reduced the threshold voltage (V T ) compared with standard channel lengths CMOS digital, analog & mixed microelectronics ICs 46

24 MOSFET - Miniaturization Problems Effects of High Electric Fields: 1. Breakdown Breakdown of gate oxide (E max ~ 5x10 6 V/cm) Breakdown of the drain-substrate junction 2. Generation of Hot Electrons E Kinetic > E G i.e. Avalanche effects CMOS digital, analog & mixed microelectronics ICs 47 Electrical field along the channel CMOS digital, analog & mixed microelectronics ICs 48

25 Energy-band diagram at the semiconductor surface from source to drain - DIBL DIBL (a) Long channel MOSFETs Dashed lines V D = 0, solid lines V D > 0. (b) Short-channel MOSFETs DIBL - Drain-Induced Barrier Lowering effect in the latter Short-Channel Effect (SCE) CMOS digital, analog & mixed microelectronics ICs 49 MOSFET: Hot Electrons CMOS digital, analog & mixed microelectronics ICs 50

26 MOSFET: Hot Electron Effects 1. Injection and trapping Instability 2. Avalanche multiplication Holes 3. Substrate Current Polarization of substrate 4. Injection of electrons Current leakage and breakdown 5. Bipolar transistor effects Current leakage and breakdown CMOS digital, analog & mixed microelectronics ICs 51 MOSFET: Lightly Doped Drain (LDD) SUB P N DRAIN Conventional LDD N+ Goal: Avoid problems due to hot electrons CMOS digital, analog & mixed microelectronics ICs 52

27 The CMOS Power Crisis CMOS digital, analog & mixed microelectronics ICs 53 Sources of Variability CMOS digital, analog & mixed microelectronics ICs 54

28 Improving I ON /I OFF [King Liu] CMOS digital, analog & mixed microelectronics ICs 55 MOSFET in ON State (V GS > V TH ) [King Liu] 2.1 CMOS digital, analog & mixed microelectronics ICs 56

29 Optimizing MOSFET Performance CMOS digital, analog & mixed microelectronics ICs 57 Reduced SCE with Body Biasing CMOS digital, analog & mixed microelectronics ICs 58

30 CMOS Technology Scaling [King Liu] CMOS digital, analog & mixed microelectronics ICs 59 MOSFET Performance Boosters [King Liu] CMOS digital, analog & mixed microelectronics ICs 60

31 Analog Scaling Parameters 1. Headroom (V DD & V T Scaling) 2. Transconductance & output impedance 3. Mismatch (random & systematic) 4. Leakage 5. Modeling methodology/eda tools CMOS digital, analog & mixed microelectronics ICs 61 Headroom: V DD / V t Scaling 1) V DD cuts down active power consumption for digital circuitry quadratically: P = C V 2 2) But V DD /V t don t decrease anymore with scaling : flatting out ~ 65nm due to substantial static power consumption (dramatic increase in BOTH Off state LATERAL and VERTICAL leakage) 3) Headroom reduction a problem for analog designs 4) Minimum theoretical V GS value: kt/q = 26 mv at room temp and n = 1 + C D /C ox, in which C D is the bulk Depletion layer capacitance under the channel and C ox the gate oxide capacitance. Note that this value is about 80 mv and does not depend on channel length (n 1.6). [Bergemont] CMOS digital, analog & mixed microelectronics ICs 62

32 Off State lateral leakage & Temperature Weak inversion mode (below VT) : Id exponentially dependent on the value of V gs Vt. S does not scale with technology scaling (~ 1.4) S~ room temp and 85C Reducing Vt by 100mV increases off current by an order of magnitude. Sharper subthreshold slope is obtained by reducing either T or n, with expensive technologies such as FD SOI, FinFet (S~ 60mV/dec) Exacerbated with Temperature (~ 1.25 mv/c) : For specifications ranging from 40C to 85C, shift due to temp alone is ~ 170mV With S = 65mV/dec & assuming sub-threshold occupies 4-5 decade (resulting in an I on to I off ratio approaching 10 5, 300mV = V t would ensure an acceptable I on /I off ratio for digital logic. [Bergemont] CMOS digital, analog & mixed microelectronics ICs 63 V T variations issues Vt variations -> Huge impact on both speed and standby power dissipation. Example : - speed performance impact due to +/-100mV VT variation is about +/-2.5% in a 5V process with VT of 800mV & rises to +/- 12% in a 1V process with Vt = 200mV! - Standby current : assuming Ids = 1uA at Vgs = Vt, S=100mV/dec, the highest off current in above example would be 100fA for 5V-high Vt and 10nA for 1Vlow Vt. Such a large impact on speed and standby power intolerable circuit techniques are often required to address this issue multiple Vt processes offers circuit design flexibility at the expense of cost (Low-Vt for circuit speed and high- Vt to reduce the I leak ) [Bergemont] CMOS digital, analog & mixed microelectronics ICs 64

33 Physics of V T variations V T variability tied to process variations (random dopant fluctuations RDF & channel length variations) Standard deviation due to random dopant fluctuations RDF concentration variation is: A VT improves with scaling ( ox ) but decrease less than predicted oxide thickness scaling as MOS scaling forces the doping level under the gate to increase [Bergemont] CMOS digital, analog & mixed microelectronics ICs 65 Effects of Random Dopant Fluctuations RDF RDF Random Dopant Fluctuations getting worse as less dopants in the channel At minimum L, control and variations are exacerbated, mainly through Vt Vt dependence on Vds getting worse (SCE) Better control with large W Discrete dopants randomly distributed in (Xnm) 3 cubes with average conc of 5X10 18 cm dopants within (100nm) 3 cube Average 40 dopants within its 125 sub cubes of (20nm) 3 NMOS VT & Ioff [L down to 20nm for (a) width=200nm and (b) width=20nm at Vd=1.0V (Source TSMC)] [Bergemont] CMOS digital, analog & mixed microelectronics ICs 66

34 Differential amplifier gain analog FOM Commonly used as good analog FOM R R Gain limited to < g m /g ds Mobility on the wish list General practice : use longer W Lambda known also as 1/VA VA called Early Voltage [Bergemont] CMOS digital, analog & mixed microelectronics ICs 67 Gate Leakage Mechanism is tunneling through thin gate oxide. Gate leakage extremely sensitive to the oxide thickness. 65nm node shifted the leakage by more than six orders of magnitude as compared to 0.18 um node For digital circuits, power associated with gate leakage is acceptable until oxide thickness reduces less than 2nm (~1A/cm2) When high-κ materials are used as the gate insulator in later generation devices, gate leakage currents are greatly reduced. [Bergemont] [Bergemont] CMOS digital, analog & mixed microelectronics ICs 68

35 Latest changes in CMOS and the implication on Analog design RESOLUTIONS: (digital scaling) Gate leakage by using High K dielectric V t variations by using undoped channels and Metal Gate Lateral leakage by using exotic structures : FinFet, UTSOI, FDSOI CMOS digital, analog & mixed microelectronics ICs 69 Un doped channels With undoped channels, Fermi potential and the depletion charge are approximately zero, and the expression for the threshold voltage becomes: Thus the threshold voltage of the transistor is essentially set by the gate workfunction. Two solutions for achieving a Vt ~ 0.35V band edge gate materials (N+/P+Poly gates) with high channel doping ~ 1X10 18 cm3 or mid gap gate material with low channel doping 1X10 15 cm3 [Bergemont] CMOS digital, analog & mixed microelectronics ICs 70

36 Structures to resolve lateral leakage ISSUE drain control competing with gate control SOLUTIONS Provide gate control from more than one side of the channel (Multi gate FETs) Vertical gates: FINFET Lateral Gates : UTSOI Channel consists of two vertical surfaces and the top surface of the fin (Intel) [Bergemont] FDSOI with back planes Fully Depleted Silicon On Insulator (ST 28nm) CMOS digital, analog & mixed microelectronics ICs 71 Resulting in good news for analog design 1. Better matching No Vt variation due to RDF Demonstrated with FDSOI (mainly LETI/ST and IBM) & FinFets (INTEL, IMEC) 2. Better gm/gds 6 A VT IBM ST BULK ST IBM Intel Intel IMEC FINFET LETI FDSOI IBM FDSOI FDSOI (Fully Depleted SOI) better FINFET sensitive to fin height control [Bergemont] CMOS digital, analog & mixed microelectronics ICs 72

37 Unknown & Concerns (1) 1. Battle for mainstream technology still not resolved (FDSOI vs. FINFET) INTEL : FinFet ST/IBM: FDSOI Foundries:? IBM INTEL 2. Expensive: - Resources commitment & IP: INTEL, ST/IBM alliance, TSMC - At least 300mm tools [Bergemont] CMOS digital, analog & mixed microelectronics ICs 73 Unknown & Concerns (2) 3. EDA: FDSOI FET similar to a bulk FET > extend applicability of existing design and EDA tools. FinFET: part of the width of the transistor is in the vertical direction > traditional EDA tool cannot be used 4.Specific New materials, new difficulties Dual gate diel, embedded NVM CMOS digital, analog & mixed microelectronics ICs 74

38 FINFET, FDSOI FINFET Significantly more complex than either strained Si (90nm) or HKMG (<45nm) 4 years in pathfinding phase, 4 years in full scale development Thousand of wafers run, large development team (2000+) Compatibility with SoC environment unclear Multiple VTs and oxide thickness, body bias power mode Next issues? Highly restrictive design rules > favors adoption by IDM, not foundry Restrictive design rules > footprint penalty Incompatibility with existing IP blocks > no IP reuse EDA availability? Foundry strategy? FDSOI Cost increase ~ $500 EDA on line with current planar Compatibility with SoC environment unclear Multiple VTs and oxide thickness, body bias power mode (doped channel or multiple work functions?) Rext issues? [Bergemont] CMOS digital, analog & mixed microelectronics ICs 75 Foundries benchmark 28nm first note with Metal gate New structure expected 14nm CMOS digital, analog & mixed microelectronics ICs 76

39 Conclusions - MOSFET Evolution [King Liu] CMOS digital, analog & mixed microelectronics ICs 77 Conclusions Analog design main issue is headroom Good news is that matching and Gain improves while scaling digital CMOS Innovations required to design at lower Vcc CMOS digital, analog & mixed microelectronics ICs 78

40 Chip Scale Cs Atomic Clock CMOS digital, analog & mixed microelectronics ICs 79 Some References S. M. Sze, Kwok K. Ng, Semiconductor Devices, 3 rd Edition, John Wiley and Sons Inc., 2007 H. Mathieu, H. Fanet, Physique des Semiconducteurs et des composants électroniques, Dunod, Paris, 2009 R. Jacob Baker, CMOS Circuit Design, Layout and Simulation, 3 rd edition, 2010 A. Bergemont, Lessons from 15 years of fab development for deep sub-micron mixed signal ICs, IEEE Swiss Chapter, March 2012 T. J. King Liu, Bulk CMOS Scaling to the End of the Roadmap, Symposium on VLSI Circuits Short Course, UC Berkeley, June 2012 CMOS digital, analog & mixed microelectronics ICs 80