Technology Advantages for Analog/RF & Mixed-Signal Designs

Transcription

1 Technology Advantages for Analog/RF & Mixed-Signal Designs Andreia Cathelin STMicroelectronics, Crolles, France SOI Consortium Forum, Tokyo, January 21 st, 2016

2 Agenda 2 At a glance ST 28nm UTBB FD-SOI CMOS: Simpler Analog Integration Advantages for analog design Advantages for RF/mmW design Advantages for Mixed-Signal design Conclusion and takeaways Nota: all measurement data from ST 28nm FD-SOI CMOS, unless otherwise specified

3 Transistor 3 Bulk Gate Gate Source Drain Source Drain Ultra-Thin Buried oxide Substrate Punch Through! Substrate Typical Transistor in today CMOS System on Chip Change of Substrate adding the thin Buried oxide Improving power Efficiency Bringing high flexibility in SoC integration While keep very similar manufacturing flow

4 Fully Depleted Transistors FinFET FinFET & FD-SOI : Just a rotation ultimately converging when scaling BOX to TOX

5 Addressing Digital Markets 5 FinFet High end servers Networking Infrastructure Consumer Multimedia Internet of Things, Wearable Laptops & tablet-pc Smartphone Available from 28nm node Automotive Ultimate Digital Integration Ultimate Digital + AMS + RF + Integration

6 Example: Ultra Low Power in IoT 6 SoC Architecture 34 mw* Power Supply Loss SoC Power Consumption RF Analytics RF CPU & Memories Power Management Analytics CPU & Memories Other Previous Generation (40LP) <10 mw* FD-SOI 28nm X3 to X6 Power Consumption Improvement with FD-SOI <5 mw** FD-SOI 28nm optimized design * Measured on Silicon / Product Simulation ** Projection

7 ST 28nm FD-SOI Transistor Flavors 7 Low VT (LVT) CMOS in FD-SOI; flipped-well VBBN D NMOS G BOX N-Well PMOS S P-Sub D PMOS G BOX NMOS P-Well S VBBP LVT NMOS LVT PMOS Nominal VBB GND VDD GND Biasing mode FBB FBB -3 VBBN Bulk type CMOS VBBP D G BOX N-Well S P-Sub D G S BOX P-Well VBBN RVT PMOS RVT NMOS VDD GND RBB RBB -3 VBBP Vth (V) RBB FBB FBB RBB NLVT NRVT PLVT PRVT Regular VT (RVT) CMOS in FD-SOI VB (V)

8 for Simpler Analog Integration 8 ST 28nm FD- SOI makes analog/rf/hs designer s life easier Improved Analog Performance Improved Noise Efficient Short Devices Very large V T tuning range High performance frequency behavior Speed increase in all analog blocks Higher gain for a given current density Lower gate and parasitic capacitance Lower noise variability Better matching for short devices and efficient design with L>L min Analog parameters wide range tuning via a new independent tuning knob (back-gate) f T / f max >300GHz for LVTNMOS and high performance passives enabling RF/mmW/HS integration with technology margin Higher bandwidth Lower power Smaller designs Improved design margins wrt PVT variations Novel flexible design architectures

9 σ(log(w*l*si d /I d ²)) SI d /I d ²(/Hz) SI d /I d ²(/Hz) Advantages in Analog Design 9 Efficient Short Devices Improved Analog Perf. Improved Noise NMOS_SOI_W=9(µm) 1,E-06 1,E-07 model L=0,903(µm) L=0,03(µm) 1,E-08 1,E-09 1,E-10 1,E-06 1,E-11 1,E-08 1,E-07 1,E-06 1,E-05 1,E-04 1,E-07 1,E-03 1,E-02 I drain (A) NRVT_Bulk_W=9(µm) model L=0,903(µm) L=0,03(µm) L=9,903(µm) L=0,273(µm) 1,E-08 Higher Gm for a given current density 1,E-09 1,E-10 1,E-11 1,E-08 1,E-07 1,E-06 1,E-05 1,E-04 1,E-03 1,E-02 I drain (A) 0,45 0,4 NMOS C028_SOI C045 0,35 C028_LVT Efficient use of short devices : High analogue Low L Low Vt mismatch (Avt ~ 2mv/µm) Performance example: A 10µm/100nm device has a DC gain of 100, & a svt of only 2mV! Lower gate capacitance Higher achievable bandwidth or lower power for a given bandwidth 0,3 0,25 0,2 0,15 0,1 0, /sqrt(W*L)(µm -2 ) Same normalized drain current noise between BULK and FD-SOI Lower noise variability for FD-SOI Improved noise in FD-SOI Courtesy, L. Vogt, F. Paillardet, C. Charbuillet, P. Scheer, STMicroelectronics

10 V T [mv] Advantages in Analog Design-II 10 Very large V T tuning range by FBB ST 28nm LVT NMOS (typical) +3V FBB VBBN Bulk FD-SOI P-Sub 0V Forward body bias [V] VBBP Flip-well devices: Large Forward Body Bias (FBB) range Negligible control current FD-SOI (flip-well flavor/lvt devices) -3V P-sub Use back-gate as «VT tuning knob»: Unprecendented ~250mV of tuning range for FD-SOI vs. ~ 10 s mv in any bulk Courtesy, A. Cathelin, STMicroelectronics

11 Analog Filter Design Example 11 Filters with several 100 s MHz bandwidth - PVT + ageing affect system operation - Need to tune/trim independently several parameters impacting overall system: V DD V Filter Regulator drop (>20%) Tuning margin Global supply cut-off frequency, linearity, noise, all for an optimal power consumption Filter supply Regular CMOS Tuning/trimming solution: Voltage regulator impacting directly the signal path behavior FD-SOI revolutionary solution: individual transistors body biasing oxide-isolated from the signal path behavior

12 Typical example of Analog Filter 12 Inverter-based analog functions: attractive implementations: simple and compact scale nicely with technology nodes Here: analog low-pass Gm-C filter Typical implementation: Fixed capacitors Tune the filter cut-off frequency by tuning Gm Bulk specific solution: Tune local Vdd Local V DD FD-SOI specific solution: Tune all VBB s

13 gm Tuning Gm with V DD OK: gm variation; NOK: linearity 13 Local V DD Tune Gm value with local VDD Major issue: it changes also linearity and noise behavior V DD high nominal low 0 V input

14 gm gm FD-SOI: Tuning gm with Vbody OK: gm variation; OK: linearity 14 New tuning knob (and off the signal path): VBBP and VBBN Compensate V DD variations Tune gm back to nominal Ensure constant linearity operation V DD high nominal low 0 Without back-gate bias V input 0 With back-gate bias V input

15 Inverter-based Analog Filter 15 RF low-pass Gm-C filter using CMOS inverters Tuned by back-gate instead of supply (no signal path interference) Supply regulator-free operation Energy efficient Low voltage operation (VDD = 0.7V) Competitive linearity Compared to similar circuit in 65nm bulk [2], at same noise level, get X2 linearity for /4 power level [J. Lechevalier at al, ISSCC2015] [2] Houfaf, et al., ISSCC 2012 [5] Saari, et al., TCAS-I 2009 [6] Mobarak, et al., JSSC 2010 [7] Kwon, et al., TMTT 2009 Compared to best-in-class filters [7], at same noise level and Fc, get competitive linearity for /14 power level Best in class in terms of the compromise noise-linearity-power Integrated in ST 28nm FD-SOI CMOS

16 Advantages in RF/mmW Design 16 Active devices high frequency performance Performant passive devices Nbt = 1 For ST 28nm FD-SOI LVTNFET: f T / f max >300GHz Nbt = 2 to 6 For RF operation frequency : Work with L = 100nm MAG = NFmin ~ 10GHz current density: 125 µa/µm For mmw operation frequency (intrinsic models): Lmin MAG = NFmin ~ 60GHz current density: 200 µa/µm 33% less power than in 28LP bulk Operation frequency range : 2 GHz - 50 GHz Inductance range: 0.1 nh - 28 nh Q factor range: Size: 60x60 µm² 600x600 µm² Courtesy, L. Vogt, F. Paillardet, C. Charbuillet, P. Scheer, C. Durand STMicroelectronics

17 Average PAE (at 8-dB back-off) [%] PAE at 8-dB back-off [%] dc consumption [mw] Dissipated power [mw] GHz transceivers (RF TX part) 65nm JSSC 2011 ISSCC 2011 PA 65nm Other TX blocks 90nm JSSC nm ISSCC 2014 ISSCC nm 50% power in mmw TRx spent in PA High dc consumption Low average PAE Solve the general trade-off linearity and power consumption High PAPR Output Average power at 8-dB power back-off GHz PA Output power [dbm] CMOS 40nm CMOS 65nm JSSC, 2013 WiGiG with max. operation 8dB back-off high linearity with optimized power JSSC, 2012 ISSCC, 2014 RFIC, 2014 RFIC, 2014 JSSC, 2010 MWCL, 2015 ESSCIRC, dB compression point [dbm] 17

18 Novel mmw Power Amplifier thanks to FD-SOI and wide-range body biasing 18 Classical Doherty Power Amplifier Revisit classical Doherty power amplifier architecture FD-SOI-specific Doherty Power Amplifier Class C V DD, RF Out+ RF Out-, V DD Class AB Class AB Class C V B1 V B2 V B1 Two different class power amplifier in parallel Ability of gradualy change the overall class of the PA (mix of class AB and class C) thanks to wide range FBB optimise in the same time power efficiency and linearity Remove signal path power splitter as in classical implementations reduced signal path losses RF In+, V G_DC V G_DC, RF In-

19 60GHz Configurable PA 19 This work S. Kulkarni ISSCC 2014 D. Zhao JSSC 2013 D. Zhao JSSC 2012 E. Kaymaksut RFIC 2014 A. Siligaris JSSC 2010 Technology 28nm UTBB FD-SOI 40nm 40nm 40nm 40nm 65nm PD-SOI Operating mode High gain High linearity NA Low/High power NA NA NA Supply voltage [V] Freq. [GHz] Gain [db] / P SAT [dbm] / P 1dB [dbm] / PAE max [%] / PAE 1dB [%] / PAE 8dB_backoff [%] / P DC [mw] / 75 # P DC_8dB_backoff [mw] / 78 # xP 1dB /P DC / 32 # Active area [mm²] * ITRS FOM [W.GHz²] 161,671 1,988 1,198 6, / 2,832 13, ,038 Fully WiGiG compliant (linearity and frequency range) New PA architecture: continuously reconfigurable power cells Continuous operation class tuning thanks to body bias with 2 extreme modes: High gain mode: Highest ITRS FOM 10X better than previous SoA High linearity mode: Break the linearity / consumption tradeoff ULV high efficiency operation (Vdd_min = 0.8V) ITRS FOM = P SAT.PAE max.gain.freq² [A. Larie et al., ISSCC2015] * : with pads # : estimated Integrated in ST 28nm FD-SOI CMOS

20 Advantages in MS Design 20 Variability Switch performance Lower capacitance Lower juction capacitance makes a substantial difference in high-speed circuits Drastic reduction of self-loading in gain stages Drastic reduction of switch selfloading Tighter process corners and less random mismatch than competing processes Benefits: Simpler design process, shorter design cycle Improved yield or improved performance at given yield Improved gate control allows smaller VTH Backgate bias allows for VTH reduction by tuning Results is an unprecedented quality of analog switches Compounding benefits: smaller R -> smaller switch -> compact layout -> lower parastics -> even smaller switch Key for high performance data converters and other Switched- Cap. Circuits Two-fold benefit: Leads to incremental improvements Allows the designer to use circuit architectures that would be infeasible/inefficient in bulk technologies Courtesy, S. Le Tual, STMicroelectronics; B. Murmann, Stanford Univ.

21 High-Speed Time Interleaved-ADC example 21 Lower Vth, less variability Better switch: R ON & linearity Faster logic Reduced S/D capacitances Increased comparator BW Reduced switch parasitics [S. Le Tual et al., ISSCC2014] Verma ISSCC 2013 Tabasy VLSI 2013 Kull VLSI 2013 This Work Technology 40nm CMOS 65nm CMOS 32nm SOI 28nm FD-SOI Architecture TI-FLASH TI-SAR TI-SAR TI-SAR Power Supply (V) / Sampling Rate (GS/s) Resolution (bits) Power Consumption (mw) Nyquist (db) Active Area (mm 2 ) Nyquist (fj/conv) Max Input Frequency (GHz) Gain/Skew Calibration Yes Yes Yes No Energy efficient operation Integrated in ST 28nm FD-SOI CMOS O : 28FD-SOI or 32nm SOI Courtesy, B. Murmann, Stanford Univ.

22 Takeaways for Analog/RF/mixed-signal 22 ST 28nm FD-SOI CMOS arguments: For Analog/RF design: FBB as VT tuning knob ultra large tuning range for VT Very good analog performance lower power consumption and operate at L>Lmin for design margin For RF/mmW design, operate at Lmin and add: Efficient Flexible Simple Deep submicron technology features: Front-end: performant f T, f max Back-end + FD-SOI features: performant passive devices For mixed-signal/high-speed design: Improved variability Switch performance Reduced parasitic capacitance

23 Take-aways charts per field

24 Analog/RF design in FD-SOI 24 FD-SOI arguments: FBB as VT tuning knob ultra large tuning range for VT Very good analog performance lower power consumption and operate at L>Lmin for design margin Consequences on analog/rf design: Operate amplifiers at constant Gm Employ new tuning strategies Competitive noise and linearity behavior Obtain strong design independence with respect to PVT variations New robust design oportunities

25 RF/mmW design in FD-SOI 25 FD-SOI arguments: FBB as VT tuning knob ultra large tuning range for VT Very good analog performance lower power consumption Deep submicron technology: Front-end: performant f T, f max Back-end + FD-SOI features: performant passive devices Consequences on RF/mmW design: New family of reconfigurable topologies; new design architectures Power efficient solutions State of the art implementations with concomitent optimisation for each system-level parameter New robust design oportunities

26 FD-SOI arguments: Improved variability Switch performance Reduced parasitic capacitance Mixed-signal / High-speed design in FD-SOI 26 Consequences on MS design: State of the art HS Data Converters Drastic improvement of the Nyquist FOM (FOM=P/(f s *2 ENOB ) ) New robust design oportunities and new design architectures enabled