Product Design Methodology
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1 Product Design Methodology 2018 Tokyo Christophe Tretz, Carlos Mazure 1 SOI Industry Consortium 2018
2 Agenda SOI Industry Consortium SoC design approach Design considerations Conclusions 2 SOI Industry Consortium 2018
3 2014 FD-SOI Where s the supply chain? 3 SOI Industry Consortium
4 2018 FD-SOI Substrates: production Foundry: production IP: good enough and improving The Ecosystem is ready Focus: Applications and Products 4 SOI Industry Consortium
5 SoC Design Approach 5 SOI Industry Consortium 2018
6 Design Flow Design flow System Specification Architectural design Functional/Logic design Circuit design Physical design Physical verification and signoff Fabrication Starting a new design will go through all the steps from system specification to manufacturing and testing. Packaging and testing Chip 6 SOI Industry Consortium 2018
7 Design Flow Design flow System Specification Architectural design Functional/Logic design Circuit design Physical design Physical verification and signoff Fabrication Using FD-SOI, the following steps could take advantage of the technology, either through performance estimation (blue) or bias connections (orange) Packaging and testing Chip 7 SOI Industry Consortium 2018
8 Design Flow Design flow System Specification Architectural design Functional/Logic design Circuit design Physical design Physical verification and signoff Fabrication Packaging and testing Chip It is not necessary to optimize an SoC design at every stage, but improvements can be obtained progressively 8 SOI Industry Consortium 2018
9 Design Flow Case 1: Simple digital SoC System Specification Architectural design Functional/Logic design Circuit design Physical design Physical verification and signoff Fabrication Packaging and testing Chip All digital SoC, using basic library blocks, with some specialized proprietary logic Most standards blocks are already available in foundry libraries Recompile the proprietary logic with or without back bias optimization Benefit savings from the existing optimized blocks Using this approach, significant power savings can be achieved by reusing existing blocks and doing minor recompile 9 SOI Industry Consortium 2018
10 Design Flow Case 2: RF Mixed signal chip System Specification Architectural design Functional/Logic design Circuit design Physical design Physical verification and signoff Fabrication Packaging and testing While this type of design likely need to do a full circuit design and physical design, they are usually small and easier to control Turnaround time can be relatively small with significant savings in power Example: AnalogBits SERDES remap completed in 3 months minimum layout fixes greatly improved performance!!! Chip 10 SOI Industry Consortium 2018
11 Design Flow Case X: fully optimized SoC System Specification Architectural design Functional/Logic design Circuit design Physical design Physical verification and signoff Fabrication Packaging and testing Sometimes a full optimization is desired, and some design can benefit from all the advantages of FD-SOI Architecture and logic can be further optimized and changed to take into account back bias This approach will take the most design time, but can be done in parallel with a faster turnaround design Most dramatic power improvements!! Chip 11 SOI Industry Consortium 2018
12 A short history of circuit design 12 SOI Industry Consortium 2018
13 Why looking at the past? The SOI Consortium is often asked how difficult it is to use FD-SOI in designs Many circuit design techniques were created BC (Before CMOS), without even going to prehistoric eras of circuit design (think TTL, ECL, etc) The same basic design guidelines still apply, maybe more than ever Circuit design techniques evolved into what is CMOS design And, maybe designing with back gate bias is not such a new thing We can all learn from the past and why people designed a certain way There are always new ways to use something, and several talks from past SOI Consortium events have shown such techniques (Andrea s, Borat s presentations are great example of what can be done) 13 SOI Industry Consortium 2018
14 Enhancement/Depletion mode MOS design Overview: Logic high is only Vdd Vth (enhancement only, full swing with depletion device load) Fabrication of both types of devices is tricky BUT: still better than any type of ECL or TTL design! Solutions: Improve the load devices (Bootstrapped nmos, depletion, pmos) Using back gate biasing to change operation mode 14 SOI Industry Consortium 2018
15 Intel 4004 The Intel 4004 is a 4-bit central processing unit (CPU) released by Intel Corporation in It was the first commercially available microprocessor by Intel, [2] and the first in a long line of Intel CPUs. The 4004 employs a 10 µm process silicongate enhancement load pmos technology on a 12 mm² die 15 SOI Industry Consortium 2018
16 Pseudo nmos The logic evolution from nmos logic to logic with nmos/pmos Large ratio between respective device performance made CMOS area prohibitive Pseudo nmos reduce the gate loading significantly Clocking/dynamic logic is a direct improvement on pseudo nmos 16 SOI Industry Consortium 2018
17 Domino and Zipper (NORA) logic Domino logic is fast, but inverters are needed Zipper logic removes the need of inverters and solve some charge sharing and charge leakage issues 17 SOI Industry Consortium 2018
18 Why did I go over those logic design styles? Design has evolved over time Many design choices were related to what was available at the time, and trade offs were made to compensate relative performance or manufacturing shortcomings FD-SOI offers new opportunities, but also allows to go back to past decisions For example, having a stronger pmos load would remove some drawbacks from having a pmos load (pseudo nmos) or a pmos pullup network (zipper) Depletion/enhancement devices mix offered some interesting construct (forward/reverse bias do too ) 18 SOI Industry Consortium 2018
19 What about body biasing? Body biasing is not really new First order, body biasing is not a mandatory design option; a fixed value can be used and the various EDA tools available will take care of the implementation/verification Body biasing offers many design options and design philosophies 19 SOI Industry Consortium 2018
20 Body Biasing Leveraging for Market Leadership Vdd Overdrive Only SOG Global Body Biasing Independent Domain Body Biasing On Chip Memory Array Body Biasing Assymetric Device Body Biasing Mixed Vt Common Well Body Biasing Courtesy Ron Martino, NXP SOI Consortium Silicon Vally SOI Industry Consortium 2018
21 Back gate bias: an additional performance boost knob Current high performance SoC/microprocessors use Vdd to alter performance Increasing Vdd will improve speed/overall performance but will also increase consumed power By decreasing Vdd (or turning it off), you can enter a sleep/lower power mode (or turning off unused parts of the SoC Back gate biasing offers more tuning options You can use both Vdd and various back gate bias values to either improve performance even more You can also use both Vdd and other back gate bias values to improve overall performance while not increasing power as much You can use other back gate bias values to enter low Vdd operation mode and enable low power performance 21 SOI Industry Consortium 2018
22 Conclusions The ecosystem has been ready and there are many ways to approach designing with FD-SOI We do not need to reinvent the wheel!!! A lot of solutions are there already even if we have to look in the past. There is more than one way to use back gate bias!! Finally, do not hesitate to contact the Consortium! We are here to help you! 22 SOI Industry Consortium 2018
23 Backup slides 23 SOI Industry Consortium 2018
24 Remap example: AnalogBits Courtesy: AnalogBits - SOI Consortium April SOI Industry Consortium 2018
25 Remap example: AnalogBits ANALOG BITS achieved this work in about 3 months!!! Courtesy: AnalogBits - SOI Consortium April SOI Industry Consortium 2018
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