CMOS Technology for Computer Architects

Transcription

1 CMOS Technology for Computer Architects Lecture 1: Introduction Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTH-ICS (University of Crete) Course Contents Implementation of high-performance digital designs CMOS ASIC designs and standard-cell flow Course goals (what will you learn?) Ability to design, implement, evaluate and optimize designs with respect to different constraints: size, speed, power dissipation, and reliability Course prerequisites Fluency in digital logic design at the gate level and above Good knowledge of Computer Architecture Some knowledge of HDL will be helpful 1 2 Course Administration Course Administration Instructors Iakovos Mavroidis (jacob@ics.forth.gr) Giorgos Passas (passas@ics.forth.gr) Manolis Katevenis (kateveni@ics.forth.gr) Joint Graduate Course UoC, UPC, Chalmers Course Web Cast Website Project Standard cell implementation and evaluation Sources Recent publications Roadmaps (ITRS) Digital Integrated Circuits, 2 nd Edition, Rabaey et. al. Live streaming Recorded lectures Check:

2 Detailed Topics Today s Lecture - Introduction Lectures Transistor Logic and CMOS inverter Static and dynamic CMOS gates Interconnect Network on Chip Standard-Cell design flow EDA tools Crossbar Memories Chip-to-chip communication Sequential circuits Power consumption Clock trees Design intensive class 65nm and 40nm Synopsys synthesis Cadence PnR Digital Integrated Circuit Design: The Past, The Present and The Future Why is designing digital ICs different today than it was before? Will it change in the future? Transistor Switch model 5 6 Digital Design Abstraction Levels Switch Model of MOS Transistor Digital ICs are ubiquitous. Why? Electronic switching device Source Drain focus NMOS device 7 8 2

3 Technology (nm) Semiconductor manufacturing processes Why Scaling? Strained Silicon (2002) Technology shrinks by ~0.7 per generation With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly High-k + Metal Gate (2007) 8 Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years 1 Year tri-gate (2011) Hence, a need for more efficient design methods Exploit different levels of abstraction 9 10 Design Complexity Trends Transistor Revolution Bell Labs, 1948 First Transistor Intel, 1971 (Moore, Noyce) 2,300 transistors 740KHz operation 10μm (=10000nm) PMOS technology Intel Core i7, ,600,000 transistors 3.4GHz 32nm ITRS,

4 Moore s Law Transistor Count In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 months (i.e., grow exponentially with time). Pentium 4 AMD K8 10-Core Xeon Core i7 He made a prediction that semiconductor technology will double its effectiveness every 18 months. Pentium Doubles every 2 years! Transistor Count (GPUs FPGAs) Clock Frequency ~2 times more transistors than CPUs GPU Year Manufa cturer Transistor Count NV NVIDIA 15M NV NVIDIA 25M NV NVIDIA 222M GT NVIDIA 1.4B RV AMD 2.1B GF NVIDIA 3B Tahiti 2011 AMD 4.3B ~3 times more transistors than CPUs FPGA Year Manufac turer Transistor Count Virtex-E 1998 Xilinx 200M Virtex-II 2000 Xilinx 350M Virtex Xilinx 1B Virtex Xilinx 1.1B Stratix IV 2008 Altera 2.5B Stratix V 2011 Altera 3.8B Virtex Xilinx 6.8B Intel Core i7 (2011) 3.4GHz Xilinx s 3D (or 2.5D) packaging Speed/Power tradeoff: Underclocking single core by 20% saves half the power while sacrificing13% of the performance => use more parallelism

5 Power (Watts) Power Supply Die Size H. Iwai, Micr. Eng., 2009 Trends of supply voltage for various versions of ITRS Past Present CPU Year Die Size Pentium Pro mm 2 Pentium II mm 2 AMD T-Bird mm 2 P mm 2 AMD K mm 2 grows by ~14% every 2 years CPU Process Cores Transistor Die Size AMD Bulldozer 8C 32nm 8 1.2B 315mm 2 AMD Thuban 6C 45nm 6 904M 346mm 2 AMD Deneb 4C 45nm 4 758M 258mm 2 Intel Gulftown 6C 32nm B 240mm 2 Intel SandyBridge 4C 32nm 4 995M 216mm 2 Intel Lynnfield 4C 45nm 4 774M 296mm 2 Intel Clarkdale 2C 32nm 2 384M 81mm 2 Intel SandyBridge 2C 32nm 2 624M 149mm Power Dissipation Technology Trends All in one PentPro Pentium Pentium4 Core i5 Power has to stay ~constant (~100W) Year

6 Design Metrics Major Design Challenges How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Speed/Performance (delay, frequency) Power Microscopic issues Ultra-high speeds Interconnect Noise, Crosstalk Variability Reliability Power dissipation Clock distribution Power Performance Time to market Macroscopic issues Complexity Time-to-market Reuse and IP, portability Systems on a chip (SoC) High-level abstractions Tool interoperability Everything Looks a Little Different The NMOS Transistor Cross Section Switch Model of NMOS Transistor W L V s < V D

7 Switch Model of NMOS Transistor Switch Model of PMOS Transistor Strong 0 Weak Threshold Voltage Concept Threshold Voltage Concept V s V G V GS < V T V D V s V G V GS < V T V D V GS > V T V s V G V D V B V B V B Three voltage differences V GS = V G V S V DS = V D V S V SB = V S V B When V S = V B = 0 V GS = V G V DS = V D V SB = 0 Three voltage differences V GS = V G V S V DS = V D V S V SB = V S V B When V S = V B = 0 V GS = V G V DS = V D V SB = 0 The value of V GS where strong inversion occurs is called the threshold voltage, V T

8 Threshold Voltage Body Effect Threshold Voltage V T = V T0 + ( -2 F + V SB - -2 F ) V B = 0 = V T0 + ( -2 F + V S - -2 F ) V SB is the source-bulk voltage V T0 is the threshold voltage at V SB = 0 F -0.3V (called Fermi Potential) γ (called body-effect coefficient) depends on the gate capacitance per unit area H. Iwai, Micr. Eng., 2009 Trends of supply voltage and threshold voltage for various versions of ITRS Multi-gate MOSFET and FinFET Multi-gate MOSFET and FinFET Traditional Planar Traditional Planar Gate 1 Source Drain Gate 2 P. Mishra et. al, Nan. Circ. Des.,

9 Multi-gate MOSFET and FinFET Multi-gate MOSFET and FinFET Traditional Planar 3D Tri-gate third dimension! L G H fin W fin Mark Bohr, Intel, 2011 FinFET announced for 22nm production ( 11) After 11 years R&D low Vdd operation and chip power savings Multiple fins to increase drive strength Mark Bohr, Intel, 2011 P. Mishra et. al, Nan. Circ. Des., nm Tri-Gate Circuit 35 9