Kenneth R. Laker, University of Pennsylvania, updated 20Jan15

Transcription

1 1

2 TOPICS The Course Industry Trends Digital CMOS Basics Some VLSI Fundamentals Illustrative Design Example 2

3 1. Apply principles of hierarchical digital CMOS VLSI, from the transistor up to the system level, to the understanding of CMOS circuits and systems that are suitable for CMOS fabrication. 2. Apply the models for state-of-the-art VLSI components, fabrication steps, hierarchical design flow and semiconductor business economics to judge the manufacturability of a design and estimate its manufacturing costs. 3. Design simulated experiments using Cadence to verify the integrity of a CMOS circuit and its layout. 4. Design digital circuits that are manufacturable in CMOS. 5. Apply the Cadence VLSI CAD tool suite layout digital circuits for CMOS fabrication and verify said circuits with layout parasitic elements. 6. Apply course knowledge and the Cadence VLSI CAD tools in a team based capstone design project that involves much the same design flow they would encounter in a semiconductor design industrial setting. Capstone project is presented in a formal report due at the end of the semester. 3

4 Classification of Digital CMOS Circuits STATIC CIRCUITS DYNAMIC CIRCUITS STATIC CIRCUIT In steady-state the output is always at a 1 or 0 via a lowimpedance path between the output and VDD or GND, respectively. DYNAMIC CIRCUIT In steady-state the output is at 1 or 0 due to the presence or absence of charge, respectively, stored on the output node capacitance. 4

5 Course Introduction 5

6 COURSE PROTOCOLS Grading Policies Homework: 20 % Midterm 05Mar15: 40 % Project 07May15: 40 % Homework Policies Homework assignments are combination of textbook problems, CADENCE tutorial & CADENCE lab exercises. Homework is assigned each week by Friday and will be due on Thursday the week after it is assigned. All homework assignments and due dates will be posted on the ESE 570 website Students are permitted up to THREE one-week latenesses without penalty. a. On three occasions homework may be turned-in one week after the official due date, unless it falls on a university or religious holiday. b. Homework not turned in accordance with policy will receive zero grade. 6

7 Industry Trends 7

8 Microprocessor Transistor Count & Moore's Law 16-Core SPARC T3 10-Core Xenon 6-Core 6-Core i7 i7 IBM 4-Core z196 2-Core Itanium 2 IBM 8-Core POWER7 4-Core Itanium Tukwilla AMD K10 AMD 6-Core Opteron Core i7 Curve shows transistor count doubling every two years Pentium AMD K8 Pentium 4 AMD K7 Pentium III Pentium II AMD K Mot Mot Zilog Z MOS : Oracle SPARC M7, 20 nm CMOS, 32-Core, 10B 3-D FinFET transistors

9 TREND Minimum Feature Size vs Year Process Node/ Minimum Feature 100 µm Integrated Circuit History 10 µm 1 µm ITRS Roadmap 0.18 µm in µm 10 nm Distant Future Transition Region 1 nm Quantum Devices 0.1 nm 1960 Atomic Dimensions Year Minimum Feature Measure = line/gate conductor width or half-pitch (adjacent 1st metal layer lines or adjacent transistor gates) 9

10 Intel Cost Scaling 10

11 22 nm 3-D FinFET Transistor High-k gate dielectric Tri-Gate transistors with multiple fins connected together increases total drive strength for higher performance 11

12 Moore's Law Impact on Intel Micro-Computers 2BT µp (Intel Itanium Tukwila) 4-Core chip (65 nm) introduced Q BT mp (Intel Itanium Poulson) 8-Core chip (32 nm) to be introduced Serial data22 links at 10 Gbits/sec. Introduces nm operating Tri-gate Transistor Tech. Increased reuse of logic IP, i.e. designs and cores. Complexity - # transistors Double every Two Years ' m ' m YEAR 12

13 Moore's Law and More Geometrical g ScalinScaling Equivalent Scaling More-than-Moore, International Road Map (IRC) White Paper, International Technology Road Map for Semiconductors 13

14 More Moore => Scaling Geometrical Scaling - refers to the continued shrinking of horizontal and vertical physical feature sizes. Equivalent Scaling - refers to 3-dimensional device structure improvements and new materials that affect the electrical performance of the chip even if no geometrical scaling. Design Equivalent Scaling - refers to design technologies that enable high performance, low power, high reliability, low cost, and high design productivity even if neither geometrical nor equivalent scaling can be used. Examples include: Design-for-variability Low power design (sleep modes, clock gating, multi-vdd, etc.) Multi-core SOC architectures 14

15 Examples of More Than Moore Devices More than Moore => Functional Diversification Interacting with the outside world Electromagnetic/Optical - Radio-frequency domain up to the THz range - Optical domain from the infrared to the near ultraviolet - Hard radiation (EUV, X-ray, γ-ray) Mechanical parameters (sensors/actuators) - MEMS/NEMS position, speed, acceleration, rotation, pressure, stress, etc. Chemical composition (sensors/actuators) Biological parameters (sensors/actuators) Powering Integration of renewable sources Energy storage Smart metering Efficient consumption 15

16 More-than-Moore Components Complement Digital Processing/Storage Elements in an Integrated System 16

17 3D integration of More-than-Moore photodetector with More Moore ROIC and DSP optical Back-Side Illuminated (BSI) Photodiode Array Readout Integrated Circuit (ROIC) Digital Signal Processing (DSP) electrical 17

18 Semiconductor System Integration More Than Moore's Law SOP law for system integration. As components shrink and boards all but disappear, component density will double every year or so Systemin-package System- 103 Multichip (SIP) on-package Module (SOP) Components/cm2 Transistors/cm R. Tummala, Moore's Law Meets Its Match, IEEE Spectrum, June,

19 System-on-Package Vision (Georgia Tech 3D Systems Packaging Research Center) 19

20 Improvement Trends for VLSI SoCs Enabled by Geometrical and Equivalent Scaling TRENDS 1. Higher Integration level -> exponentially increased number of components/transistors per chip/package. 2. Performance Scaling -> combination of Geometrical (shrinking of dimensions) and Equivalent (innovation) Scaling. 3. System implementation -> SoC + increased use of SiP -> SOP CONSEQUENCES 4. Higher Speed -> CPU clock rate at multiple GHz + parallel processing. 5. Increased Compactness & less weight -> increasing system integration. 6. Lower Power -> Decreasing energy requirement per function. 7. Lower Cost -> Decreasing cost per function. 20

21 Digital CMOS Basics 21

22 Classification of Digital CMOS Circuits STATIC CIRCUITS DYNAMIC CIRCUITS STATIC CIRCUIT In steady-state the output is always at a 1 or 0 via a lowimpedance path between the output and VDD or GND, respectively. DYNAMIC CIRCUIT In steady-state the output is at 1 or 0 due to the presence or absence of charge, respectively, stored on the output node capacitance. 22

23 23

24 24

25 Ideal nmos and pmos Characteristics High Impedance or High Z g g=1 g=1 g=1 g a b g g=0 g b g=0 g=1 High Impedance or High Z a a b a g=0 a b g=0 If N- & P-Switch are MOS transistors a = drain & b = source 25

26 22 Complementary CMOS Switch -g g g -g -g g g 26

27 Ideal CMOS Inverter Inverter Truth Table PUN F=A F=A F=A A PDN F=A F=A 0 (GND) 27

28 F A? = N A F P 0 (GND) 0 (GND) 28

29 CMOS GATES VDD A B C D When the PUN is conducting, the output F will be 1. Hence,the PUN is determined by a Boolean expression for the un-complemented output F in terms of the complemented inputs (A,B,C,D). PUN Inputs F = f(a,b,c,d) A B C D PDN PUN and PDN are Dual Nets DeMorgan s Theorem Output When the PDN is conducting, the output F will be 0. Hence,the PDN is determined by a Boolean expression for the complemented output F in terms of the un-complemented inputs (A,B,C,D). 29

30 Two-Input CMOS NAND Gate DeMorgan's Theorem PUN F =% A$B& F =% A B& F A AND % A B & NOT % A B & = % A$B& OR % A$B& NOT B Gate Circuit Symbols F =% A B& PDN OUTPUT A-INPUT FF=% A B& A B-INPUT B Z = open circuit 30

31 Two-Input CMOS NOR Gate F PUN F =% A B& DeMorgan's Theorem % A$B& = % A B & B A % A$B& OR F F =% A$B& % A B & AND F =% A$B& PDN A $ B 31

32 Constructing Compound CMOS Gates F =%% A B&$%C D&& PUN (F = f(a,b,c,d) F =% A$B& %C $D& 1 X X 1 F X PUN PDN(F = f(a,b,c,d) F =%% A B&$%C D&& F 0 F F 0 F PDN 0 32

33 F =%% A B &$%C D&& Combining the PDN and PUN => 33

34 MULTIPLEXOR (MUX) output = A s$b s x = DON'T CARE 34

35 Some VLSI Fundamentals Oracle SPARC M7 Processor 35

36 VLSI Hierarchical Representations fabricated? - Circuit - Component 36

37 Y-Chart: Consistent Abstractions in 3 Domains System Level Algorithmic Level Behavioral Domain Register-Transfer Level Structural Domain System Specification CPU, ASIC Logic Level Algorithm Processor, Sub-system Register-Transfer Spec. ALU, Register, MUX Circuit Level Boolean Expression Gate/Flip-flop Transistor Model Equation Transistor symbols Transistor Layout Standard-cell/Sub-cell Layout Macro-cell/Module Layout Block/Die Layout Chip/SoC/Board Physical Domain 37

38 Goal of All VLSI Design Enterprises Convert System Specs into an IC DESIGN in MINIMUM TIME and with MAXIMUM LIKLIHOOD that the Design will PEFORM AS SPECIFIED when fabricated. MAX YIELD + MIN DEVELOPMENT TIME + MIN DIE AREA=> MIN COST TRADEOFFS MIN DIE AREA MIN DEVELOPMENT TIME MIN DIE AREA MAX YIELD 38

39 CMOS CHIP MANUFCTURING STEPS 39

40 Basic VLSI Chip Cost Model cost per packaged IC die = variable cost per IC packaged die + # good die FIXED COST: total cost due to expenditures that do not directly vary with sales, e.g. R&D, equipment depreciation, general operations and administration. mask set, all indirect costs. VARIABLE COST: total cost due to expenditures directly linked to making the product; e.g. engineering, wafer, mask set, test, package. variable cost variable cost per packaged = IC die (total # of die fabricated) * yield # good die # of IC dies satisfy ALL requirements total # of IC dies fabricated where 0 yield 1 (100 %) 40

41 VLSI Design Cycle or Flow Verilog/SPICE 41

42 Illustrative Circuit Design Example Design a One-Bit Adder Circuit using 00.8 (8µmtwin-well twin-wellcmos CMOSTechnology. technology. The The design specifications are: 1. Propagation Delay Times of SUM and CARRY_Out signals: 1.2 ns 2. Rise and Fall Times of SUM 2and CARRY_Out signals: 1.2 ns 3. Circuit Die Area: 1500 ' m 4. Dynamic Power Dissipation (@ VDD = 5 V and f max = 20 MHz): 1 mw 5. Functional 42

43 Bit-Sliced Data Path Control Bit N Data IN Data OUT Register ADDER Shifter Multiplier Bit 0 43

44 Illustrative Circuit Design Example Binary Full Adder (BFA) sum_out = A + B + C = ABC + ABC + ABC + ACB = ABC + (A + B + C) carry_out carry_out + AB + AC + BC Use of carry_out to realize sum_out reduces circuit complexity and die area. 44

45 Gate Level Schematic of One-Bit Full Adder Circuit NOT directly realizable in CMOS - Why? 45

46 8-bit Ripple Adder a<7:0> b<7:0> VDD BFA(0) cin BFA(1) BFA(2) BFA(7) cout clk GND 1-bit Adder Cell sum<7:0> a b vdd cin BFA cout gnd sum 46

47 42 Transistor Level Schematic of One-Bit Full Adder Circuit COUT % A$B & C $ A B COUT SUMOUT % A$B$C & COUT CMOS Implementable A B C$% A$B$C & COUT 47

48 Initial Layout of One-Bit Full Adder Circuit COUT N1 SUMOUT N2 COUT N1 N1 N2 N2 48

49 Initial Layout of One-Bit Full Adder Circuit COUT 1500 ' m 2 Dynamic Power Dissipation (@ VDD = 5V, f max = 20 MHz): = 0.7 mw 1 mw 49

50 Simulated Performance of One-Bit Full Adder Circuit Let all specs be met except tplh, i.e. Spec NOT met. 50