VLSI I (Introduction to VLSI Design) EE 382M-ECD (#14970)

Transcription

1 VLSI I (Introduction to VLSI Design) EE 382M-ECD (#14970) Spring 2004 Jacob A. Abraham Electrical and Computer Engineering 1 Example System-on-a-Chip (SoC) for Mobile Applications Source: ARM , J. A. Abraham 1

2 The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: 17,470 3 ENIAC - The first electronic computer (1946) , J. A. Abraham 2

3 A Brief History of the Transistor Some of the events which led to the microprocessor Photographs in the following are from State of the Art: A photographic history of the integrated circuit, Stan Augarten, Ticknor & Fields, They can also be viewed on the Smithsonian web site, 5 Early Ideas Leading to the Transistor J. W. Lilienfeld s patents 1930: Method and apparatus for controlling electric currents, U.S. Patent 1,745, : Device for controlling electric current, U. S. Patent 1,900, , J. A. Abraham 3

4 Key Developments at Bell Labs 1940: Ohl develops the PN Junction 1945: Shockley's laboratory established 1947: Bardeen and Brattain create point contact transistor (U.S. Patent 2,524,035) Diagram from patent application 7 Developments at Bell Labs, Cont d 1951: Shockley develops a junction transistor manufacturable in quantity (U.S. Patent 2,623,105) Diagram from patent application , J. A. Abraham 4

5 1950s Silicon Valley 1950s: Shockley in Silicon Valley 1955: Noyce joins Shockley Laboratories 1954: The first transistor radio 1957: Noyce leaves Shockley Labs to form Fairchild with Jean Hoerni and Gordon Moore 1958: Hoerni invents technique for diffusing impurities into Si to build planar transistors using a SiO 2 insulator 1959: Noyce develops first true IC using planar transistors, back-to-back PN junctions for isolation, diode-isolated Si resistors and SiO 2 insulation with evaporated metal wiring on top 9 The Integrated Circuit (IC) 1959: Jack Kilby, working at TI, dreams up the idea of a monolithic integrated circuit Components connected by hand-soldered wires and isolated by shaping, PN-diodes used as resistors (U.S. Patent 3,138,743) Diagram from patent application , J. A. Abraham 5

6 ICs, Cont d 1961: TI and Fairchild introduce the first logic ICs ($50 in quantity) 1962: RCA develops the first MOS transistor Fairchild bipolar RTL Flip-Flop RCA 16-transistor MOSFET IC 11 Computer-Aided Design (CAD) 1967: Fairchild develops the Micromosaic IC using CAD Final Al layer of interconnect could be customized for different applications 1968: Noyce, Moore leave Fairchild, start Intel , J. A. Abraham 6

7 Static and Dynamic RAMs 1970: Fairchild introduces the 4100, 256-bit Static RAM 1970: Intel starts selling a1k-bit Dynamic RAM, the 1103 Fairchild bit SRAM Intel K-bit DRAM 13 The Microprocessor! 1971: Intel introduces the first microprocessor, the 4004 (originally designed as a special circuit for a customer) , J. A. Abraham 7

8 MOS Technology Trends 15 VLSI Design - The Big Picture What do you do with a billion transistors? Need to be able to deal with complexity Important to identify potential applications Designing systems for a particular application: Identify sub-functions Design system using a variety of powerful Computer-Aided Design (CAD) tools Use a process relevant to industry Industry Consultants Dr. Raghuram Tupuri, AMD Dr. Mark McDermott , J. A. Abraham 8

9 Course Information Instructor: Jacob A. Abraham (512) , Course Web Page: 382m For material restricted to students in class, Use Blackboard: 17 Course Information, Cont d Prerequisites: logic design, basic computer organization Textbook: Rabaey et al., Digital Integrated Circuits: A Design Perspective, 2 nd Edition, Prentice-Hall, 2003 Lectures and discussion in class will cover basics of course Homework, Laboratory exercises will help you gain a deep understanding of the subject , J. A. Abraham 9

10 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, What is this book all about? Introduction to digital integrated circuits. CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. What will you learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability , J. A. Abraham 10

11 Evolution in Complexity 21 Transistor Counts 1,000,000 K 1 Billion Transistors 100,000 10,000 1, Pentium III Pentium II Pentium Pro i486 Pentium i Projected Source: Intel J. Courtesy, A. Abraham Intel , J. A. Abraham 11

12 Moore s law in Microprocessors Transistors (MT) X growth in 1.96 years! 10 P6 Pentium proc Transistors 0.01 on Lead Microprocessors double every 2 years Year J. Courtesy, A. Abraham Intel 23 Die Size Growth 100 Die size (mm) P6 486 Pentium proc ~7% growth per year ~2X growth in 10 years Year Die size grows by 14% to satisfy Moore s Law J. Courtesy, A. Abraham Intel , J. A. Abraham 12

13 Frequency Frequency (Mhz) Doubles every 2 years P6 Pentium proc Year Lead Microprocessors frequency doubles every 2 years J. Courtesy, A. Abraham Intel 25 Power Dissipation 100 Power (Watts) P6 Pentium proc Year Lead Microprocessors power continues to increase J. Courtesy, A. Abraham Intel , J. A. Abraham 13

14 Power will be a major problem Power (Watts) Pentium proc 18KW 5KW 1.5KW 500W Year Power delivery and dissipation will be prohibitive J. Courtesy, A. Abraham Intel 27 Power density Power Density (W/cm2) Rocket Nozzle Nuclear Reactor 8086 Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp J. Courtesy, A. Abraham Intel , J. A. Abraham 14

15 Not Only Microprocessors Cell Phone Small Signal RF Power RF Units Digital Cellular Market (Phones Shipped) M 86M 162M 260M 435M Power Management Analog Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments) 29 Challenges in Digital Design DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. 1/DSM Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. Everything Looks a Little Different? and There s a Lot of Them! , J. A. Abraham 15

16 Productivity Trends 10,000,000 10,000 1,000,000 1, , , , Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Complexity 2009 Logic Transistor per Chip (M) Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity J. Courtesy, A. Abraham ITRS Roadmap 31 Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction , J. A. Abraham 16

17 Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE D n+ 33 Design Metrics How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function , J. A. Abraham 17

18 Cost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area 35 NRE Cost is Increasing , J. A. Abraham 18

19 Die Cost Single die Wafer Going up to 12 (30cm) From 37 Cost per Transistor cost: -per-transistor Fabrication capital cost per transistor (Moore s law) , J. A. Abraham 19

20 π Dies per wafer = Yield No. of good chips per wafer Y = 100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer Die yield ( wafer diameter/2) die area 2 π wafer diameter 2 die area 39 Defects α defects per unit area die area die yield = 1+ α α is approximately 3 die cost = f 4 (die area) , J. A. Abraham 20

21 Some Examples (1994) Chip Metal layers Line width Wafer cost Def./ cm 2 Area mm 2 Dies/ wafer Yield Die cost 386DX $ % $4 486 DX $ % $12 Power PC $ % $53 HP PA $ % $73 DEC Alpha $ % $149 Super Sparc $ % $272 Pentium $ % $ Reliability Noise in Digital Integrated Circuits i(t) v(t) V DD Inductive coupling Capacitive coupling Power and ground noise , J. A. Abraham 21

22 DC Operation Voltage Transfer Characteristic V(y) V OH f V(y)=V(x) VOH = f(vol) VOL = f(voh) VM = f(vm) V Switching Threshold M V OL V OL V OH V(x) Nominal Voltage Levels 43 Mapping between analog and digital signals V out 1 V OH V OH Slope = -1 V IH Undefined Region V IL Slope = -1 0 V OL V OL V IL V IH V in , J. A. Abraham 22

23 Definition of Noise Margins "1" V OH V OL NM H NM L V IH Undefined Region V IL Noise margin high Noise margin low "0" Gate Output Gate Input 45 Noise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sources , J. A. Abraham 23

24 Key Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver; 47 Regenerative Property out out v 3 f (v) v 3 finv(v) v 1 v 1 finv(v) v 3 f (v) v 2 v 0 Regenerative in v 0 Non-Regenerative v 2 in , J. A. Abraham 24

25 Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5 v 6 A chain of inverters 5 V (Volt) 3 1 v 0 v 1 v 2 Simulated response t (nsec) 49 Fan-in and Fan-out N M Fan-out N Fan-in M , J. A. Abraham 25

26 ( V ) V o u t UT Austin, ECE Depatrment The Ideal Gate V out g = R i = R o = 0 Fanout = NM H = NM L = V DD /2 V in An Old-time Inverter 4.0 NM L V M 1.0 NM H V in (V) , J. A. Abraham 26

27 Delay Definitions V in 50% t V out t phl t plh 90% 50% 10% t t f t r 53 Ring Oscillator v 0 v 1 v 2 v 3 v 4 v 5 v 0 v 1 v 5 T = 2 t p N , J. A. Abraham 27

28 A First-Order RC Network R v out vin C t p = ln (2) τ = 0.69 RC Important model matches delay of inverter 55 Power Dissipation Instantaneous power: p(t) = v(t)i(t) = V supply i(t) Peak power: P peak = V supply i peak Average power: 1 P ave = T ) V t+ T supply t+ T p( t dt = t t T i supply () t dt , J. A. Abraham 28

29 Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av t p Energy-Delay Product (EDP) = quality metric of gate = E t p 57 A First-Order RC Network R v out vin C L E 0 1 T T Vdd = Pt ()dt = V dd i supply ()dt t = V dd C L dv out = C L V 2 dd T T Vdd 1 2 E cap = P cap ()dt t = V out i cap ()dt t = C L V out dv out = --C V 2 L dd , J. A. Abraham 29

30 Goals of this Course Learn to design and synthesize state-of-theart digital Very Large Scale Integrated (VLSI) chips using CMOS technology Employ hierarchical design methods Use integrated circuit cells as building blocks Understand design issues at the layout, transistor, logic and register-transfer levels Use commercial design software in the lab Understand the complete design flow Be able to design state-of-the-art CMOS chips in industry 59 Work in the Course Lectures Read sections in text and slides before class Homework problems Solve related problems on web each week Laboratory exercises Three major exercises dealing with various aspects of VLSI design Complete each section before the deadline Project Course involves a large amount of work throughout the semester , J. A. Abraham 30

31 Types of IC Designs IC Designs can be Analog or Digital Digital designs can be one of three groups Full Custom Every transistor designed and laid out by hand ASIC (Application-Specific Integrated Circuits) Designs synthesized automatically from a highlevel language description Semi-Custom Mixture of custom and synthesized modules 61 Steps in Designing Hardware Designer Tasks Tools Architect Define Overall Chip C/RTL Model Initial Floorplan Text Editor C Compiler Logic Designer Behavioral Simulation Logic Simulation Synthesis Datapath Schematics RTL Simulator Synthesis Tools Timing Analyzer Power Estimator Circuit Designer Cell Libraries Circuit Schematics Circuit Simulation Megacell Blocks Schematic Editor Circuit Simulator Router Physical Designer Layout and Floorplan Place and Route Parasitics Extraction DRC/LVS/ERC Place/Route Tools Physical Design and Evaluation Tools , J. A. Abraham 31

32 Laboratory Exercise 1 Schematics (Cadence) Library DRC LVS Layout (Cadence) Extraction (Cadence) Characterization SPICE Symbol Functional model (Simulation) Footprint (APR) Timing model 63 Laboratory Exercise 2 Library Schematics (Cadence) Functional Verification VerilogXL Library Data Path Block DRC LVS Layout Extraction Static Timing Analysis (Cadence) (Cadence) (Synopsys) Schematic Layout , J. A. Abraham 32

33 Laboratory Exercise 3 Verilog RTL model Synthesis (Synopsis) APR (Cadence) Extraction (Cadence) Static Timing Analysis (Synopsys) Control Block Formal Verification (Verplex) Netlist Layout 65 Laboratory Exercises 1. Layout and evaluation of memory cells, register file Familiarity with layout, circuit simulation, timing 2. Design and evaluation of an ALU, performance optimization Learn schematic design, timing optimization 3. Design, synthesis and analysis of a simple controller as part of an SoC Learn RT-level design, system simulation, logic synthesis and place-and-route , J. A. Abraham 33

34 Laboratory Design Tools We will us commercial CAD tools Cadence, Synopsys, HSpice, etc. Commercial software is powerful, but very complex Designers sent to long training classes Students will benefit from using the software, but we don t have the luxury of long training TAs have experience with the software Start work early in the lab Can access software from home (use X- emulator on Windows, or a Linux computer) Plan designs carefully and save work frequently 67 Homework, Exams and Project Homework exercises assigned each month Two in-class exams 75 minutes each No Final Exam All exams are open book, open notes Group (2-4 student) Project Topic of your choice , J. A. Abraham 34

35 Grading Weights for Final Grade: Homework Exams Laboratory Project 15% 30% 35% 20% 69 Academic Honesty Ethical professionals don t cheat Feel free to discuss homework, laboratory exercises with classmates, TAs and the instructors However, you should do the homework and lab exercises by yourself, and the submitted work should be your own , J. A. Abraham 35

36 What Will the Course Cover? How integrated circuits work How to design chips with millions of transistors Ways of managing the complexity Use of tools to speed up the design process Identifying performance bottlenecks Ways of speeding up circuits Making sure the designs are correct Making the chips testable after manufacture Other issues: effect of technologies, reducing power consumption, etc. 71 Learning General Principles Chip design involves optimization, tradeoffs We use an in-house 0.18µ technology library Non proprietary, principles apply to proprietary state-of-the-art technologies Technology changes fast, so it is important to understand the general principles Systems are implemented using building blocks (which may be technology-specific) Example: relays tubes bipolar transistors MOS transistors (which are like relay switches) Lot of work in course, but you ll learn a lot , J. A. Abraham 36