Dynamic behavior of the UTBB FDSOI MOSFET

Transcription

1 Dynamic behavior of the UTBB FDSOI MOSFET MOS-AK, March 12 th, 2015 Salim EL GHOULI 1, Patrick SCHEER 1, Thierry POIROUX 2, Jean-Michel SALLESE 3, Christophe LALLEMENT 4 André JUGE 1 1 STMicroelectronics, 2 CEA-LETI, 3 EPFL, 4 University of Strasbourg

2 Overview 2 Introduction Current work motivation High frequency modeling challenges FDSOI MOSFET predisposition for RF Modeling & characterization UTSOI2 compact model Equivalent circuit and enhancement proposal Characterization and parameters extraction Model validation Conclusion

3 Introduction

4 Current work motivation 4 Radio frequency (RF) and microwave integrated circuit engineering are growing rapidly in importance in recent years boosted by digital wearable and mobile communication devices The down scaling of MOSFETs and integration of many functions on a single chip are prerequisites for RF circuits RF performance of CMOS is rapidly increasing and is competing with the III-V compound based devices Need to well understand the FDSOI UTBB MOSFET behavior in high frequency regime Need to develop physical and accurate models for high frequency RF and low voltage design applications Goal is to predict accurately the small signal AC behavior at high frequency regimes

5 High frequency modeling challenges 5 Large number of physical effects have to be accurately modeled Better understanding of parasitic components is required Gate resistance is a critical limiter for RF FOMs [1] Substrate impedances Fringing capacitances High order current derivatives have to be accurately simulated RF distortion Non-Quasi-Static effects: g m and C gg frequency dependency for long MOSFETs Importance of thermal and gate induced noise Compact models and CAD integration: high frequency models are layout dependent and standardization is difficult Standard Analog & RF Cells [1] INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2013 EDITION

6 FDSOI MOSFET predisposition for RF 6 Better electrostatic control / mismatch / back gate control advantage Tradeoff between current efficiency and power consumption [2] No junction capacitances Reduced gate capacitance FDSOI BULK Reduced drain-to-well (Cdb) capacitance versus bulk Back gate bias flattens the f T V gs characteristic (highly linear amplifiers ) [3] [2] Joel Hartmann, FD-SOI technology development and key devices characteristics for fast, power efficient, low voltage SoCs IEEE Compound Semiconductor Integrated Circuit Symposium, La Jolla, California, USA, October 2014 [3] S. Shopov, S. Voinigescu Characterization of the High Frequency Performance of 28-nm UTBB FDSOI MOSFETs as a Function of Backgate Bias, IEEE CSICS Digest, San Diego, CA, October 2014

7 Modeling & characterization

8 Leti-UTSOI2 compact model 8 UTSOI2 is a surface potential based model for the Ultra Thin Body and Box Fully Depleted SOI MOSFET [4] Includes all relevant physical effects encountered in UTBB FDSOI MOSFET Includes drain/source series resistance with gate voltage dependence Charge model is taking into account intrinsic and parasitic charges (overlap and fringe capacitances) Symmetry and reciprocity of capacitances are met Noise model includes flicker, thermal, induced gate and shot noise sources UTSOI2 model is a good candidate for analog & RF FDSOI modeling [4] T. Poiroux et al, UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs, Electron Devices Meeting (IEDM), 2013 IEEE International, vol., no., pp ,12.4.4, 9-11 Dec. 2013

9 Equivalent circuit and enhancement proposal 9 UTBB FDSOI MOSFET structure (N-type): Back gate is used for V T modulation (FBB, RBB) R g = 1 N f R b = R bsh 1 P bgate R contact + R sh. W f 3 L + R int. where W f and P bgate are gate finger width and back gate access strap perimeter 1 L W f Small-signal equivalent circuit in common source configuration: Extrinsic components are gate resistance and back gate resistance (both are layout dependent) Included in UTSOI2 compact model

10 MOSFET Characterization 10 2-port test structures (grounded Source and Bulk) with Mult > 1 and Nf>1 SOLT calibration executed AC S-parameters measurements coupled with DC IV characterization ground-signal-ground probes are used Up to Frequency = 110GHz From:??? De-embedding using OPEN-SHORT

11 Series resistances extraction 11 Extraction of external series resistances is possible using the SHORT structure SHORT equivalent small signal circuit resistances are optimized using HDW Series DC resistors are encountered during DC measurements (in green) Series HF resistors are encountered during DC & S-parameters measurements (in blue) Shunt high capacitances (C=1F) are used to short the DC resistors in high frequency simulations Id and Ig currents optimization Equivalent small signal circuit of SHORT

12 DC/AC MOSFET parameters extraction An estimation of the thermal resistance and capacitance is used 2. Main physical effects parameters extracted using long and wide MOSFET 3. Then length and width scaling calibration is done using relevant geometries 4. After de-embedding, S-parameters are transformed into Y-parameters Small signal component Extraction [Ref1] Gate resistance (R g ) R g = Re Y 11 Im Y 11 2 Gate-Drain capacitance (C gd ) C gd = Im(Y 12) ω Trans-conductance g m g m = Re Y 21 Y 12 Gate-Source+Bulk capacitance (C gs +C gb ) C gs + C gb = Im Y 11 ω C gd Output conductance (g ds ) g ds = Re Y 22 + Y 12 Drain-Source+Bulk capacitance (C ds +C bd ) C ds + C bd = Im(Y 22) C ω gd

13 Model validation versus measurements (NMOS)

14 Normalization 14 Drain current is normalized using the formulation initially used by EPFL for EKV model [5]: I C = inversion coefficient = I d I sp Isp (specific current) can be obtained using g m I dsat U T versus I d plot at V ds = 1V where U T is the thermal voltage Weak inversion: I C < 0.1 Moderate inversion: 0.1 < I C < 10 V ds = 1V Strong inversion: 10 < I C < 1000 [5] M. Bucher et al, An Efficient Parameter Extraction Methodology for the EKV MOST Model, Proceedings of the 1996 IEEE International Conference on Microelectronic Test Structures, Vol. 9, March 1996 Isp

15 Basic MOSFET characteristics DC normalized I d, g m, g m2 versus V g L=30nm Wf=0.3μm L=30nm Wf=1μm L=30nm Wf=2μm 15 I d V g g m V g g m V g Good agreement is achieved in weak, moderate and strong inversion.

16 Basic MOSFET characteristics g m DC versus AC 16 L=30nm Wf=0.3μm L=30nm Wf=1μm L=30nm Wf=2μm V d = 0.3V and 1V g mdc V g V d = 0.3V and 1V g mac V g g mdc and g mac characteristics might be simultaneously used: to discriminate and check R th estimated value To discriminate and check external series resistances encountered in DC and High frequency

17 Basic MOSFET characteristics DC normalized I d and g ds versus V d 17 L=30nm Wf=0.3μm L=30nm Wf=1μm L=30nm Wf=2μm V g = 0V 1V I d V d V g = 0V 1V g ds V d Good matching in linear and saturation regimes Dependence on gate finger width W f is reproduced

18 V d = 0V, 0.3V and 1V Basic MOSFET characteristics C gg, C gd, C gs +C gb (10GHz) L=30nm Wf=0.3μm L=30nm Wf=1μm L=30nm Wf=2μm 18 C gg V g V d = 0V, 0.3V and 1V C gd V g V d = 0V, 0.3V and 1V C gs + C gb V g Good agreement for all bias conditions (from linear to saturation) thanks to UTSOI2 charge and capacitance model

19 f T figure of merit 19 Transit or Cut-off frequency where small-signal current gain H21 drops to unity (amplifier usage) L=30nm Wf=2μm f T = g m 2π C gs +C gb + C gd = g m 2π C gg Early silicon results showed a peak f T of more than 300 GHz Vg F T Peak f T obtained for moderate inversion f T FOM is not sufficient for RF applications f T versus I dnorm = I C = I d at V I d = 1V sp

20 f max figure of merit 20 Frequency at which Mason power gain U drops to unity f max f T 4R g g ds +2πF T C gd f max reproduced thanks to acceptable parasitic extraction f max shape is mainly captured using suitable Gate resistance R g A simple back gate access strap perimeter dependent R b resistance added to capture behavior up to 80GHz (curves spread) L=30nm Wf=2μm UTSOI2 + negligible R g R g F= [10GHz 80GHz] UTSOI2 + R g Rb UTSOI2 + R g + R b

21 V d = 0.3V and 1V f T and f max for: 10, 20, 30, 40, 50, 70 and 80 GHz L=30nm Wf=0.3μm L=30nm Wf=1μm L=30nm Wf=2μm 21 f T I C V d = 0.3V and 1V f max I C Good agreement achieved using external R g and R b resistances

22 V d = 0V 1V F = 1GHz 90GHz (10GHz step) g m /I d & g m.f T / I d figure of merit L=30nm Wf=0.3μm L=30nm Wf=1μm L=30nm Wf=2μm 22 g m I d I C V d = 0V 1V F = 1GHz 90GHz (10GHz step) g m I d F T I C g m I d f T is a figure of merit proposed in [6] for tradeoff between speed and power efficiency Good agreement achieved from 0.1GHz up to 90GHz [6] A. Shameli and P. Heydari, Ultra-Low Power RFIC Design Using Moderately Inverted MOSFETs: An Analytical/Experimental Study, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006, pp , 2006.

23 Conclusion 23 FDSOI technology has predispositions for high frequency applications; therefore high frequency modeling challenges must be addressed The tradeoff between speed and power efficiency is obtained in moderate inversion regime, where f T and f max are optimal The simple proposed extension of UTSOI2 model was sufficient to capture high frequency behavior up to 80GHz Substrate resistance R b has been found to have very low impact on RF behavior (C bd ) RF characterization and modeling methodology validated on Bulk CMOS devices also applies well to FDSOI devices; the methodology is now valid to support RF design community needs Future work: Extend AC signal model validation Noise and large signal validation of the model

24 Acknowledgements 24 Clément Charbuillet Michel Buczko Sebastien Jan Frederic Dauge Yannick Mourier Michel Minondo Hervé Jaouen

25 Additional References 25 [Ref1] W. Grabinski, B. Nauwelaers and D. Schreurs «Transistor Level Modeling for Analog/RF IC Design», Springer, [Ref2] Franck Ellinger «Radio Frequency Integrated Circuits and Technologies» second edition, Springer, [Ref3] B. Dormieu, P. Scheer, C. Charbuillet, H. Jaouen, F. Danneville Revisited RF Compact Model of Gate Resistance Suitable for High-K/Metal Gate Technology, IEEE TED 2013 [Ref4] «Surface potential based model of ultra-thin fully depleted SOI MOSFET for IC simulations,» O. Rozeau, M.-A. Jaud, T. Poiroux and M. Benosman, 2011 IEEE International SOI conference, Tempe Arizona, USA, October [Ref5] «UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs,» Poiroux, T.; Rozeau, O.; Martinie, S.; Scheer, P.; Puget, S.; Jaud, M.A.; El Ghouli, S.; Barbe, J.C.; Juge, A.; Faynot, O., Electron Devices Meeting (IEDM), 2013 IEEE International, vol., no., pp ,12.4.4, 9-11 Dec [Ref6] «UTBB FD-SOI: A process/design symbiosis for breakthrough energy-efficiency,» Magarshack, Philippe; Flatresse, Philippe; Cesana, Giorgio, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, vol., no., pp.952,957, March 2013