An HF SSB Software Defined Radio

Transcription

1 By Dick Benson, WG (v.) An HF SSB Softwre Defined Rdio ntroduction n the Jnury 948 issue of ST, SSB ws herlded s being the most significnt development tht hs ever occurred in mteur rdiotelephony.... We re now on the brink of nother step in technology tht will eventully chnge how HF nd ll high performnce rdios will be constructed. This technology will ultimtely led to lower cost, improved performnce nd vstly incresed flexibility. One of the most remrkble components to evolve over the pst decde is the Field Progrmmble Gte Arry or FPGA. The FPGA is uniquely suited for high speed digitl signl processing (RF dt rtes) due to its sclble nd prllel hrdwre resources. As mind bending s the FPGA is, it is mde even more remrkble by the ltest design tools tht llows high fidelity simultion of the system nd then utomticlly genertes the VHDL code to progrm the device. An engineer s drem, come true! The sme sitution holds for the Digitl Signl Processing chips. Tools exist tht do both system simultion nd utomtic code genertion. And s if ll tht ws not enough, the design environment turns into grphicl user interfce to control, monitor, nd djust prmeters on your cretion while it is running! Yes, it seems too good to be true, but it is rel. This note describes how these tools nd components re used to crete n HF SSB rdio. Some Definitions A Softwre Defined Rdio is rdio tht is mde from generl purpose reconfigurble / progrmmble components. t is the progrmming of these components tht define its opertionl chrcteristics. For instnce bndwidth nd modultion (ssb, cw, m, fsk, psk, qpsk etc) re completely determined by how the reconfigurble prts re progrmmed, not by hrdwre filters, mixers, mplifiers, nd other trditionl components. (chip) is computing device tht is optimized for the processing of dt strems (signls). The holy gril of signl processing is the multiply-dd opertion since virtully ll lgorithms need myrid of these computtions. n conjunction with fst hrdwre multiplier nd ccumultor, the memory ddressing is computed in the sme instruction cycle using memory ddress genertion hrdwre such tht two vlues (coefficient nd dt) cn be fetched from fst memory to feed the multiplier. This llows Figure Experimentl setup of the Softwre Defined Rdio. Softwre on the host notebook computer genertes the code required to progrm the nd FPGA hrdwre the Lyr Signl Processing SignlMster development bord on its edge in the bckground. After the code is downloded to the hrdwre, the notebook lso serves s the rdio s user interfce. The receiver RF pre-mp, trnsmitter power-mp, nti lis filter, nd T/R switching re on the copper cld bord behind nd to the left of the microphone. the multiply-dd opertion to be done in one mchine cycle. Although it is true tht generl purpose processor (e.g. ntel Pentium) cn in fct computtionlly outpce the, the power consumption but its cost is commensurte with this performnce. The FPGA is re-progrmmble logic device tht cn contin the equivlent of millions of gtes. On bord these remrkble devices reside RAM, 8x8 prllel multipliers, registers, look up tbles, nd the equivlent of generl purpose logic. The key dvntge the FPGA enjoys over the is its bility to utilize the hrdwre in prllel fshion. n other words, one is not constrined to process dt strems through one (or t most 4) rithmetic elements, but it literlly my hve thousnds of elements to perform the computtions in prllel. This llows the FPGA to process dt strems tht re running in the s of MHz. Until recently, the downside of the FPGA ws its difficulty to write the required code to progrm it. t required knowledge of Hrdwre Descriptor Lnguge such s Verilog or VHDL. This hs now ll chnged with the introduction nd evolution of the Xilinx System Genertor for TM.

2 Figure Block Digrm. The rdio rchitecture cn be described with only mjor components. The color code is s follows: blck : continuous time signls red : the fstest smpling rte, 64 MSPS green : / dt t 64 MSPS/496 rte blue : udio dt t 64 MSPS/89 (7.85 khz) Rdio Architecture Figure shows the utter simplicity of this rdio! True, millions of trnsistors re required, but thnks to modern semiconductor mnufcturing techniques, the cost per trnsistor is less thn the cost of turn wire loop serving s n inductor! Who would hve thought tht to ever be possible? As cn be seen, the rdio uses multiple smpling rtes for the signl processing nd the high speed work is done in the FPGA while the udio bndwidth work is done in the. A rther perfect division of lbor, with ech component doing wht mkes the most sense. Wever s Third Method Prior to 956 there were two primry methods known for generting SSB signls: phsing nd filtering. Ech of these methods hd its pro s nd con s. The phsing method required circuit tht generted 9 degree phse shift cross the udio frequency rnge (- Hz). Devitions from 9 degrees led to reduction in the unwnted sidebnd suppression. The filter method eventully won out with both crystl nd mechnicl filters being used. n 956, Donld Wever cme up with third method tht pprently hd been overlooked. t required filters, nd phse shifts, but the phse shifts were fixed with respect to frequency nd the filters were low-pss, not bnd-pss. However, the technology of the time ws not relly up to the tsk, nd the filtering pproch worked well, so the new Third Method ws not dopted. mplementing Wever s technique in hrdwre is quite esy! The min issues of dc offset, nd filter gin-phse mtch tht prevented the ide from being dopted in 956, simply do not exist. Figure shows block digrm, creted with the Mthworks Simulink environment, of simple SSB genertor using Wever s scheme. To provide recognizble shpe to the spectrum, weighted sum of sine wves is used s the udio input. The first trnsltion nd filtering opertion centers the desired sidebnd round DC nd removes the other sidebnd. Then it is simple mtter to up convert this complex ( & ) signl to the desired RF frequency. The output of the finl two mixers is either summed or differenced to get the upper or lower sidebnd. The spectr shown in Figure tell the story.

3 Figure Wever s Third Method. A simple SSB genertor mde from Simulink blocks is useful to understnd the spectrl shifting, filtering, nd up trnsltion to RF. Filter Design The previous simplified exmple shifted the upper sidebnd to pproximtely 5 khz. The ctul rdio will need to go fr higher, lmost MHz. To ccomplish this, multi-stge, multi-rte filtering is required. The Mthworks hs superior set of filter design tools tht mke this design job quite esy. To cover the MHz HF spectrum, smpling clock of greter thn x MHz is needed. The on-bord 64 MHz clock stisfies this requirement. The desired udio rte is round 8 Hz, nd 64e6/89 = 78.5 Hz is good fit here. Focusing on the receiver for moment, the first filter will be Cscded ntegrtor Comb (CC) filter since it mps very well to FPGA hrdwre. The remining filters will be FR decimtors or interpoltors for the trnsmit chin. The filter p-rocessing is s follows: CC (D=64), FR_ (D=8), FR_ (D=8), FR_ (D=) for n overll smple rte reduction of 64*8*8*=89. Figure 4 shows the overll frequency response of the multi stge filter. The sme filter coefficients re used for trnsmit s well. The lst filter (D=) determines the ultimte frequency response chrcteristics. t therefore borders on being trivil to chnge the filter chrcteristics since they re ll defined by softwre. Overll Filter Response in db Hertz x 4 Figure 4 Filter Frequency Response

4 Simulink HF SSB Trnsceiver Fo Rx/Tx Frequency () Gin 8.4 Freq (MHz) RF_in RF nput Spectrum RF input Red = 64MHz Cyn = 64MHz/496 Drk Green = 64MHz/89 Fin hf_lo_sin hf_lo_cos LSB_sel Locl Oscilltors lo_sin lo_cos _out Rx Digitl Down Converter (c) _in Audio_out SSB Demodultor Rx_out AF Spectrum lo_sin lo_cos RF_out AF nput Sidebnd Select () _out Audio_in SSB Modultor (c) _in Tx Digitl Up Converter Color Trck Tx RF Spectrum Tx_out Figure 4 Hrdwre ndependent Model (Top Level) Evolving the Design The bsics re now lid out, nd more detil now needs to be dded. The first step in this process is to crete hrdwre independent model. This is esily done by using Simulink s Block Librry. Figure 4 shows the generl signl flow in the rdio. The locl oscilltors re shred by both receive nd trnsmit processing chins. The receiver consists of digitl down converter followed by finl filter-demodultor stge. The trnsmitter is simply the receiver blocks turned round with interpolting rther thn decimting filters! Fin LSB_sel Fbfo BFO Freq Figure 5 Locl Oscilltors -Km sin Vin cos LO_dds sin Vin cos BFO_dds hf_lo_sin hf_lo_cos 4 Once stisfctory simultion results hve been obtined indicting the generl signl flow nd filtering re correct, it is time to split the model between the FPGA nd the. For this design, it is quite strightforwrd to prtition the functions. The light green blocks will be implemented in the chip while the light red blocks will be implemented in the Xilinx FPGA. And yes, this is still the Wever scheme, but using modern terminology (digitl down / up converters). 4 Audio_in -Km SSB Modultor Product Product Figure 6 SSB Modultor Re (c) m Rel-mg to Complex x[n/] FR nterpoltion by (c) _out (c) _in 4 x[n] FR Decimtion (c) e(u) m(u) Rel-mg Mix Mix SSB DEMOD Gin Audio_out Figure 7 SSB Demodultor

5 lo_sin lo_cos RF_in Re m iqc (c) Product (c) CC Decimtor D=64 Digitl Down Converter (c) (c) (c) x[8n] x[8n] FR_ Decimtion by FR_ Decimtion by 8 _out Figure 8 Rx Digitl Down Converter _in Digitl Up Converter (c) x[n/8] (c) x[n/8] (c) CC nterpoltor (c) e(u) FR nterpoltion FR nterpoltion m(u) Rel-mg lo_sin lo_cos Mixer Mixer RF_out Figure 9 Tx Digitl Up Converter The FPGA Design The Xilinx System Genertor for is stte-of-the-rt tool tht provides design entry, dt pth definition, bit / cycle true simultions, test bench genertion, hrdwre cosimultion, VHDL code genertion, nd more! The key to the tool is tht the Xilinx system Genertor Bock Librry mps to Xilinx LogiCores which re highly optimized implementtions of typicl functions (filters, direct digitl synthesizer, FFT, etc.). One merely picks blocks from the librry, defines the prmeters (e.g. word size, binry point position), nd hooks them together just like stndrd Simulink blocks. Gtewys re used to go between the stndrd Simulink precision nd the fixed point representtion used by the Xilinx blocks. Referring to figure, there re blocks tht re specific to the Lyr SignlMster hrdwre nd these re mrked with n LSP. The ADC (red) represents the 64 MSPS converter, while the DAC (red) is the 64 MSPS DAC. The gte_ gtewy is bit register tht the cn write to chnge the frequency of the Direct Digitl Synthesizer in the RF Locl Oscilltor block. The downconverted strem from the Rx_Mix_Filters is fed to bit gtewy tht interfces to SSB Rx/Tx Prt : FPGA Frequency Trnsltor fpt dbl center freq Gin Frequency (MHz) nput Spectrum LO_cos out UFix D (c) nrx_ D Fix_4_ RF_dc To demux RX Output RF input Fix -C- D Frequency gte_.5-9 MHz, Fs=64MSPS ADC Fix_4_ Freq_in Fix_4_ LO_cos RF Locl Oscilltor _muxd D Fix RX_Mix_Filters UFix LO_cos RF_DAC in xldsmp z - Down Smple D DAC UFix Codec Sync xmit_rf_out DAC dc sim RF in/out Output Spectrum System Genertor LSP FPGA Genertor for Xmit From TX_Filters_Mix :O Freq 6.4e+7 Fs_ADC&DAC Color Trck Figure FPGA top Level

6 the T. On the trnsmit side, nother gtewy ( from ) tkes dt form the T nd drives the input of the TX_Filters_Mix block. This digrm is the top level nd further detil is contined within ech block s shown in Figures - to the right. Freq Fix xlcst force Reinterpret UFix xlusmp 89 Up Smple UFix k = Constnt Bool Fix_4_ dt sin xldds Fix_4_ we cos DDS z - Fix_4_ hf_lo_sin Dely z - Fix_4_ hf_lo_cos Dely Once the dt pths nd processing is defined, simultion revels if the design meets the objectives of dynmic rnge, nd spurious responses introduced by the fixed point implementtion. f not, chnces re tht more bits need to be used in the filter coefficients nd/or dt pths. Once the objectives re met, click of the mouse genertes the circ files of VHDL required to implement the design. t is then mtter of using the norml Xilinx tool flow (Figure 4) of synthesis, plce nd rout, nd finlly to bitstrem genertion to progrm the FPPGA. This process requires virtully no user intervention nd bit-strem cn be ccomplished with mouse click. Figure- DDS HF Locl Oscilltor :O.56e+4 dt rte Fix_6_5 Fix_6_5 Fix_6_4 Fix_6_5 Fix_4_ xlmult z - (b) b UFix Out Fix_6_5 Fix_6_4 Fix_6_5 M _out d64_cc d8_ mux Fix_6_5 d8_ Fix_4_ xlmult b z - (b) to mke b strem LO_cos M : O.5e+5 Fix_4_ Freq RX_ADC : O e+6 Freq Figure- Rx Down-Smpling Filters xlmult b z - (b) Fix_6_5 Fix Fix n Fix Tx_ demux for. fmt Fix Fix i8_ Fix Fix i8_ Fix Fix i64_cc M xlmult b z - (b) Fix_6_5 xlddsub b z -+b TX sum Fix_6_5 xlconvert z -cst Convert Fix n Out FixUFix UFix RF_out Fix_4_ M Fix_4_ LO_cos Figure- Tx Up-Smpling Filters Figure-4 Xilinx SE 5.i One of the more interesting reports tht cn be generted is floor-pln of the FPGA design. This tool (Figure 5) provides grphicl representtion of the FPGA resources used by ech mjor component (DDS, FR filter etc). As cn be seen, virtully ll (95%) of the FPGA fbric is used by the digitl up/down converter. The design did not initilly fit in the xcv prt. Bits were trimmed from the trnsmit dt pths nd rounding / sturtion were bndoned. The simultion results indicted tht this would not cuse ny severe problems if the proper udio signl conditioning were done in the chip portion of the design. The bility to esily mke these trdeoffs is key ttribute of the design flow. Much more cn be done to shrink the design llowing the use of lower cost FPGA, but for this exmple, there is little point. Figure-5 Xilinx Floor Plnner.

7 SSB Rx/Tx Prt : T Filters + Modultor / Demodultor nterfce to - from FPGA Digitl Frequency Trnsltor [64x].7 AF Out [64x] [64x] Test / Rx Out [64x] [64x] [64x] CS48 Plybck [64x] [64x] Audio Out [64x] AF Gin Audio Processing Audio_in _to_fpga BFO_out Tx cmprs Tx SSB Modultor int [64x] (c) [64x] SMC6xx Asynchonous nterfce SMC6xx Asynchronous Bus nterfce int [64x] [64x] _from_fpga BFO_in Audio_out Tx Smeter cmprs Rx SSB Demodultor [64x] [64x] Time Audio Out Constnt Constnt LSB== Tx== LED lsb/usb Freq Out Freq FPGA Register FPGA Freq Control 7.74 Freq Level Profiler 6.8 % CPU Loding CMD File Genertor CS48_cntl Color Trck Corse F Fine F The Design Figure 6 shows the top level of the rdio prtition which is implemented with the T C67 chip on the Lyr SignlMster development hrdwre. Like the preceding models, the model is hierrchicl. The Audio Processing block is shown in Figure 7. The left most mnul switch selects either the udio ADC in the Mic. nput block, or, two udio sine genertors tht re summed together to mke built in -tone genertor. Reverbertion is not used with the two tone test, but if the ADC is selected, the output of the Reverbertion module is routed to the block output. The detils of the Reverbertion module re shown in Figure 8. For processor efficiency, most of the signl processing is done with frmes of dt. On the block digrm, frme bsed signls show s wide line. However, feedbck systems such s the reverb, need to be implemented on smple by smple bsis, therefore there is n un-buffer nd buffer combintion to go to smple bsed nd then bck to frme bsed processing. Figure-6 Prtition in T C67 boolen Select Mic. Select Two Tone Figure-7 Audio Processing n Audio / Test [64x] [64x] Figure-8 Reverbertion Module BFO u Unbuffer (c) [64x] if(u ~=) f else ction ction else { } Out Two Tone if { } out Mic nput [64x].6 Feedbck Gin z - nteger Dely [64x] Merge [64x] +j*eps Constnt Merge (c) [64x] [64x] [64x] Buffer n reverb Out [64x]. (c) [64x] AF Out [64x] [64x] [64x] [64x] [64x] Audio Out [64x] [64x] BFO_out Out The trnsmit chin modultor is shown in Figure 9. The min subsystem is only enbled during trnsmit to lower the processing lod. Figure hs the modultor nd compressor which rther thn being in the udio chin, is pplied to the dt strem from the modultor block output. [64x] Audio (c) [64x] Out Audio_in (c) [64x] int [64x] BFO in Out [64x] (c) _to_fpga +j*eps Out lsb 4 mpx to bit word Modultor + Compressor Constnt cmprs Downsmple Repet x Tx Repet Figure-9 Tx SSB top Level Modultor

8 Audio [64x] [64x] [64x] Product [64x] Enble 64 MSPS in the Lyr SignlMsterhrdwre. Also, some numeric displys re shown mesuring signl levels. BFO (c) [64x] [64x] Re(u) [64x] m(u) Rel-mg Rel-mg to Complex (c) [64x] Audio out Re [64x] (c) [64x] (c) [64x] Out m x[n/] in [64x] Compress Out FR Compressor nterpoltion by [64x] lsb [64x] - [64x] [64x] Gin [64x] Product [64x] z -9 (c) [64x] [64x] nteger Dely (c) [64x] [64x] [64x] Enble Out Product Buffer DF FR (c) [64x] (c) [64x] [64x] [64x] u [64x] mx log z - 64 /6 () n Abs Gin Smeter Digitl Filter Unbuffer MinMx Mth nteger Dely Downsmple Dt Type Conversion Gin Gin5 Function.5 Figure- Tx SSB Modultor, Filter nd Compressor Constnt.9995 Gin Constnt 9.4 RF gin Sturtion RF AGC in (c) [64x] [64x] [64x] Gin z -9 (c) [64x] nteger Dely R DFT (c) [64x] [64x] 5 u Abs Digitl Filter [64x] Unbuffer Constnt Figure- Tx Compressor Referring to Figure 9, the output of the Compressor feeds switch tht only psses the strem on to the subsequent blocks during trnsmit. The finl block in figure 9 converts the complex precision dt strem into bit fixed point word (6 bits for nd 6 bits for ) to be pssed to the FPGA by the Asynchronous nterfce block in Figure 6. mx MinMx z - nteger Dely.999 Gin Buffer 64 [64x] Downsmple [64x] Product Gin (c) [64x] () Compress Dt Type Conversion Audio out Figure- Rx AGC The normlized level from the AGC subsystem is then fed to the SSB demodultor block long with the BFO signl from the (complex) udio oscilltor tht ws in the Tx SSB Modultor block (Figure 9). in BFOin (c) [64x] Re(u) m(u) Rel-mg (c) [64x] Re(u) m(u) Rel-mg [64x] [64x] [64x] [64x] [64x] [64x] Product Product [64x] [64x] [64x] Ded Zone - m [64x] Gin4 [64x] [64x] [64x] 9 RFA RFA [64x] paudio (c) [64x] BFO_in Out (c) [64x] [64x] in [64x] paudio Audio_out BFOin SSB demod Figure- Rx SSB Demodultor The output of the demodultor (Figure ) forms the Audio Out signl in Figure 9. _from_fpga 5 cmprs 4 Tx int [64x] nout bit demux (c) [64x] x[n] FR Decimtion NOT Logicl Opertor (c) [64x] n Figure- Rx SSB Demodultor The first block in Figure converts the bit fixed point combined signl from the FPGA to complex () precision flot which drives the downsmple-by- FR filter. This filter determines the informtion bndwidth of the receiver. ts up-smple-by- counterprt in the trnsmitter does the sme thing. To switch between vrious informtion filters, one need only to crete them using the filter design tools, nd plce the filters in enbled subsystems in mnner similr to the mechnism used to select between the mic nd the two-tone source. Smeter RF AGC AGC AGC ADC Gin nd more The FR filter output drives the AGC subsystem which is shown in Figure. The AGC is similr to the trnsmit compressor in tht it is feed forwrd scheme rther thn feedbck scheme. Feed forwrd is difficult in nlog hrdwre, but esy with. Note tht one of the pths (RF AGC) lso drives progrmmble gin mplifier before the Smeter To control tuning frequency, trnsmit/receive, nd sidebnd selection, simple user interfce ws mde (Figure 6) from switches nd sliders. The light bulb icon turns on some LEDs on the SignlMster during trnsmit. A wire run from the LED driver is the electricl Trnsmit / Receive signl for the externl (nlog) hrdwre. Freq Freq Fbfo Constnt - m lsb/usb Zero-Order Hold 64 Downsmple Figure-4 FPGA DDS Frequency Control The processing of these control signls is shown in Figure 4. The bit word to set the FPGA Direct Digitl Synthesizer frequency is computed in this block. Notice tht the DDS frequency is offset from the tuned frequency by n mount tht is equl to the BFO frequency, nd, this frequency shift is up or down depending on the sidebnd select mode. This plces the tuned frequency to the point where there would be crrier in non-suppressed crrier system. e6 SMC6xx Custom Register FPGA DDS Freq Out

9 Automtic Code Genertion nd Control Now the good prt! The rel-time code to implement the previous block digrms, downlod it, nd run it, is mouse click wy! A key feture of the Simulink environment is n (optionl) fully integrted code genertion engine option clled the Rel Time Workshop. The process tht genertes the C code cn be modified to support vriety of trget hrdwre. A pre-pckged trget exists for the Lyr SignlMster mking it remrkbly esy to get up nd running. Not line of code ws mnully written. f tht were not impressive enough, the block digrm now becomes the user interfce to control the rdio! The switches nd sliders on the block digrm chnge prmeters (T/R, frequency, USB/LSB) on the fly while the code is executing in the hrdwre. Plus, the displys (e.g. numericl in Figure ) updte s well. You cn even drop in scopes s in the top level of Figure 6, nd these updte while the code is running s well! Frnkly, it hs to be seen to be pprecited. Ok, How Does it Work? Reports re universlly positive with regrd to the signl qulity of the rdio. n spite of the fct tht the receiver hs no tuned pre-selector, it overlods only on the strongest locl signls. For certin, quntittive mesurements need to be mde, but there is no question tht the rdio works well under rel world conditions. Further Work This design is Work n Progress. Now tht the bsic scheme is functioning, dditions will be firly esy. Notice from Figure 6 tht only 6% of the processor horsepower is being used for the current code. This implies tht x more processing is vilble. On the downside, there hs been pesky intermittent filure which hs been found to be relted to temperture. New hrdwre hs just rrived nd will hopefully cure this ill. Sty tuned, Dick, wqg September, Figure-5 Rel time Scope on Audio Signl Beyond this, prmeters ( e.g.constnts) cn lso be chnged while the code is running to djust reverb level, AGC time constnt, signl limiting etc. Useful Links