Resolver Interface Card "OPC-G1. RES" Product Specifications

Transcription

1 Resolver Interfce Crd "OPC-G1 G1-RES RES" Product Specifictions Suzuk Fctory Design Dept. Dte Nme Approved Drwn Awi/Ueki Checked Y.Kto Y.Kto Drwing No. Fuji Electric Co., Ltd. SI /15

2 1 Overview This product is n optionl resolver interfce crd to be mounted on the FRENIC-MEGA-Position Control Type series of inverters. It hs the following functions: - The resolver interfce - The pulse trin input (5V differentil line driver) - The pulse trin output (5V differentil line driver) This interfce crd llows the inverter to perform vector control of synchronous motor. 2 Specifictions 2.1 Avilble Ports for the Interfce Crd This interfce crd cn be connected to the C-port only, out of three option connection ports (A-, B-, nd C- ports) provided on the FRENIC-MEGA-Position Control Type. Any option crd cnnot be mounted to the B- port, becuse this crd occupies lso its spce. 2.2 Applicble ROM Version Tble 2-1 shows the inverter's ROM version to which the interfce crd is pplicble. Tble 2.1 Applicble ROM Version Inverter Series Type of inverter Inverter cpcity ROM version FRENIC-MEGA- Position Control Type FRN G1 - Q * Up to 220kW G1S11700 or lter * is replcing lphnumeric letters tht represent inverter cpcity, enclosure, power supply voltge, etc. is A or B 2.3 Operting Environment Tble 2-2 shows the environmentl requirements for the inverter equipped with the interfce crd. Tble 2.2 Environmentl Requirements Item Specifictions Remrks Site loction Indoors Surrounding temperture -10 to +50 C Reltive humidity 5 to 95% Atmosphere The inverter must not be exposed to dust, direct sunlight, corrosive or flmmble gses, oil mist, vpor or wter drops. Pollution degree 2 (IEC ) The tmosphere cn contin smll mount of slt. (0.01 mg/cm2 or less per yer) The inverter must not be subjected to brupt chnges in temperture tht will cuse condenstion. Altitude 1,000 m mx. No. SI /15

3 2.4 Interfce Specifictions Resolver interfce specifictions Tble 2.3 shows the resolver interfce crd specifictions. Tble 2.3 Resolver interfce specifictions Resolver interfce Item Applicble Resolver Exciting Input signl Wiring length Red bsolute position detect Velocity detection Fult detection function Type Function Specifictions :TS2620N21E11(TAMAGAWA SEIKI CO.,LTD) :1X-BRX Trnsformtion rtio :0.5±5% Excittion signl terminl REF :[R1],[R2] Signl mplitude :19.8Vp-p±20% (7Vrms±20%) Signl current :65mA mx Signl frequency :10kHz typ, sinusoidl wve Input signl terminl SIN COS Allowble mplitude Input signl frequency 20m mx :[S2],[S4] :[S1],[S3] :9.45Vp-p±27% :1kHz mx Use the twist pir shield cble becuse the blnced circuit is composed. Mechnicl ngle 360 / 12bit Incrementl encoder emultion (1024 pulses/rev) The inverter could be stopped running by detected the mlfunction of the resolver signl (signl loss or signl rise). (The lrm is lso output from the inverter.) Signl loss Signl rise :When Sin signl or Cos signl flls below 6.9Vp-p :When Sin signl or Cos signl exceeds 12.0Vp-p PG interfce specifictions This crd provides pulse trin input function nd pulse trin output (divided frequency) function. Tble 2.4 shows PG specifictions of this crd. Tble 2.4 PG interfce specifictions Item Pulse resolution Mximum response frequency 20 to 3000 P/R 100 khz * 1 Specifictions Applicble PG Pulse output 5V, differentil line driver (Equivlent to 26C31 or 26LS31) The interfce crd hs line receiver (26LS32). Source current: +20 ma (mx.) Sink current: -20 ma (mx.) Mximum wiring length *3 100 m PG power supply +5 VDC ±10%, 200 ma or below *2 *1 Setting rnge : 20 to 3600P/R. *2 Use n externl power supply, when the totl PG current consumption exceeds 200 ma. *3 Use wire with lrger size (see Tble 2.5) or use n externl power supply, when the PG power requirements re not stisfied due to the voltge drop cused by wiring impednce from the PG to the interfce crd. No. SI /15

4 Tble 2.5 Reltionship between Wiring Length nd Applicble Minimum Wire Size PG power requirements Wiring length Up to 20 m Up to 30 m Up to 50 m Up to 75 m Up to 100 m 5 V ±10%, 200 ma AWG24 (0.25 mm 2 ) AWG22 (0.34 mm 2 ) AWG20 (0.50 mm 2 ) AWG18 (0.75 mm 2 ) AWG16 (1.25 mm 2 ) Pulse trin input interfce specifictions Tble 2.6 shows the pulse trin input interfce specifictions of this crd. Tble 2.6 Pulse trin input interfce specifictions Item Specifictions Pulse trin genertor Mximum response frequency Pulse output system Mximum wiring length * khz 5V, differentil line driver (Equivlent to 26C31 or 26LS31) The interfce crd hs line receiver (26LS32). Source current: +20 ma (mx.) Sink current: -20 ma (mx.) 100 m *1 Use wire with lrger size (see Tble 2.5) or use n externl power supply, when the PG power requirements re not stisfied due to the voltge drop cused by wiring impednce from the PG to the interfce crd Pulse trin output interfce specifictions Tble 2.7 lists the pulse trin output interfce specifictions of this crd. Tble 2.7 Pulse trin output Interfce Specifictions Item A pulse trin output B pulse trin output Z pulse trin output Mximum wiring length *1 The interfce crd hs line driver (26LS31). Specifictions The output signls of dividing frequency to refer the resolver or the pulse trin input. (Division rtio : 1, 2, 4, 8, 16, 32, 64, 128) The output signls to refer the resolver or the pulse trin input. (Frequency is not divided.) 20m No. SI /15

5 3 Terminl Functions 3.1 Terminl Alloction Figure 3.1 shows the terminl lloction. FXA Output *FXA FXB *FXB FXZ *FXZ S3 Input (PG or Pulse trin) PO XA *XA XB *XB XZ *XZ S1 S4 S2 R2 R1 Input (Resolver) Figure 3.1 Terminl Alloction 3.2 Terminl Functions Tble 3.1 shows terminl symbols, nmes nd functions of the option terminls on the interfce crd. Tble 3.1 Option Terminls nd Their Specifictions Resolver interfce PG or Pulse trin input Symbol Nme Functions [R1] [R2] [] [S2] [S4] [] [S1] [S3] Excittion signl (EXC) Excittion signl (*EXC) Signl Common Signl input (SIN) Signl input (*SIN) Signl Common Signl input (COS) Signl input (*COS) Output terminl for resolver excittion signl Signl common terminl (Equipotent with [] terminl of the inverter) Input terminl for sin signl from resolver Signl common terminl (Equipotent with [] terminl of the inverter) Input terminl for cos signl from resolver [] Signl Common Signl common terminl (Equipotent with [] terminl of the inverter) [PO] Internl power supply output Power output terminl for the PG +5 VDC -0% to +10%, 200 ma output [XA] A(+) phse pulse input Input terminl for A(+) phse signl *1 [*XA] A(-) phse pulse input Input terminl for A(-) phse signl *1 [XB] B(+) phse pulse input Input terminl for B(+) phse signl *1 [*XB] B(-) phse pulse input Input terminl for B(-) phse signl *1 [XZ] Z(+) phse pulse input Input terminl for Z(+) phse signl *1 [*XZ] Z(-) phse pulse input Input terminl for Z(-) phse signl *1 No. SI /15

6 Pulse trin output Tble 3.1 Option Terminls nd Their Specifictions Symbol Nme Functions [] Signl Common Signl common terminl (Equipotent with [] terminl of the inverter) *2 *3 [FXA] A(+) phse pulse output Output terminl for A(+) phse signl *2 *3 [*FXA] A(-) phse pulse output Output terminl for A(-) phse signl *2 *3 [FXB] B(+) phse pulse output Output terminl for B(+) phse signl *2 *3 [*FXB] B(-) phse pulse output Output terminl for B(-) phse signl *2 *3 [FXZ] Z(+) phse pulse output Output terminl for Z(+) phse signl *2 *3 [*FXZ] Z(-) phse pulse output Output terminl for Z(-) phse signl *1 This interfce crd does not hve wire brek detection function. *2 A/B phse : Selectble dividing rtio by hrdwre switch. Z phse : Cn not be divided. *3 reference signl is selectble by hrdwre switches. Refer to Chpter 5 Setting. 3.3 Terminl Specifictions Tble 3.2 lists the terminl specifictions. Tble 3.2 Terminl Specifictions Type of terminl block Item Resolver interfce TERM1 Pulse trin output TERM2 PG or Pulse trin input TERM3 Applicble wire size *1 Screw size Strip length of wire end Pitch of terminl block Tightening torque Specifictions SMC 1,5/8-STF-3,81 (socket) MC1,5/8-GF-3,81 (plug) mnufctured by Phoenix Contct SMC 1,5/7-STF-3,81 (socket) MC1,5/7-GF-3,81 (plug) mnufctured by Phoenix Contct SMC 1,5/8-STF-3,81 (socket) MC1,5/8-GF-3,81 (plug) mnufctured by Phoenix Contct AWG24 to AWG16 (0.25 to 1.25 mm 2 ) M2 7 mm 3.81 mm 0.22 to 0.25 N m Plug Socket (Terminl block sketches) *1 Depending upon the wire type nd the number of wires used, the front cover my be lifted by the wires, which impedes norml keypd opertion. In this cse, chnge the wire type or size. *2 When ferrule is used, vinyl-insulted one should be used. *3 The wire end should be inserted into the opening of the terminl block nd secured with the screw. No. SI /15

7 4 Detiled Specifictions 4.1 Function codes Set following "Set vlue" to the function code when using this interfce crd. Function codes Set vlue Defult Rnge Setting No. Nme E01 to Terminl [X1] to [X7], [FWD],[REV] Refer to chpter - 0 to : Red encoder position mnully (RPDC) E07, 4.3 E98, E99 E20 to E24, Terminl [Y1] to [Y4], [Y5A/C], [30A/B/C] - 0 to : Speed vlid (DNZS) 88: Reding encoder position (RPDT) 89: Pole tuning done (PTD) E27 F42 Drive Control Selection to 16 16: Vector control for PMSM with speed sensor nd mgnetic pole position sensor d14 d15 d16 d17 d59 d60 d61 d62 d63 P95 Feedbck Input (Pulse input formt) Feedbck Input (Encoder pulse resolution) Feedbck Input (Pulse count fctor 1) Feedbck Input (Pulse count fctor 2) Commnd (Pulse Rte input) (Pulse input formt) Commnd (Encoder pulse resolution) Commnd (Filter time constnt) Commnd (Pulse count fctor 1) Commnd (Pulse count fctor 2) Mgnetic pole position sensor offset 2 2 2, 4 2: A/B phse with 90 degree phse shift 4: A/B phse with 90 degree phse shift nd U/V/W phse by the mgnetic pole position 0400 (1024 pulse) 0400 (1024 pulse) 0014 to EA60 (20 to pulse) Use the fctory defult. It is hexdeciml number disply. 1 to to 9999 Adjust to be suitble of the correction vlue. 1 to to 9999 Adjust to be suitble of the correction vlue. 0, 1, 2 0 0, 1, 2 0: Pulse trin sign/pulse trin input 1: Forwrd rottion pulse/reverse rottion pulse 2: A/B phse with 90 degree phse shift 0400 (1024 pulse) 0400 (1024 pulse) 0014 to 0E10 (20 to 3600 pulse) Use the fctory defult. It is hexdeciml number disply to to Set it ccording to the response speed s 1 to to 9999 Adjust to be suitble of the correction vlue. 1 to to 9999 Adjust to be suitble of the correction vlue. 0.0 to to 359.9, 999 Adjust the mgnetic pole position before driving synchronous motor. No. SI /15

8 4.2 Protective functions The inverter is stopped nd output by detecting the following bnormlities. Item Disply Specifictions OPC-G1-RES PG Option crd error "PG wire brek lrm" *1 is output, in the following cse. When CPU of OPC-G1-RES drives recklessly When the wire brek between OPC-G1-RES nd the resolver. *2 When the following mlfunctions of the resolver signl is found Loss of signl Degrdtion of signl Loss of trcking PG relted circuit ffected by strong electricl noise. The wire between the pulse genertor (PG) nd the option crd hs been broken. Option communictions error Er. 4 When CPU of OPC-G1-RES drives recklessly. There ws problem with the connection between the option crd nd the inverter. Strong electricl noise. Speed mismtch or excessive speed devition Er. E When the wire brek between OPC-G1-RES nd the resolver. *1 Output dt becomes invlid while outputting the PG wire brek lrm. *2 As for only one disconnection, either of [S1], [S2], [S3] or [S4] error detection cnnot be done ccording to the position under the stop. PG or Er.E comes out while driving. 4.3 Absolute position detection Absolute position detection nd updte method Absolute position detection nd updte condition The interfce crd hs two methods for detecting the bsolute position. Mnul detection: The inverter becomes mnul reding mode, when "57(RPDC : Red Encoder Position Mnully)" is llocted to terminl [X],. The bsolute position is red only once by inputting the RPDC signl. Automtic detection: The inverter becomes n utomtic reding mode, when "57(PRDC)" is not llocted in terminl [X]. Whenever the reding condition consists, reding nd the updte of the bsolute position re done. The bsolute position detection nd the updte re done, when following "Operting conditions" is ll pproved, nd one of "Detecting conditions: " is pproved. Reding method Mnul detection Automtic detection Operting conditions 57(RPDC) is llocted in terminl [X]. 57(PRDC) is not llocted in The driving instruction is not input. terminl [X]. Detecting conditions The inverter output is stop (Terminl Y 00(RUN) = ). The motor is stop (The rottionl speed of the motor is less thn F25: Stop frequency. Terminl Y 70(DNZS) = ). The lrm (filure detection) doesn't occur. Power on OPC-G1-RES ctive setting *1 Output stopping PG wire brek returning Red position detect - commnd input Detecting cycle 1.5 ms Absolute positionl updte condition When the difference of three times is less thn 2.8 in the consecutive detection. *1 Mounting this interfce crd nd setting the prmeter F42=16. No. SI /15

9 4.3.2 Opertion exmple Mnul detection Power on Becuse PG is being disconnected, the speed detection cnnot be done. Output frequency 00 F25: Stop frequency Run commnd (FWD) or (REV) Restrt Inverter driving 00 (RUN) PG wire brek lrm Pole tuning done 89 (PTD) Reding completion Therefter, it reds it t ech PTD= reding commnd input. Reding encoder O N position 88(RPDT) Reding strt 5ms (Min) fter RPDC= Red encoder position mnully 57 (RPDC) Trouble Cost-to-stop O N PTD= fter RPDC= Trouble After it returns, PG wire brek is PTD=. O N Stte of brke Turning on Relese Turning on Relese Turning on *2 Relese Pole tuning done 89 (PTD) Reding encoder position 88 (RPDT) Red encoder position mnully 57 (RPDC) Drive possible 5ms (Min). O N Absolute positionl updte completion Not drive possible Drive possible * Plese turn it off fter completing bsolute position's reding (Rising edge of 88 (RPDT)). The updte of the bsolute position is cnceled when turning it off on the wy. Stte of brke Turning on *1 When the power supply is turned on, the bsolute position is red utomticlly even if bsolute position reding commnd is not input. *2 The motor brke is turned on, red position detect commnd is input fter the motor stops, nd the red sequence processes the position. *3 Red position detect commnd fter the lrm returns whenever PG wire brek lrm is generted nd red the input nd the position. No. SI /15

10 Automtic detection Power on Becuse PG is being disconnected, the speed detection cnnot be done. F25: Stop frequency Output frequency 00 It begins reding below the stop frequency. Restrt Run commnd (FWD) or (REV) Inverter driving 00 (RUN) Trouble Cost-to-stop PG wire brek lrm Trouble Pole tuning done 89 (PTD) Reding completion PTD= Reding encoder position 88 (RPDT) 5ms (Min). Stte of brke Turning on PTD is kept fter returning of PG wire brek. RUN= nd the stop It is reding completion nd PTD=. frequency or less It doesn't red it while the brekdown is occurring. Relese Turning on Relese Turning on Relese No. SI /15

11 5 Setting 5.1 Setting of J1, J2, J3 nd SW1 Set reference signl of the pulse trin output by J1, J2, J3, nd set the rtio of dividing frequency of the circuit of A, B pulse dividing frequency by SW1, before the inverter is powered on. See Tble 5.1, 5.2 nd Figure 5.1, 5.2, 5.3. SW1 Pulse trin output (5V line driver method) Resolver interfce S1/S2/S3/S4 PG or Pulse trin input (5V line driver method) XA/ *XA/ XB/ *XB / XZ/ *XZ A, B, NM J1, J2, J3 XA, XB, XZ A B Z Selectble Divider (1,2,4,8,16,32,64,128) FXA *FXA FXB *FXB FXZ *FXZ Figure 5.1 Pulse trin output circuit outline chrt J1,J2,J3 J1,J2,J3 SW1 Jumper cp Jumper cp XA,XB,XZ A,B,NM XA,XB,XZ A,B,NM When using the pulse trin input When using resolver vlue (Fctory defult) Figure 5.2 Setting switch of division rtio Figure 5.3 Setting of Jumper J1, J2, J3 for reference signl Tble 5.1 Switch (SW1) setting of division rtio SW n: Division rtio 1 (Fctory defult) Invlidity Tble 5.2 The reference signl setting of pulse trin output The reference signl of output J1 J2 J3 Remrks Resolver interfce (Fctory defult) A B NM Fctory defult PG or Pulse trin input XA XB XZ No. SI /15

12 5.2 Wiring between the Interfce Crd nd the Resolver Mke the wiring between interfce crd nd the resolver within 20m by using the twisted shielded pir. To prevent mlfunction due to noise, the wiring should be kept wy from the min circuit wiring of the inverter nd the power wiring of other devices s fr s possible (10cm or more). Signl should not be routed in the sme duct with power wiring. The shielded lyer should be connected to the [] terminl on the resolver interfce crd nd be opened t the Pulse trin genertor or resolver side. A resolver is rotting trnsformer tht produces output voltges on pir of SIN nd COS secondry windings. When n excittion voltge is pplied to the primry winding nd the resolver shft is rotted, mplitudemodulted voltge wveforms pper on the secondry windings, where the excittion voltge cts s crrier for the modultion. [S2]-[S4] must be connected to the phse reltionship to dvnce 90 ginst [S3]-[S1] in the direction of CW t view of the motor drive side. (Figure 5.4) Note: Clockwise directionl rotting direction of the motor is defined with the motor corresponding to the IEC stndrd. Figure 5.4 Exmple of shpe of wves nd direction where resolver is rotted 5.3 Wiring between the Interfce Crd nd the Pulse trin genertor or the PG Wiring between the interfce crd nd Pulse trin genertor or PG should be performed with shielded cble hving length of 100 m or less. The shielded lyer should be connected to the [] terminl on the interfce crd nd be opened t the Pulse trin genertor or PG side. To prevent mlfunction due to noise, the wiring should be kept wy from the min circuit wiring of the inverter nd the power wiring of other devices s fr s possible (10cm or more). The wiring should not be routed in the sme duct. No. SI /15

13 6 Connection Digrm Ⅰ. In cse of using the resolver feedbck only FRENIC-MEGA L1/R U L2/S V L3/T W G U V W MOTOR M YA YB YZ R/D CVERTER Commnd input R1 R2 S2 S4 S1 S3 PO XA *XA XB *XB XZ *XZ R1 R2 S2 S4 S1 S3 Pulse trin output FXA *FXA FXB *FXB FXZ *FXZ 6 FXA,*FXA,FXB,*FXB,FXZ,*FXZ User Controller or Slve Inverter No. SI /15

14 Ⅱ. In cse of using the resolver feedbck nd the ctul speed feedbck from PG Ⅲ. In cse of using the resolver feedbck nd the speed commnd input from user controller FRENIC-MEGA L1/R U L2/S V L3/T W G U V W MOTOR M YA YB YZ R/D CVERTER Commnd input R1 R2 S2 S4 S1 S3 PO XA *XA XB *XB XZ *XZ R1 R2 S2 S4 S1 S3 8 PO,,XA,*XA,XB,*XB,XZ,*XZ User Controller Pulse trin output FXA *FXA FXB *FXB FXZ *FXZ FXA,*FXA,FXB,*FXB,FXZ,*FXZ 6 User Controller or Slve Inverter No. SI /15

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