DIGITAL I&Q DEMODULATION IN ARRAY PROCESSING: THEORY AND IMPLEMENTATION. David Bernal, Pau Closas, Juan A. Fernández Rubio

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1 DIGITAL I&Q DEMODULATION IN ARRAY PROCESSING: THEORY AND IMPLEMENTATION Dvid Bernl, Pu Closs, Jun A. Fernández Rubio Dept. of Signl Theory nd Communictions, Universitt Politècnic de Ctluny (UPC) Jordi Giron 1-3, Cmpus Nord, Brcelon, Spin. e-mil: ABSTRACT Following the IF smpling strtegy, receiver is ble to overcome inherent limittions of conventionl I&Q demodultors, performing this opertion in completely digitl mnner. In this pper, IF smpling is nlyzed both from theoreticl nd implementtion points of view for the cse of n ntenn rry bsed receiver. Both nlysis re complementry nd provide useful guidelines for the design of Softwre-Defined Rdio receivers. The foundtions of IF smpling strtegy re presented nd the design of ll-digitl I&Q demodultors is covered. Finlly, n ppliction to the design of S-DMB receiver is lso presented nd FPGA implementtion issues discussed. 1. INTRODUCTION In communiction systems, signl is bsebnd modulted in its in phse (I) nd qudrture (Q) components, which re trnsmitted to the Rdio Frequency (RF) spectrum. Receivers re in chrge of demodulting the I&Q components of the received signl. A conventionl I&Q demodultor is shown in Figure 1. Bsiclly, it consists in splitting the received signl nd multiplying ech rm by locl oscilltor (LO) nd its 90 o shifted version. This procedure provides I&Q components fter lowpss filtering nd quntiztion. A number of errors my pper when considering the conventionl pproch shown in Figure 1, minly cused becuse the two rms must be closely mtched for correct demodultion, e.g. gin blnce, qudrture-phse blnce or DC offsets. New trends following the Softwre-Defined Rdio (SDR) philosophy emerged [1, 2], minly thnks to recent dvnces in high-speed nlog-to-digitl converters (ADC), tht llow IF smpling strtegies to be envisged nd the I&Q demodultor to be implemented digitlly, overcoming some of the forementioned errors [3]. Certinly, the nlog components of the RF/IF chin hve to be still crefully designed. However, direct downconversion might be unffordble in highspeed pplictions [4]. This pper presents both theoreticl nd implementtion spects of IF smpling, focusing on the demodultion of I&Q components in completely digitl fshion. Section 2 provides detiled overview of IF smpling strtegies nd the signl processing involved. Although This work hs been finnced by the Spnish/Ctln Science nd Technology Commissions nd FEDER funds from the Europen Commission: TEC /TCM, TEC , TIC nd 2005SGR Figure 1: Conventionl I&Q demodultor. this is n incresingly used technique in SDR receivers [5], this pper presents useful design guidelines. In ddition, the cse of n ntenn rry receiver is ddressed, where the use of Mtched Filters my not be possible due to re constrints in the digitl pltform. The ltter introduces spurious interference, whose impct is discussed from n rry processing point of view. Section 3 is devoted to the implementtion concerns of digitl I&Q demodultion. Finlly, Section 4 presents n ppliction to the design of S-DMB receiver [6] in the S-bnd. The resulting design hs been progrmmed in VHDL code nd implemented in n FPGA device, some results re discussed. 2. DIGITAL I&Q DEMODULATION: THEORY A complex bsebnd signl b(t), tht hs bndwidth of B Hz, is trnsmitted t RF. We define b I (t) nd b Q (t) s the in-phse nd qudrture components of b(t). After downconversion to n Intermedite Frequency, f IF, the signl is bndpss filtered t the receiver to void lising nd to remove high-frequency components. Thus, t the output of the RF chin, the received rel signl consists of the desired IF signl corrupted by noise: x IF (t) = V (t) (2πf IF t + Θ(t)) + ν(t) (1) where is the mplitude of the signl nd ν(t) is dditive noise. V (t) nd Θ(t) re the envelope nd the phse of b(t) = b I (t) + jb Q (t), respectively. The IF signl feds n ADC which smples signl t smpling rte of f s = 1/T s with n b bits of quntiztion. Hence, the smpled version of the IF signl cn be expressed s: x IF [n] = V [n] (2πf IF nt s + Θ[n]) + ν[n] (2)

2 The ide behind digitl IF smpling is to undersmple IF signl in order to obtin replic of the signl t bsebnd, without requiring n dditionl downconversion. This cn be ccomplished by properly choosing f IF nd f s. In generl, the following reltions f IF = kf s ± f s, k Z k 1 4 f s 4B (3) ensure tht non-overlpped lis will pper centered t f s /4. Then, one of the replics t ±f s /4 cn be downconverted to bsebnd using the frequency-shifting property of the Fourier trnsform of signl, i.e., Z(f ± f o ) F z[n]e j2πfonts. With f o = f s /4, it results tht we hve to multiply the IF signl by e j π 2 n to shift the spectrum to the left. Actully, this is strightforwrd opertion since the sequence of cyclic vlues of e j π 2 n re {1, j, 1, j}, where j 2 = 1. As shown in Figure 2, this provides the I nd Q components of the desired signl. Figure 2: After frequency-shift, I&Q components re obtined. Figure 3 shows the spectr of the signls involved in the process. S IF (f) is the spectrl density of the received IF signl in eqution (1). Setting f IF = 3f s /4, i.e. k = 1, nd smpling x IF (t) ccording to eqution (3), we cn observe in Figure 3 tht lising ppers without overlpping in its spectrum SIF dc (f) - reclling tht we hve ssumed bnd-limited signl V [n]. After frequency-shift, we obtin bsebnd replic of the desired signl in S(f) = SIF dc(f f s/4). Notice tht the spectrl density SIF dc (f) shown in Figure 3 is obtined for ny chosen k in (3). Thus, the selection of k is relted to implementtion issues, i.e., to select suitble f IF for the ppliction under design. The restriction on f s to be minimum of twice the Nyquist frequency rises in order to void overlpping in SIF dc(f). After lowpss filtering S(f) one cn decimte the signl up to fctor tht depends on the chosen smpling frequency. Now we consider the cse of n ntenn rry bsed receiver nd provide detiled nlysis of the digitl signl processing involved in the digitl I&Q demodultion procedure. In n N element ntenn rry, ech ntenn element receives different replic of signl in (1), with different gin nd phse depending on the rry geometry nd the Directions Of Arrivl (DOA) [7, 8]. Assuming the nrrowbnd rry ssumption, consisting of tking the time required for the signl to propgte Figure 3: Up-down: spectrl densities of x IF (t), x IF [n] nd x[n] = x IF [n] e j π 2 n. long the rry s much smller thn its inverse bndwidth, phse shift cn be used to describe the propgtion from one ntenn to nother. Hence, it cn be ssumed tht the signl wveform is identicl in ech element of the ntenn rry for given instnt. For the i th ntenn element, the single snpshot signl model for n rbitrry ntenn rry geometry is given by x i IF [n] = g i V [n] (2πf IF nt s + Θ[n] γ i ) + ν i [n] (4) where g i nd γ i re the gin nd phse of the i th ntenn element respectively. ν i [n] is the dditive noise contribution to x i IF [n]. Setting herefter f IF = 3f s /4 for the ske of clrity, we cn express the snpshot model s: ( ) 3π x i IF [n] = g i V [n] 2 n + Θi [n] + ν i [n] (5) where Θ i [n] Θ[n] γ i. The ine cn be expnded s ( ) 3π 2 n + Θi [n] = (6) 2 n ( Θ i [n] ) sin 2 n sin ( Θ i [n] ), with the sequences of cyclic vlues with n: 2 n = 1 2 jn (1 + ( 1) n ) {1, 0, 1, 0} (7) sin 2 n = 1 2 jn+1 (1 ( 1) n ) {0, 1, 0, 1} When multiplying x i IF [n] by the complex exponentil e j π 2 n we obtin tht the I&Q components of the resulting signl re: x i I[n] = g i 2 V [n] ( Θ i [n] ) (1 + ( 1) n ) + ν i I[n] x i Q[n] = g i 2 V [n] sin ( Θ i [n] ) (1 ( 1) n ) + ν i Q[n] (8)

3 being ν I i[n] nd νi I [n] the I&Q components of the resulting noise, ν i [n] = ν i [n] e j π 2 n. Then, the complex bsebnd signl cn be expressed, for ech ntenn element, s x i [n] = x i I[n] + jx i Q[n] (9) [ ] = g i 2 V [n] e jθi [n] + ( 1) n e jθi [n] + ν i [n] = 2 b[n] g i e jγ i + 2 b [n] ( 1) n g i e jγ i + ν i [n] Arrnging signls from elements in row vectors, bsebnd signl in (9) cn be expressed s x[n] = 2 b[n] s d + 2 b [n] ( 1) n s d + n[n] (10) where x[n] = [ x 1 [n],..., x N [n] ] T C N 1 is the signl vector whose rows corresponds to ech ntenn IFsmpled output. s d = [ g 1 e jγ 1,..., g N e jγ N ] T C N 1 is the steering vector of the signl, i.e., row vector contining the response of the elements to the direction of the signl. n(t) = [ ν 1 [n],..., ν N [n] ] T C N 1 represents dditive noise nd ll other disturbing terms. The spectrl contribution of the two signl terms in eqution (10) cn be observed in Figure 3, for the cse of single ntenn s d = 1. The first term corresponds to the desired bsebnd signl, b[n]. The second term, b [n]( 1) n, corresponds to replics centered t ±f s /2, being uncorrelted with b[n]. As shown in Figure 3, x[n] cn be low-pss filtered with two Mtched Filters (I&Q) in order to recover b[n] reducing the contribution of b [n]( 1) n. However, when considering n ntenn rry, it could hppen tht the use of 2 N Mtched Filters in prllel requires n unffordble computtionl t nd tht mtched filtering must be performed t the output of the ntenn rry, fter bemforming. In tht cse, it is seen from eqution (10) tht, in ddition to the desired signl, n interference is cused by b [n]( 1) n being its steering vector the complex conjugte of s d. Prticulrizing for the cse of plnr rry, it is strightforwrd to observe tht the conjugte of s d corresponds to the steering vector of the speculr multipth of b(t). Thus, if bemforming is performed, the computed weights ccording to ny optiml criteri will ttempt to null the direction where the fictitious speculr replic ppers. For the cse of conforml rry, it is not pprent tht s d represents n ctul steering vector. 3. DIGITAL I&Q DEMODULATION: FPGA IMPLEMENTATION Due to the inherent nture of the prllel processing in n ntenn rry receiver, it is pprent tht n FPGA device is proper pltform. In ddition, this pltform provides high degrees of reconfigurbility, following the SDR philosophy. Aprt from voiding the bove cited inherent errors of conventionl pproches, some prticulrities of n ll-digitl I&Q demodultor re of interest when ddressing its implementtion. Compring the digrms of conventionl nd n ll-digitl I&Q demodultor, Figures 1 nd 4 respectively, it rises tht the number of input pins to the digitl pltform hs been reduced to hlf since only the smpled rel IF signl is required - considering tht the digitl pltform is locted fter ADCs in both schemes. Thus, for n N element rry where the ADC smples t f s nd quntizes with n b bits in prllel we would require N n b inputs to perform digitl I&Q demodultion, insted of the 2 N n b delivered in the conventionl pproch. Figure 4: Digitl IF smpling with I&Q demodultion. As could be devised from Figure 2, the implementtion of x IF [n] e j π 2 n is strightforwrd in n FPGA. This process only requires to split into two rms even nd odd smples nd then, multiply ech rm with cyclic sequence of ±1 vlues. The ltter opertion is performed t f s /2, since null-vlues in-between do not need to be multiplied. The proposed rchitecture is shown in Figure 5, long with the operting function t ech point. Actully, the product by ±1 does not requires multiplier, s only the two s complement is performed when multiplying by 1 nd bypss for the cse of 1, sving computtionl resources. Additionlly, one cn decimte ech rm in order to remove the null-vlues. This decimtion will reduce the operting frequency of the FPGA to f s /2, since the block in Figure 5 is locted immeditely fter signl hs been delivered to the FPGA. This cn be performed t the expenses of more lborious designs. This is of interest in high-frequency pplictions, where FPGAs do not operte efficiently, reducing the operting frequency. Figure 5: Implementtion of the e j π 2 n product t the i-th rry element.

4 4. APPLICATION TO THE S-DMB STANDARD The generl concepts presented long Sections 2 nd 3 hve been pplied to the design of n ntenn rry bsed S-DMB receiver under the SDR prdigm for S- bnd opertion. S-DMB is designed to provide stellite nd complementry terrestril on chnnel repeter services for high qulity udio nd multimedi dt for vehiculr, portble nd fixed reception [6]. The min chrcteristics of the system re now presented (those which re of interest for the design of the digitl I&Q demodultor). A stellite trnsmits 30 chnnels multiplexed using CDMA on QPSK modultion t f RF = MHz. The chip rte is r c = MHz, the processing gin 64 nd the trnsmitted signl is filtered by squre root rised ine with roll-off fctor ρ = Due to cquisition nd trcking issues it is desirble to hve t lest 4 smples per chip, for this reson it hs been set f s = 4r c = MHz, n b = 8 bits nd, ccording to eqution (3) with k = 1, f IF = MHz. Notice tht with this design we ensure the condition in eqution (3), B = (1 + ρ) r c 2 4f s. An ntenn rry receiver (N = 40) hs been designed, being the digitl pltform progrmmed in VHDL code nd synthesized into Xilinx FPGA device. Bemforming with ntenn rrys consists of severl ntenns, whose outputs re controlled in phse nd gin, i.e., multiplied by complex weights, in order to chieve gin pttern tht cn be mnipulted electroniclly. Then, ll the weighted signls re combined to obtin single output y[n]. These mentioned weights cn be stcked in complex vlued vector w C N 1 = [w 0,, w N 1 ] T, nd the output signl of the bemformer cn be computed s y[n] = w H x[n]. Weight vector w cn be designed following severl criteri, usully exploiting the sptil filtering provided by ntenn rrys. Since the im of the present pper is to study digitl I&Q demodultion, we now emphsize on this subsystem of the whole receiver presented in [9]. For the ske of clrity, Figure 6 presents the block digrm of the Digitl Bemforming receiver nd the loction of the digitl I&Q demodultion block in it, which consists in bnk of N I&Q demodultors in prllel, similr to tht shown in Figure 5. Notice tht, for this ppliction, the IF smpling strtegy results especilly helpful s it reduces the number of signl input pins to the FPGA from 640 to 320, prt from voiding errors of conventionl I&Q demodultors. The schemtic description of the digitl I&Q demodultor is shown in Figure 7. Other ttempts to implement digitl I&Q demodultors cn be found in the literture [5, 10, 11, 12] for other communiction systems. Nevertheless, the schemtic in Figure 7 hs been designed tking into ccount the S-DMB specifictions. Therefore, there re some remrkble prticulrities w.r.t. the generic block presented in Figure 5. Since we hve considered 4 smples per chip, the implemented block for the S-DMB receiver is composed of four prllel blocks, corresponding to ech smple. Hence, we hve replced the multiplexer nd the two multipliers in Figure 5 by 4 different blocks, being two rms creted for ech component, one for those smples multiplied Figure 6: Digitl Bemforming receiver with digitl I&Q demodultion. Figure 7: Schemtic of the implemented digitl I&Q demodultor. by 1 nd nother for those bypssed, operting t frequency of f s /4. In generl, one cn increse the grnulrity of the design in order to decrese the operting frequency (f fpg ) t the expenses of incresing the consumed re (A fpg ) in the FPGA, since more blocks re required. As rule of thumb, it is considered tht the following holds f fpg A fpg = κ, where κ is constnt, i.e. the product defines n hyperbolic behvior. Tble 1 shows A fpg nd f fpg synthesis results of schemtic in Figure 7 for number of Xilinx FPGA devices. It is remrkble tht not only the number of inputs re reduced, but lso little computtionl t is introduced by the digitl I&Q demodultor w.r.t. direct downconversion strtegies. Technology A fpg (Slices) f fpg (MHz) XC5VLX of XC4VLX of XC3S1600E 37 of XC3S4000L 37 of Tble 1: Synthesis results of the I&Q demodultion block into different Xilinx F P GA technologies.

5 IF smpling hs emerged s fesible nd ppeling strtegy for SDR receivers. In this pper, theoreticl nlysis hs been provided long with design guidelines nd the digitl I&Q demodultor studied for generl ntenn rry receiver. In ddition FPGA implementtion issues were discussed, concluding tht digitl I&Q demodultion reduces the number of inputs to digitl signl processing device nd llows high degrees of downconversion configurtions. A generic block digrm hs been presented, which is strightforwrd implementtion of the digitl I&Q demodultor. As n exmple, it hs been presented n ppliction of those concepts to the design of S-DMB ntenn rry receiver, which hs been progrmmed in VHDL code nd implemented on n FPGA device, vlidting the bove discussions. Figure 8: Correltor output without Mtched Filtering fter digitl I&Q demodultion. Figure 9: Rdition Pttern fter Digitl Bemforming: desired signl t 0 o nd jmmer t 9 o. Finlly, to ssess the correct opertion of the tested digitl demodultion block, some results of the overll S- DMB receiver [9] re presented. In prticulr: synchronism cquisition vi code correltion nd pttern computtion. On the one hnd, Figure 8 shows the correltor output when no mtched filtering is pplied to the digitlly demodulted I&Q components. Notice tht the interference in eqution (10) does not significntly ffect the performnce since the fctor ( 1) n uncorreltes this signl with the generted locl CDMA code. On the other hnd, the Digitl Bemforming technique, nmely the Temporl Reference Bemforming bemformer [8], hs been implemented fter digitl I&Q demodultion. Bsiclly, it uses the well-known wveform structure of trnsmitted pilot signl to point the bem of the ntenn rry. Figure 9 shows the computed bempttern for S-DMB signl t 0 o nd jmmer t 9 o. It is redily seen tht the Digitl Bemforming module is correctly operting, being the jmmer nulled nd the desired signl pointed. 5. CONCLUSIONS REFERENCES [1] J. Mitol, Softwre Rdio Architecture: Object- Oriented Approches to Wireless Systems Engineering, Wiley Interscience, [2] Jeffrey H. Reed, Softwre Rdio: A Modern Approch to Rdio Engineering, Prentice Hll, [3] J. Tsui, Digitl Techniques for Widebnd Receivers, Artech House, Norwood, 2 edition, [4] R. H. Wlden, Anlog-to-Digitl Converter Survey nd Anlysis, IEEE J. Select. Ares Commun., vol. 17, no. 4, pp , April [5] H. Smueli nd B. C. Wong, A VLSI Architecture for High Speed All-Digitl Qudrture Modultor nd Demodultor for Digitl Rdio Appliction, IEEE J. Select. Ares Commun., vol. 53, no. 8, pp , October [6] ITU-R BO : Systems for digitl stellite brodcsting to vehiculr, portble nd fixed receivers in the bnds llocted to BSS (sound) in the frequency rnge MHz, Tech. Rep., Interntionl Telecommunictions Union - Rdiocommunictions (ITU-R), [7] Robert A. Monzingo nd Thoms W. Miller, Introduction to Adptive Arrys, John Wiley & Sons, [8] Hrry L. Vn Trees, Optimum Arry Processing. Detection, Estimtion nd Modultion Theory, Prt IV, Wiley Interscience, [9] O. Lücke, A. Pellon, P. Closs, nd J. A. Fernández- Rubio, Cost-optimised ctive receive rry ntenn for mobile stellite terminls, in IST Mobile Communictions Summit 2007, Budpest, Hungry, July [10] B.E. Priynto, C.L. Lw, nd Y.L. Gun, Design & implementtion of ll digitl I-Q modultor nd demodultor for high speed WLAN in FPGA, in Proceedings of the IEEE Pcific Rim Conference on Communictions, Computers nd signl Processing, PACRIM 2003, August 2003, vol. 2, pp [11] C.C. Jong, Y.Y.H. Lm, nd L.S. Ng, FPGA implementtion of digitl IQ demodultor using VHDL, in Proceedings of the 7th Interntionl Workshop on Field-Progrmmble Logic nd Applictions, FPL 1997, pp [12] S.S Abeyseker nd C. Chroensk, FPGA implementtion of Σ rchitecture bsed digitl IF stge for softwre rdio, in Proceedings of the 15th Annul IEEE Interntionl, ASIC/SOC Conference, 2002, September 2002, pp