A New Stochastic Inner Product Core Design for Digital FIR Filters

Transcription

1 MATEC Web of Conferences, (7) DOI:./ mtecconf/7 CSCC 7 A New Stochstic Inner Product Core Design for Digitl FIR Filters Ming Ming Wong,, M. L. Dennis Wong, Cishen Zhng, nd Ismt Hijzin Fculty of Engineering, Computing nd Science, Swinburne University of Technology, Srwk Cmpus, Mlysi. Heriot Wtt University Mlysi, Wilyh Persekutun Putrjy, Mlysi. School of Softwre nd Electricl Engineeing, Swinburne University of Technology, Hwthorn VIC, Austrli. Abstrct. Stochstic computing (SC) is computtionl technique with computtionl opertions governed by probbility insted of rithmetic rules. It recently found promising pplictions in digitl nd imge processing res nd ttrcted ttentions of reserchers. In this pper, new stochstic inner product (multiply nd ccumulte) core with n improved scling scheme is presented for improving the ccurcy nd fult tolernce performnce of SC bsed finite impulse response (FIR) digitl filters. The proposed inner product core is designed using tree structured multiplexers which is cpble of reducing the criticl pth nd fult propgtion in the stochstic circuitry. The designed inner product core cn led to construction of SC bsed light weight nd multiplierless FIR digitl filters. As result, n SC bsed FIR digitl FIR filter is implemented on Alter Cyclone V FPGA which opertes on stochstic sequences of -bits length (8-bits precision level). Experimentl results show tht the developed filter hs lower hrdwre cost, better ccurcy nd higher fult tolernce level compred with other stochstic implementtions. Introduction Stochstic computing (SC) [] is computtionl technique with opertions bsed on probbility insted of rithmetic rules [ ]. This technique cn simplify mthemticl functions, which re computtionlly demnding in binry computtion, with simple logic opertions nd reduced hrdwre requirement. It is robust ginst noise. And it hs progressive precision chrcteristic tht the precision of stochstic numbers (bit strems) increses s computtion proceeds []. These dvntges enbled SC s recent pplictions in signl nd imge processing, in prticulr, in reliztion nd implementtion of digitl filters [, ] In this pper, new stochstic inner product core with n improved scling scheme is presented for improving the ccurcy nd fult tolernce performnce of SC bsed finite impulse response (FIR) digitl filters. The proposed inner product core is designed using tree structured multiplexers which is cpble of reducing the criticl pth nd fult propgtion in the stochstic circuitry. The designed inner product core cn led to construction of SC bsed light weight nd multiplierless FIR digitl filters. The performnce of the proposed SC bsed FIR filter is tested vi hrdwre implementtion on n FPGA using cse study on th-order FIR digitl filter. With the filter s order vrying from th to 8th order nd ech hving cutoff frequencies rnging from.π to.8π, empiricl nlysis is performed to evlute the proposed FIR filter s ccurcy levels, fult tolernce cpbilities s well s the ssocited Corresponding uthor: wmingming7@gmil.com hrdwre costs. The obtined results show tht our proposed SC filter design outperforms other existing higher precision stochstic FIR filter designs. The rest of the pper is orgnized s follows. Section reviews stochstic computtionl elements of SC. The motivtion nd problem sttement of proposed SC bsed FIR filter design re presented in Section. Next, n improved stochstic inner product is presented in Section. The proposed function is lter employed to design new SC digitl FIR design nd the cse study is reported in Section. The experimentl results (ccurcy nd fult tolernce nlysis) s well s the hrdwre implementtion for the ppliction is reported nd discussed in Section. Finlly, some conclusion remrks re drwn in Section 7. Bsic Theory of Stochstic Computtion The bsic rule of SC is tht the computtionl dt (in bit-strems) re represented s stochstic sequences nd re processed in form of digitized probbilities []. Nturlly, the representtions nd ll the involved computtions lwys lie within the rel-number unit intervl [, ]. Stochstic representtion cn be coded in two formts: SC-unipolr nd SC-bipolr []. In SC-unipolr formt, the input s is rel number within the unit intervl, i.e. s. As n exmple, s complement binry input bit-strem {} is represented in stochstic bit-strems S, consisting of of bit out of = bits (remining bits re zeros). This stochstic bit-strems S, is lso interpreted s p = P(S = ) = /. On the other hnd, in SC-bipolr formt, the rnge of the rel number input, s, is extended to The Authors, published by EDP Sciences. This is n open ccess rticle distributed under the terms of the Cretive Commons Attribution License. (

2 MATEC Web of Conferences, (7) DOI:./ mtecconf/7 CSCC 7 s. Consider s complement binry input bitstrem {}. In SC-bipolr bit-strems S, the deterministic vlue is mpped to p = P(S = )/ = /( ) = /. In other words, stochstic representtion observes the probbility of s t rbitrry bit position in S. Such representtion serves s the min reson for hving high fult tolernce in SC. A single bit-flip in long bit-strem cuses minor chnge in originl logicl vlue. On the contrry, single bit-flip in the conventionl s complement computtion will result in huge error especilly if the bit-flip occurs on the higher-order bit. Multipliction of two inputs strems, which is computtionl intensive in conventionl signed binry computing, cn be performed using single logicl gte in SC. Consider two stochstic input bit-strems, X nd X nd the output for their multipliction, Y, is derived s, y = P(Y = ) = P(X = )P(X = ) +( P(X = ))( P(X = )) Stochstic multipliction in bipolr formt is clerly logicl XNOR opertion between input bit-strems, X nd X in digitl circuit. For unipolr formt, the multipliction is performed using logicl AND opertion insted. Stochstic multiplier for both unipolr nd bipolr formts re s depicted in Figure. Px AND (i) Unipolr Multiplier Px XOR (ii) Bipolr Multiplier Figure. Stochstic Multiplier for (i) SC-unipolr nd (ii) SCbipolr formts. Addition in SC is performed using specil opertion, termed s scled ddition. The ddition is scled such tht the vlue lwys lies between the probbility intervl [, ]. With S being constnt scle, the sum of two independent stochstic bit-strems X nd X, produces Y, defined s, y = P(Y = ) = P(S = )P(X = ) + ( P(S ))(P(X = )) = SX + ( S )X Thus, multiplexer with conditionl select line S, set s P(S ) = cn be used to relize the scled ddition of two stochstic bit-strems in digitl circuit. Subtrction in SC is similr to the dder except tht the stochstic scled substrctor requires n dditionl inverter nd this only fesible in SC-bipolr formt. Both the stochstic scled dder nd scled substrctor re illustrted in Figure. Px MUX Ps=. (i) Scled Adder Px Figure. Stochstic scled dder/substrctor Problem Sttement MUX Ps=. (ii) Scled Substrctor FIR filter is widely used in mny clssicl DSP pplictions in order to chieve filtering stbility nd liner-phse property. FIR filters re generlly chrcterized by their impulse response coefficients which perform multipliction with the input signls, i.e. the inner product. Alterntively, these computtionlly expensive opertions cn be well pproximted through SC. To be precise, the summtion of the multipliction between input vectors {X, X } nd filter coefficients {, } cn be derived using single stochstic opertion, ) the stochstic scled ddition, i.e. ( X + X. Through SC, the computtionl dt re represented in stochstic bit-strems of n bits (n is precision level) nd re processed in the form on digitized probbilities []. In terms of hrdwre, stochstic scled ddition cn be relized using multiplexer with its conditionl select line, S set s the scling fctor []. Unfortuntely, when repetitive computtions re involved, the implicit scling of in stochstic scled ddition will severly degrde the filter s output ccurcy []. An lterntive stochstic inner product rchitecture ws reported in [, ] where the scling is performed using with unevenly weightings. However, significnt ccurcy degrdtion is observed s the filter s order increses. Therefore, to ddress this issue, new scling scheme in stochstic inner product is required. An Improved Stochstic Inner Product In this work, n improved stochstic inner product is designed using new scling scheme which considers the weight distribution of the filter s coefficients. Under this scheme, the coefficients of equl (or ner equivlent) weightings re pired together nd form the scling fctor in the stochstic scled ddition. For instnce, coefficients {, } is pired when nd this produce scling +. fctor A cusl discrete-time FIR filter of order N (length M = N+) is generlly described s y[n] = N k= [k]x[n k], with y[n] s the output signl, x[n] is the input signl nd {,,,,..., N } re the filter coefficients. All the types of liner phse FIR filters hve symmetric prmeters in bsolute vlue. Therefore, the distribution of the bsolute vlue of the filter s impulse response

3 MATEC Web of Conferences, (7) DOI:./ mtecconf/7 CSCC 7 coefficients resembles bell curve. The lrgest vlue is weighted t the center of the distribution nd decreses grdully towrds the first nd the lst coefficients, i.e N < N < N < < N. Hence, the scled dditions re performed ccording to the pirs of the FIR filter coefficients rrnged such s follows. P = {, N }, P = {, N }, P = {, N },... nd P N = N = { } N, N+ for even length (such s FIR Types II nd IV), P N = N = { } N for odd length (such s FIR Types I nd III). Furthermore, note tht P < P < P < < P < P N with N = N for even filter length nd N = N for odd filter length. With tht, the next round of scled dditions re performed following the piring shown below. P = {P, P }, P = {P, P },... nd P N = N = { P N, P N } for N is odd, P = { P N = N N } for N is even. The similr ddition process is repeted until the inner product computtion is completed. An exmple of the resultnt stochstic inner product using the proposed pproch is shown in (7). Cse Study of New SC FIR Filter Design Consider th-order liner phse Type I FIR filter with its tps coefficients lbeled s {,,,,,, } nd the input vectors listed s {X, X, X, X, X, X, X }. The inner product of the filter is derived s y = X + X + X + X + X + X + X. Using the proposed stochstic inner product, the finl computtion is described in (7) nd is illustrted in Figure. Note tht, both of the input vectors nd filter coefficients re first converted into stochstic bit-strems using SNG modules [], which re not shown in the figure. Y = ( ) X + ( ) X + + () Y = ( ) X + ( ) X + + () Y = ( ) X + ( ) X () + + Y = ( ) X () Y = ( + ) Y ( + ) Y () Y = ( + ) Y + ( ) Y () Y = ( ) Y ( + + ) Y (7) With such filter s coefficients,, nd, the scled ddition in (), () nd () cn be performed using fixed scling fctor. Therefore, the conditionl probbility selection line (which is determined by the scling fctor) of the correspondence multiplexers cn shre the sme SNG modules to promote hrdwre cost reduction. The svings will be more prominent in higher order filter where there is lrge mount of identicl coefficients. In ddition, our SC FIR filter is designed with precision level of 8-bits, whereby the computtions re performed using 8 = bits only. The filter designs in [, ] re computed using = bits insted. Experimentl Results Severl simultions were performed to test the effectiveness nd the efficiency of the proposed SC FIR filter. The metric of mesurements included the output ccurcy (error-to-signl power rtio), the fult tolernce nd the hrdwre requirement nd performnce in FPGA implementtion.. Accurcy Anlysis The new SC low-pss FIR filters, implemented in three different orders nd ech hving four different cutoff frequencies, re evluted for their ccurcy levels. A totl of smples of input test signl is used in the test simultion. The test signl consists of mixture of four sinusoidl wves of different frequencies pdded with white noise. The ccurcies of the proposed filters re mesured in term of the error-to-signl power rtio nd re benchmrked with the work reported in []. These results re s summrized in Tble. The results from [] showed the error rtio increses with higher filters order. In constrst, our SC FIR filter presents consistently lower error rtio regrdless of the filters order. Further ccurcy justifiction cn be deduced by compring the frequency response nd the power spectrl density (PSD) of the output signl deduced from both our SC filter nd the idel filter (see Figure ). It is observed tht the spectrum of our SC filter is very close to tht of the idel filter.. Fult Tolernce Anlysis Aprt from low hrdwre cost, SC is well recognized for being insusceptible towrds fult s opposed to the conventionl binry computing. Fult tolernce testing is conducted on our proposed SC th-order FIR filter with cutoff frequency t.π. The test is performed by rndomly injecting vrious percentge of bit-flipping error in the input signls nd the corresponding error-to-signl power rtio is mesured nd summrized in Tble. The results show tht percentge of rndom bitflipping error rnging from.% to.% hs miniml

4 MATEC Web of Conferences, (7) DOI:./ mtecconf/7 CSCC 7 x(n) D D D D D D sign() sign() sign() sign() sign() sign() y(n) sign() Legend: XOR D Dely - multiplexer Figure. The new SC th-order FIR filter. Tble. Accurcy test results of (i) our proposed design (precision level of 8-bits) compred with (ii) [] (precision level of -bits). Filter Cutoff Frequency Filter.π.π.π.8π Order (i) (ii) (i) (ii) (i) (ii) (i) (ii) Tble. Error-to-signl power rtio nlysis resultnt from vrious percentge of rndom bit-flipping error in th-order FIR filter with cutoff frequency t.π. Filter Percentge of Bit-Flipping Implementtion.%.%.%.%.%.% Our Work Conventionl Filter Direct Form [] Lttice Form [] Tble. Hrdwre review for the FPGA implementtion of the SC th-order FIR filter with cutoff frequency t.π. Hrdwre Requirement/ SC FIR Inner Product SNG Performnce Filter Core Module Combintionl ALUTs (,9) 8 Memory ALUTs (,8) Dedicted Logic Register (,9) 9 Totl Register (,9) 9 Fmx (MHz). 9.9 Dynmic Therml Power Dissiption (mw)...9

5 MATEC Web of Conferences, (7) DOI:./ mtecconf/7 CSCC 7 7 Conclusion Figure. Output spectrum nd PSD derived using the FIR idel filter nd our SC FIR filter. Both filters re low-pss with thorder nd the cutoff frequency t.π. impct on the output ccurcy of our proposed SC FIR filter. On the contrry, the conventionl idel FIR filter shows significnt ccurcy degrdtion s the injected bitflipping error increses t every.%. These results re further benchmrked with the work reported in []. The uthors presented two SC 7th-order FIR filter with cutoff frequency t.π using direct form nd lttice form. Both of their filters lso exhibited higher error percentges in comprison to our work. The multiplexers in our proposed inner product core re positioned in tree structure to void error propgtion tht tends to occur in long criticl pth. Therefore, with short criticl pth, the presented SC FIR filter hs higher fult tolernce in comprison to the conventionl FIR filter s well s the existing SC FIR filters.. Hrdwre Complexity The proposed SC FIR filter is implemented in Cyclone V CGXFC7DFC using Qurtus II.. The full hrdwre synthesis result of the filter s well s its core units; the inner product nd the SNG Module re summrized in Tble. A cse study of new SC FIR filter design using n improved stochstic inner product core ws presented in this pper. Without the use of multiplier, the inner product core unit employed stochstic scled ddition with new scling scheme tht pired the filter s coefficients in ccording to their weightge. The computtion ws relized using multiplexers positioned in tree structure, which in turn reduces the criticl pth s well s the fult propgtion in the stochstic circuitry. Such design enhnced the computtionl ccurcy nd offered high fult tolernce in SC filter system. For hrdwre evlution, new SC th-order FIR filter with the cutoff frequency t.π on FPGA pltform hs been implemented nd tested. Experimentl results hve shown tht the presented SC FIR filter outperforms the conventionl filter nd the existing works in both metrics nd lso hs low hrdwre cost. References [] B. R. Gines, Stochstic computing, Proceedings of the Spring Joint Computer Conference, New York, NY, USA, pp. 9-,(97). [] A. Alghi, nd J. P. Hyes, Survey of Stochstic Computing, ACM Trns. Embed. Comput. Syst., vol., no., pp. 9, (),. [] W. Qin, X. Li, M. D. Riedel, K. Bzrgn, nd D. J. Lilj, An rchitecture for fult-tolernt computtion with stochstic logic,ieee Trnsctions on Computers, vol., no., pp. 9-, (). [] B. Moons, nd M. Verhelst, Energy-efficiency nd ccurcy of stochstic computing circuits in emerging technologies, IEEE Journl on E,merging nd Selected Topics in Circuits nd Systems, vol., no., pp. 7-8, (). [] Y. N. Chng, nd K. K. Prhi, Architectures for digitl filters using stochstic computing, IEEE Interntionl Conference on Acoustics, Speech nd Signl Processing (ICASSP), pp. 97-7, (). [] Y. Liu, nd K. K. Prhi, Lttice fir digitl filter rchitectures using stochstic computing, IEEE Interntionl Conference on Acoustics, Speech nd Signl Processing (ICASSP), pp. 7-, ().