A Low-Power CMOS Piezoelectric Transducer Based Energy Harvesting Circuit for Wearable Sensors for Medical Applications

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1 Journl Low Power Electronics Applictions Article A Low-Power CMOS Piezoelectric Trnsducer Bed Energy Hrvestg Circuit for Werble Sensors for Medicl Applictions Teho Oh 1, * ID, Syed K. Islm 1, Mohmd Mhfouz 2 Gry To 2 1 Deprtment Electricl Engeerg Computer Science, University Tennessee, Knoxville, TN , USA; slm@utk.edu 2 Deprtment Mechnicl, Aerospce, Biomedicl Engeerg, University Tennessee, Knoxville, TN , USA; mmhfouz@utk.edu (M.M.); g@utk.edu (G.T.) * Correspondence: h@vols.utk.edu; Tel.: Received: 20 September 2017; Accepted: 12 December 2017; Publhed: 18 December 2017 Abstrct: Piezoelectric vibrtion bed hrvestg s hve been widely utilized reserched powerg modules for vrious types sensor s due ir ee tegrtion reltively high density compd RF, rml, electrosttic bed hrvestg s. In th pper, low-power CMOS full-bridge presented potentil solution for n efficient hrvestg for s. hrvestg consts n-chnnel MOSFETs (NMOS) p-chnnel MOSFETs () devices implementg full-bridge coupled bed on device driven comprr. With lod 45 kω, 694 m 703 m, respectbly, while versus IN conversion rtio 98.7% PCE 52.2%. hrvestg h been designed usg 130 nm strd CMOS process. Keywords: AC-DC power conversion; hrvestg; ; ctive ; bed 1. Introduction Technologicl dvncements low-power CMOS processes hve driven rpid development sensor electronics such implntble werble sensor s. powerg such sensor s h remed mjor problem sce trditionl btteries cn lek resultg serious helth problems ptients. Moreover, typicl sensor s, vilble spce for btteries very limited re restrictg bttery cpcity. Energy hrvestg h emerged one potentil solutions for powerg sensor electronics h been widely studied recent yers. Energy cn be hrvested vrious mbient sources such electromgnetic, wd, mechnicl vibrtion, RF, rml etc. re three generl sources tht utilize vibrtion, nmely electrosttic, electromgnetic,. Among se sources, vibrtion bed hrvestg h received gret del ttention becuse its ee tegrtion electronic s moderte power density. Severl s bed on s hve been [1 7]. s [4 6] im reduce drop cross diodes while references [2 9] im reduce wted chrges socited chrgg plte cpcitnce furr cree overll efficiency s. In [1,8,10], reserchers hve used techniques clled bi-flip synchronized hrvestg on ducr (SSHI) improve extrction. However, mjor problems socited schemes volve requirement reltively lrge ducrs improve overll efficiency while still requirg very complex s. ; doi: /jlpe

2 J. J. Low Low Power Power Electron. Electron. Appl. Appl. 2017, 2017, 7, 7, Piezoelectric Energy Hrvester 2. Piezoelectric Energy Hrvester 2. Piezoelectric Energy Hrvester 2.1. Generl Architecture Energy Hrvestg System 2.1. Generl Architecture Energy Hrvestg System 1 shows generl buildg block or rchitecture shows shows generl generl buildg buildg block block or or rchitecture rchitecture hrvestg hrvestg [1,]. A cn convert vibrtionl electricl hrvestg [1,]. A [1,]. A cn convert vibrtionl cn convert vibrtionl electricl electricl or cn be used vibrtionl device ppliction n electricl source such or bttery. cn be used or vibrtionl cn be used device vibrtionl ppliction device n ppliction source such n electricl bttery. source When such bttery. When used n electricl generr, n AC produced When used n electricl used generr, n electricl n AC generr, produced n AC t. produced t. refore, n AC--DC or n AC--DC converter must be constructed refore, t n AC--DC. refore, n n AC--DC AC--DC converter or must n be AC--DC constructed converter cquire must be useful constructed DC cquire useful DC. Sce generted n AC--DC or. cquire Sce useful DC generted. Sce n AC--DC generted or converter n AC--DC not sufficient or stble or converter not sufficient or stble enough directly power up, should be converter enough directly not sufficient power up or stble, enough directly should power be generlly up, sred bttery should or super be generlly sred bttery or super cpcir followed regulr such DC-DC converter, generlly cpcir followed sred bttery regulr super such cpcir DC-DCfollowed converter, LDO regulr etc. Insuch generl, re DC-DC converter, LDO etc. In generl, re types conventionl s: -doubler full-bridge types LDO conventionl etc. In generl, s: re -doubler types conventionl [8]. mjor drwbcks se full-bridge s: conventionl -doubler structures [8]. mjor usully drwbcks full-bridge low power se conventionl [8]. low structures mjor drwbcks power conversion usully se efficiencies. low power conventionl A extrction low extrction structures low efficiency power conversion usully low mly ttributed efficiencies. power chrgg Aextrction low extrction low dchrgg efficiency power conversion mly ternl ttributed efficiencies. pritic A cpcitnces chrgg low extrction dchrgg efficiency mly ternl ttributed whenever pritic chrgg cpcitnces chnges its dchrgg polrity ternl pritic lrge whenever cpcitnces drop occurs chnges due its polrity diode turn-on lrge whenever [8]. drop To it overcome occurs chnges dueth its polrity drwbck, diode turn-on number lrge [8]. different To overcome drop occurs schemes th hve drwbck, due diode been number turn-on such different synchronized schemes [8]. To overcome hve beenth hrvestg drwbck, on such ducr, number synchronized different -only schemes hrvester, hrvestg hve etc. onbeen In ducr, order -only such synchronized improve hrvester, conversion etc. In orderhrvestg improveon, ducr, conversion-only diode cn be efficiency replced hrvester,, etc. CMOS. diode In order cn A CMOS be replced improve bed CMOS conversion h. lower Aefficiency CMOS drop bed, compd h diode conventionl lower cn be replced f-chip drop compd CMOS. diode. conventionl A CMOS bed In th pper, f-chip CMOS diode h synchronous. lower In th bed pper, drop compd CMOS hrvestg synchronous conventionl f-chip beddiode which. fers hrvestg In th severl pper, dvntges CMOS synchronous over which schemes fers severlbed dvntges literture over hrvestg due schemes its simplicity literture which fers design, dueseverl moderte its simplicity dvntges hrvestg, design, over moderte schemes requirement hrvestg, literture no f-chip due components requirement its simplicity except no f-chip design, components moderte cpcir. except hrvestg, cpcir. requirement no f-chip components except cpcir. AC-DC Energy AC-DC Converter Energy Converter oltge Regulr oltge Regulr Energy Srge Energy Srge generl buildg block hrvester. 1. A generl buildg block hrvester Trnsducer Modelg 2.2. Trnsducer Modelg device cn be modeled both mechnicl electricl dom tht A device device cn cn be be modeled modeled both both mechnicl mechnicl electricl electricl dom dom tht tht coupled coupled through mgnetic coil [12], illustrted 2 [10,12,13]. In mechnicl dom coupled through through mgnetic mgnetic coil [12], coil illustrted [12], illustrted 2 [10,12,13]. 2 [10,12,13]. In mechnicl In mechnicl dom model dom model, RM represents mechnicl dmpg, CM reciprocl model,, R M represents mechnicl dmpg, C M reciprocl mechnicl RM represents mechnicl dmpg, CM reciprocl mechnicl stiffness, LM effective ms. In electricl dom, vibrtionl excittion mechnicl stiffness, stiffness, L M effective ms. In electricl dom, vibrtionl excittion cn be LM effective ms. In electricl dom, vibrtionl excittion cn be modeled current source pritic cpcitnce, CP modeled current source pritic cpcitnce, C pritic restnce, RP. In cn be modeled current source pritic cpcitnce, P pritic restnce, R P. In CP pritic restnce, RP. In CMOS CMOS ctive ctive,, typicl typicl model model device device h been h been CMOS ctive, typicl model device h used. been used. prmeter vlues for chosen such tht CP 25 nf, RP prmeter vlues for chosen such tht C 1 used. prmeter vlues for chosen such tht P 25 nf, R P 1 MΩ, CP 25 nf, RP 1 MΩ, IP I 45 µa. MΩ, P 45 µa. IP 45 µa. L M R M C M Piezoelectric Trnsducer L M R M C M Piezoelectric Trnsducer I P I P C P C P R P R P I AC C P R P I AC C P R P Mechnicl Dom Electricl Dom Electricl Dom Mechnicl Dom 2. Modelg showg mechnicl electricl dom; simplified Modelg showg mechnicl electricl dom; model Modelg [12]. showg mechnicl electricl dom; simplified model model [12]. [12].

3 J CMOS Full-Wve Rectifier 3. CMOS Full-Wve Rectifier 3.1. Opertg Prciple 3.1. Opertg Prciple As 2 [8], cn be modeled susoidl current As 2 [8], cn be modeled susoidl current source ip(t) = IP s(2πfpt), prllel pritic plte cpcir, CP pritic resr, RP. source i P (t) = I P s(2πf P t), prllel pritic plte cpcir, C P pritic resr, R P. mplitude current, IP vries mechnicl excittion level mplitude current, I P vries mechnicl excittion level while fp represents excittion frequency while f P represents excittion frequency.. typicl full-wve bridge consts four diodes. mjor problem usg n f-chip A typicl full-wve bridge consts four diodes. mjor problem usg n fchip diode conventionl tht it results substntil drop due diode conventionl tht it results substntil drop due diode turn-on ( d ), which typiclly 0.5~0.7. Th lrge turn-on cuses significnt loss diode turn-on (d), which typiclly 0.5~0.7. Th lrge turn-on cuses significnt conventionl full-bridge. In ddition, chrgg dchrgg plte cpcitnce loss conventionl full-bridge. In ddition, chrgg dchrgg plte cpcitnce results loss vilble chrges. To overcome se results loss vilble chrges. To overcome problems, CMOS bed full-bridge -only prllel se problems, CMOS bed full-bridge -only prllel [8]. In -only (SO) scheme, turned on whenever [8]. In -only (SO) scheme, turned current crosses zero which helps dchrge cpcir, C P. Unlike conventionl on whenever current crosses zero which helps dchrge cpcir, CP. Unlike, th process llows SO not dchrge ( RECT + 2 d ). 3,b show conventionl, th process llows SO not dchrge (RECT + 2d). 3,b conventionl full-bridge -only scheme, respectively. To reduce show conventionl full-bridge -only scheme, respectively. To -drop cross diode which ffects conversion efficiency, CMOS bed full-wve bridge reduce -drop cross diode which ffects conversion efficiency, CMOS bed fullwve bridge presented th pper. dvntges th design presented th pper. dvntges th design clude bility power operte out requirg ny f-chip components even clude bility power operte out requirg ny f-chip though power generted SO less thn tht bi-flip or or power enhnced components even though power generted SO less thn tht bi-flip or structures. Th llows more flexibility tegrte s n tegrted. In ddition, or power enhnced structures. Th llows more flexibility tegrte s n usg seprte for SO, current for chrgg tegrted. In ddition, usg seprte for SO dchrgg C sg device cn be effectively reduced, which crees vilble, current for chrgg dchrgg Csg device cn be effectively trnsfer time lod. In ddition, cn be dded N P s reduced, which crees vilble trnsfer time lod. In ddition, reduce wted chrges which used chrge or dchrge cn be dded N P s reduce wted chrges pritic cpcitnce device. 4 shows digrm which used chrge or dchrge pritic cpcitnce device. 4 [1,3,8]. shows digrm [1,3,8]. RECT RECT C P CP N I P P C L R L N IP P CL RL R P RP 3. Circuit schemtics : full-wve, conventionl diode full-bridge. 3. Circuit schemtics : full-wve, conventionl diode full-bridge.

4 4 4 Rectifier_Output (RECT) Rectifier_Output (RECT) C L R L C L R L Body_Bi Control Body_Bi Control N & P Short Switch N & P Short Switch CP RP CP RP IP IP Full-wve Full-wve s s presented presented [1,3,8] [1,3,8] rchitecture. rchitecture Proposed Active Full-Wve Rectifier 3.2. Proposed Active Full-Wve Rectifier 4 shows full-wve structure [1,3,8]. Due cross-coupled 4 shows full-wve structure [1,3,8]. Due cross-coupled nture, it requires current time chrge dchrge Csg nture, it requires current time chrge dchrge C sg chrged directly prior beg turned on f. refore, turn on chrged directly prior beg turned on f. refore, turn on order chrge Csg, PN should order chrge C sg, PN should be greter thn thp. refore, vilble trnsfer time be greter thn thp. refore, vilble trnsfer time will be reduced becuse time required chrge Csg. will be reduced becuse time required chrge C sg. However, ctive 4b, on/f However, ctive 4b, on/f led NMOS turng on/f driven powered buffer. led NMOS turng on/f driven powered buffer. refore, does not pose problems socited design [1,3,8]. refore, does not pose problems socited design [1,3,8]. As 5, time required chrge Csg bout 100 µs (bout 39% less time rech As 5, time required chrge C sg bout 100 µs (bout 39% less time rech pek current ) less thn cross-coupled presented [1,2,8]. pek current ) less thn cross-coupled presented [1,2,8]. f-time lso h been reduced 5b. stntly f-time lso h been reduced 5b. stntly dchrges Csg, result, f time nno-second rnge even though f-time dchrges C sg, result, f time nno-second rnge even though f-time cross-coupled 4.5 µs. refore, more cn be cross-coupled 4.5 µs. refore, more cn be trnsferred resultg PN ([P-N] ) beg trnsferred resultg PN ([ P - N ] ) beg bout 0.7% higher thn tht cross-coupled bed ctive sme lod piezo bout 0.7% higher thn tht cross-coupled bed ctive sme lod piezo. Although 0.7% cn be considered smll improvement, for low power. Although 0.7% cn be considered smll improvement, for low power s such one th pper, every vilble should be squeezed so tht s such one th pper, every vilble should be squeezed so tht more vilble cn be trnsferred. In ddition, if excittion frequency more vilble cn be trnsferred. In ddition, if excittion frequency force pplied lowered, n, chrgg time will be creed force pplied lowered, n, chrgg time will be creed becuse less vilble chrges. As result, mplitude becuse less vilble chrges. As result, mplitude PN will be lowered so RECT. In ddition, sce hrvestg cn PN will be lowered so RECT. In ddition, sce hrvestg cn hle more thn cross-coupled,, RECT, higher thn tht hle more thn cross-coupled,, RECT, higher thn tht cross-coupled. 6,b show body lekge current body bi cross-coupled. 6,b show body lekge current body bi utilizg lekge current, respectively. With help simple implementtion body-bi utilizg lekge current, respectively. With help simple implementtion body-bi, cn chieve lower body lekge current compd crosscoupled [1,3,8]., cn chieve lower body lekge current compd cross-coupled [1,3,8]. shows body lekge current tht h been used body 6 shows body lekge current tht h been used body bi. bi. In 6b, IN connected RECT, connected eir P or N, body-bi In 6b, IN connected RECT, connected eir P or N, body-bi port port connected body. As 6, lekge current connected body. As 6, lekge current 12. pa (blck le) while lekge current cross-coupled pa (blck le) while lekge current cross-coupled na (red na (red le), which huge improvement. With help ll bove improvements, le), which huge improvement. With help ll bove improvements, ctive 698 m while tht cross-coupled bed ctive 698 m while tht cross-coupled bed 694 m. 694 m.

5 Compron cross-coupled cross-coupled full-wve [1,3,8] 5. full-wve 5. Compron Compron cross-coupled full-wve [1,3,8] [1,3,8] 5. Compron cross-coupled full-wve [1,3,8] rchitecture (Simulted): on-time; f-time (blue circle mgnified). rchitecture (Simulted): on-time; f-time (blue circle mgnified). rchitecture (Simulted): on-time; f-time (blue circle mgnified). rchitecture (Simulted): on-time; f-time (blue circle mgnified). IN IN IN Body_Bi Body_Bi Body_Bi 6. Body bi bed ctive, simulted body bi. lekge current body 6. Body bi bed ctive, simulted body Body Body bi bi bed bed ctive ctive,, simulted simulted body body lekge body bi ctive. current -only cross-coupled ctive lekge current current body body bi bi lekge.. -only simulted sme MOSFET sizes sme piezo current. only ctive schemes p methods. 7 shows difference -only gte cross-coupled ctive -only ctive cross-coupled ctive -only ctive RECT ctive wveform current, ip versus cross-coupled conventionl full-wve. -only simulted sme MOSFET sizes sme piezo current. -only simulted sme MOSFET sizes sme piezo current. -only simulted sme MOSFET sizes sme piezo current. shded regions show wted due chrgg dchrgg pritic cpcir, only difference schemes p gte methods. 7 shows only schemes gtegte methods. 7 shows Cdifference P. only difference schemes p p methods. 7 shows wveform current, ip versus RECT conventionl full-wve. wveform current, ip versus RECT RECT conventionl full-wve. show current, ip versus conventionl wveform shded regions wted due chrgg dchrgg pritic full-wve cpcir, shded regions show wted due chrgg dchrgg pritic cpcir,. shded regions show wted due chrgg dchrgg pritic CP. C P. cpcir, CP. 7. Wveform Wveform Wveform.. 7. Wveform.

6 6 It evident figure tht significnt mount lost due chrgg dchrgg ctions C P. In 7, difference t 0 t 1 represents wted when i P used chrge C P. tl chrge vilble full-bridge cn be written, Q tl/ = 2π/ωP 0 i P dt = 4I P ω P = 4C P P (1) where p mplitude open. current, i P, h chrge C P RECT RECT every before turng on diode conventionl full bridge diode. refore, chrge lost every cn be written [8], Q lost = 2C P ( RECT ( RECT )) = 4C P RECT (2) From Equtions (1) (2), ctul chrge tht used chrge C L 3 cn be written [8], Q RECT = Q tl Q lost = 4C P p 4C P RECT (3) Multiplyg Eqution (3), RECT provides tl delivered C L. refore, tl cn be written [8], Energy RECT = Q RECT RECT = 4C P RECT ( p RECT ) Sce opertes t frequency, f P tl power delivered cpcir, C L conventionl full-bridge cn be expressed [8], Power RECT = Energy RECT f P = 4C P RECT f P ( p RECT ) Usg Eqution (5), mximum vilble power obted when RECT = P /2, cn be expressed P RECT (MAX) = C P ( P ) 2 f P (6) To reduce th unwnted loss or cree trnsfer, one effective scheme volves sertg s, P N 4. 8 shows stedy-stte opertion full-wve. It cn be seen 8 tht opertion full-wve cn be divided three phes. In phe 1 t 0 t 1, susoidl current, i P strts chrgg pritic cpcir, C P. Unlike conventionl 3, time for chrgg C P h been reduced significntly becuse clusion P N. In 9, it cn be seen tht one-shot turns on, P N termls shorted stntly refore it does not hve chrge its previous vlue, rr it strts zero. In conventionl, when i P chngg its polrity positive negtive, C P should be dchrged ( RECT + 2 d ) zero chrged zero ( RECT + 2 d ). In phes 2 3, sce chrgg pritic cpcir C P h been completed, cn be trnsferred cpcir, C L through full-wve. (4) (5)

7 J. Low Power Electron. Appl. 2017, 7, 7, J. Low Low Power Power Electron. Electron. Appl. Appl. 2017, 2017, J. 7, Simulted Simulted wveform.. Simulted wveform 8. Simulted wveform. 99 shows shows serted serted PP NN which which 99 shows which which PP shows serted serted prciple NN for llows cpcir dchrge zero. workg one-shot very llows cpcir dchrge zero. workg prciple for one-shot very llows cpcir cpcir dchrge zero. workg prciple for one-shot one-shot llows dchrge zero. workg prciple for very simple. simple. very simple. simple. Body Bi Bi Body Body Bi Control Control Control Schemtic. 9. Schemtic 9. Schemtic. Whenever crosses crosses zero zero pot, pot, one-shot one-shot Whenever Whenever crosses zero pot, one-shot Whenever crosses zero pot, one-shot designed designed provide provide short short pulse pulse which which shorts shorts ports ports designed provide short pulse which shorts ports 10 10reset designed provide short pulse which shorts ports efficiency s PP N.. Th Th shortg ction willwill help improve reset s N shortg ction will help improve efficiency reset reset s s. Th shortg ction help improve efficiency PP N. N Th shortg ction will help improve efficiency hrvestg reducg wte chrge. refore, i P does does not hve hrvestg reducg wte chrge. refore, i P not hve hrvestg reducg wte chrge. refore, ip does not hve hrvestg but reducg wte chrge. refore, ipbotm does not hve chrge or dchrge C P ±( RECT d)) but rr zero ( RECT d). ). NMOS chrge or dchrge C P ±( RECT 2 d rr zero ( RECT 2 d botm NMOS chrge or dchrge CP ±( 2d) but + 2 rr (RECT +botm 2d ). botm d ) but chrge or dchrge CP ±( RECT + RECT rr (zero RECT + 2d). NMOS es led low-power comprr whilezero p es led es es led low-power comprr while p es led NMOS led low-power comprr while p es es led br low-power comprr while p es led s. All s comprr powered br s. All s comprr powered led br br s. Alls s comprr s. All comprr powered hrvested supply, RECT RECT.. hrvested supply, powered hrvested supply,. RECT hrvested supply, RECT. Output Output Output 10. Schemtic one-shot digitl. 10. Schemtic Schemtic one-shot one-shot digitl digitl Schemtic one-shot digitl.

8 LowPower PowerElectron. Electron.Appl. Appl.2017, 2017,7,7,33 33 J.J.Low 88 In full wve, chrge lost every cn be denoted [8], In full wve, chrge lost every cn be denoted [8], =2 / Qlost/ = 2CP RECT chrge vilble cn be clculted [8], chrge vilble cn be clculted [8], = =4 Q RECT = Q tl Q lost 2 = 4CP open 2CP RECT (7) (7) (8) (8) refore, tl power delivered lod CL cn be expressed follow [8]. refore, tl power delivered lod CL cn be expressed follow [8]. = =2 (2 ) Power RECT = Energy RECT f P = 2CP RECT f P 2open RECT (9) (9) Compron Compron Equtions Equtions (3) (3) (8) (8) revels revels tht tht chrge chrge lost lost reduced reduced bout bout 50%. 50%. refore, sertg P N cn sve substntil refore, sertg P N cn sve substntil mount mount.. All All s s th th ctive ctive powered powered, RECT derived hrvested. illustrtes strt-up opertion, RECT derived hrvested. illustrtes strt-up opertion. strt-up opertion, opertion,llll s cludg comprrs. For For strt-up s cludg comprrs not workg until C L chrged properly sce no chrge ccumulted CL itilly. As not workg until CL chrged properly sce no chrge ccumulted CL itilly. As, lekge current through both (M P) NMOS(MN), lekge current flows flows through both (M P ) NMOS(MN ) strts creg re slowly chrgg L. itil chrgg current strts creg re slowly chrgg CL. itilcchrgg current derived derived th lekge current nno-mpere rnge. time required chrge 120 CL µs th lekge current nno-mpere rnge. time required chrge CL pproximtely pproximtely 120 µs resultg hrvested supply power ll s cludg resultg hrvested supply power ll s cludg comprrs. Proper comprrs. llt strts t round 180 µs. CompP CompN workg llproper workg strts round 180 µs. Comp P CompN wveform wveform comprrs, One-Shot wveform Comp One-Shot comprrs, One-Shot wveform One-Shot. P CompN. Comp P CompN represent s 4b. represent s 4b.. Simulted strt-up ctive.. Simulted strt-up ctive. 4.Meurement MeurementResults Results 4. s show show meured meured wveforms wveforms full-wve full-wve.. For For s ske simplicity vlidte opertion s, w generted ske simplicity vlidte opertion s, w function pk-pk 1.2 (600 mplitude). w generted generr function generr pk-pk m 1.2 (600 m mplitude). meured w be 580 m lod resr 45 kω. meurement dt slightly different simulted meured be 580 m lod resr 45 kω. meurement dt slightly different becuseone pritic PCB bord cpcitnce pritics. 12c,d one simulted becuse pritic PCB bord cpcitnce chip-pckge chip-pckge pritics. 12c,d show test set-up. Sce tested generr,

9 9 LowPower PowerElectron. Electron.Appl. Appl.2017, 2017,7,7,33 33 J.J.Low 99 show test set-up. Sce tested generr, model used th test set-up rn ven equivlent 13b. represents model used thtest test set-up rn rn ven ven equivlent 1 13b. model used th set-up equivlent 13b. generr ngenerr mplitude (PK-PK 1.2 ), R represents generr n0.6 mplitude ( PK-PK ), kω, represents n mplitude ( PK-PK ), 13.3 kω, cpcitnce pritic cpcitnce... CRRP 13.3 pritic cpcitnce kω, CCPPpritic Meured Meured wveforms wveforms mgnified; mgnified; full full wveform. 12. Meured wveforms mgnified; full wveform. wveform. 13.One-shot One-shot One-shot wveforms; wveforms; equivlent 13. equivlent equivlent 13. wveforms; ; (c) test setup; (d) prted bord (PCB) implementtion test bord. ; (c) test setup; (d) prted bord (PCB) implementtion test bord. ; (c) test setup; (d) prted bord (PCB) implementtion test bord. 5. Conclusions 5. Conclusions 5. Conclusions 14 14shows shows lyout lyout full-wve full-wvecmos CMOS microphogrph microphogrph 14 showsic lyout full-wve fbricted fbricted Tble shows summry summry CMOS performnce. microphogrph mplitude IC Tble shows performnce. mplitude fbricted IC Tble 1 shows summry performnce. mplitude simulted conversion rtio versus IN 98.7% simulted conversion rtio versus IN 98.7%.. simulted conversion rtio power versus IN efficiency 98.7%. power, full-wve 10.7µW, µw, power conversion efficiency (PCE) power, PP full-wve 10.7 conversion (PCE) power, P full-wve 10.7 µw, power conversion efficiency 52.2%, th PCE cn be chieved t 45 KΩ (Mx PCE). m reon for 52.2%, th PCE cn be chieved t 45 KΩ (Mx PCE). m reon for (PCE) low PCE due due low vilble power. m ide th th ctive low low 52.2%, th PCE cn be chieved tm 45 KΩ (Mx PCE). m reon for PCE low vilble power. ide ctive PCE due low vilble power. m ide th ctive reduce f-chip components much possible so tht th hrvester cn be eily tegrted

10 10 reduce f-chip components much possible so tht th hrvester cn be 10 eily tegrted or complex s. In ddition, performnce demonstrtes tht reducg time for chrgg dchrgg Csg, or complex In ddition, performnce mplitude ystems. will cree. Thdemonstrtes process svestht reducg time for chrgg dchrgg C, mplitude wted chrges cused CP, cnsgbe creed even though crement cree wted chrges mplitudewill smll. As. Tble 1,Th process PCE sves cused CP, hrvestg cns be creed even Reference crement[8] comprble or though literture. used n externl mplitude smll. Aswill Tble PCE power. comprble or power source, which decree 1,hrvested References [1,3] used high piezo current, ip hrvestgs design literture. Reference [8] used nexternl compd th high mplitude chieve power higher source, which.will In decree power. [1,3] high piezo current, compd th ddition, n hrvested ducr used References reference [1]used furr cree ippce overll. design highsuch chieve In ddition, n ducr used However, highmplitude currenthigher. n dditionl ducr firly big reference [1] cree fr PCE. However, such high vlue, PCE furr ir not overll simple but effectively led. current n dditionl ducr big vlue, PCE ir not w provided firly function generr sted fr for but led pro simple concept effectively.. prelimry test results show w provided function generr sted full-wve for pro concept tht overll performs expected. 14 shows lyout. prelimry test results show tht overll performs full-chip micro-phogrph. expected. 14 shows full-wve lyout full-chip micro-phogrph. Tble 1. Performnce Compron. Tble 1. Performnce Compron. Publictions Inducr Externl Components Publictions Externl Power Inducr Externl Components Amplitude IP PD or Applied force Externl Power Pritic Cpcitnce orpd (nf) force Amplitude IP PD Applied ibrtion Pritic Frequency Cpcitnce(Hz) PD (nf) ibrtion Frequency (Hz) IN,Pek IN,Pek () () RL (KΩ) R (KΩ) L PCE PCE (%) (%) [1] [3] SO [8] Th Work Yes [1] [3] SO [8] Th Work Yes 2Yes ma 94 µa 3.35 g 45 µa Yes ma 94 µa g12 45 µa % higher thn conventionl. 160% higher thn conventionl Converted PCE Converted PCE63% 63% 14. Lyout full-wve full-wve (540 (540 µm µm Lyout chip chip microphogrph microphogrph 540 µm). µm). Acknowledgments: Thnks Syed K. Islm, Mohmd Mhfouz Gry To for ir support test equipment for work.through chip beeneduction mnufctured through MOSIS Acknowledgments: vluble chip hdvice been mnufctured h MOSIS support. eduction support. Author Contributions: Teho Oh designed tested novel works. Thnks Syed K. Islm, Author Contributions: designed tested test novel prepd Mohmd Mhfouz Teho Gry Oh To for ir support equipment works. Also vluble dvicemnuscript. for work. Conflicts Conflicts Interest: Interest: uthors decl no conflict conflict terest. terest. References Krihely, N.; Ben-Ykov, S. Self-Conted Piezoelectric Sources Sources under under rible Self-Conted Resonnt Rectifier for Piezoelectric IEEE Trns. Trns. Power Electron. 20, 26, [CrossRef] Mechnicl Excittion. IEEE D, U.; U.; Chung, Chung, D.; D.; Prk, Prk, D.; Lee, H.; Lee, J.W. A high extrction self-lble CMOS resonnt D, for scvengg. In In Proceedgs Proceedgs 2014 Interntionl SoC Design Conference (ISOCC), Jeju, Kore, 3 6 vember 2014; pp

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