Adiabatic Technique for Energy Efficient Logic Circuits Design

Transcription

1 PROCEEDINGS OF ICETECT 11 Aditic Technique for Energy Efficient Logic Circuit Deign Rkeh Kumr Ydv #1, Ahwni K. Rn #, Shwet Chuhn #3, Deepeh Rnk #4, Kmleh Ydv #5 # Deprtment of Electronic nd Communiction, Ntionl Intitute of Technology, Hmirpur Hmirpur (H.P)-1775, Indi 1 rtu8@gmil.com hwni_pper@yhoo.com 3 hwet47@gmil.com 4 rnk.deepeh@gmil.com 5 kmlehnhr@gmil.com Atrct The Energy iption conventionl circuit cn e mimized through ditic technique. By ditic technique iption PMOS network cn e mimized nd ome of energy tored t lod cpcitnce cn e recycled ted of ipted het. But the ditic technique i highly dependent on prmeter vrition. With the help of TSPICE imultion, the energy conumption i nlyzed y vrition of prmeter. In nlyi, two logic fmilie, (Efficient Chrge Recovery Logic) nd (Poitive Feedck Aditic Logic) re compred with conventionl logic for verter nd :1 multiplexer circuit. It i fd tht ditic technique i good choice for low power ppliction pecified frequency rnge. Index Term Aditic witchg, energy iption, power clock, equivlent model. I. INTRODUCTION HE term ditic decrie the thermodynmic Tprocee which no energy exchnge with the environment, nd therefore no ipted energy lo. But VLSI, the electric chrge trnfer etween node of circuit i conidered the proce nd vriou technique cn e pplied to mimize the energy lo durg chrge trnfer event [1, ]. Fully ditic opertion of circuit i n idel condition. It my e only chieved with very low witchg peed. In prcticl ce, energy iption with chrge trnfer event i compoed of n ditic component nd non-ditic component [1-5]. In conventionl logic circuit (Fig.1), from to V DD trnition of the put node, the totl put energy C LV DD i drwn from power upply. At the end of trnition, only 1 C energy i tored t the lod cpcitnce. The hlf of LV DD drwn energy from power upply i ipted PMOS network (F). From V DD to trnition of the put node, energy tored the lod cpcitnce i ipted the NMOS network (/F) [1]. Aditic logic circuit reduce the energy iption durg witchg proce, nd reue the ome of energy y recyclg from the lod cpcitnce [1, ]. For recyclg, the ditic circuit ue the contnt current ource power upply nd for reduce iption it ue the trpezoidl [6] or uoidl power upply voltge [7]. V DD F /F Fig.1 Conventionl logic circuit with pull-up (F) nd pull-down (/F) network. II. DISSIPATION MECHANISMS IN ADIABATIC LOGIC CIRCUITS Fig. how, the equivlent circuit ued to model the conventionl circuit durg chrgg proce of the put lod cpcitnce. But here contnt voltge ource i replced with the contnt current ource to chrge nd dichrge the put lod cpcitnce. Here R i on reitnce of the PMOS network, C L i the lod cpcitnce [1]. C L /11/$6. 11 IEEE 776

2 I R C L ue four phe clockg rule to efficiently recover the chrge delivered y. For detiled tudy follow the reference [1]. Fig. Equivlent model durg chrgg proce ditic circuit. Energy iption reitnce R i [1], E = I Sce CLVDD RCL. R. T =. R. T =. CLVDD E T depend upon R, o y reducg the on reitnce of PMOS network the energy iption cn e mimized. The on reitnce of the MOSFET i given y the firt order pproximtion i [3-5], R μc W L T ( V V ) = OX GS th Where μ i the moility, COX i the pecific oxide cpcitnce, V i the gte ource voltge,w i the GS width, L i the length nd Vth i the threhold voltge. E lo depend upon the chrgg time T, If T>> RC then energy iption will e mller thn the conventionl [1]. The energy tored t put cn e retrieved y the reverg the current ource direction durg dichrgg proce ted of iption NMOS network. Hence ditic witchg technique offer the le energy iption PMOS network nd reue the tored energy the put lod cpcitnce y reverg the current ource direction [1, ]. III. ADIABATIC LOGIC FAMILIES There re the mny ditic logic deign technique [8-18] re given literture ut here two of them re choen [1] nd [11], which how the good improvement energy iption nd re motly ued reference new logic fmilie for le energy iption. A. Efficient Chrge Recovery Logic () The chemtic nd imulted wveform of the verter gte i hown Fig.3 nd Fig.4 repectively. Initilly, put i high nd put / i low. When power clock () rie from zero to V DD, ce F i on o put rem ground level. Output / follow the. When reche t V DD, put nd / hold logic vlue zero nd V DD repectively. Thi put vlue cn e ued for the next tge n put. Now fll from V DD to zero, / return it energy to hence delivered chrge i recovered. 1 Fig.3 Schemtic of verter. Fig.4 Simulted wveform of the verter gte. The chemtic nd imulted wveform of the :1 Multiplexer i hown Fig.5 nd Fig.6 repectively. Initilly, elect put i high nd power clock () rie from zero to V DD, put will elect the put. If elect put i low nd power clock () rie from zero to V DD, put will elect the put. When reche t V DD, put nd / hold logic vlue. Thi put vlue cn e ued for the next tge n put. Now fll from V DD to zero, high put return it energy to hence delivered chrge i recovered. C1 m m5 m6 / / m9 m m7 m8 / Fig.5 Schemtic of :1 Multiplexer. / / / C / 777

3 The chemtic nd imulted wveform of the :1 Multiplexer i hown Fig.9 nd Fig.1 repectively. Initilly, elect put i high nd power clock () rie from zero to V DD, put will elect the put. If elect put i low nd power clock () rie from zero to V DD, put will elect the put. When reche t V DD, put nd / hold logic vlue. Thi put vlue cn e ued for the next tge n put. Now fll from V DD to zero, high put return it energy to hence delivered chrge i recovered. / m5 m6 m9 / Fig.6 Simulted wveform of the :1 Multiplexer. B. Poitive Feedck Aditic Logic () The chemtic nd imulted wveform of the verter gte i hown Fig.7 nd Fig.8 repectively. Initilly, put i high nd put / i low. When power clock () rie from zero to V DD, ce F nd re on o put rem ground level. Output / follow the. When reche t V DD, put nd / hold logic vlue zero nd V DD repectively. Thi put vlue cn e ued for the next tge n put. Now fll from V DD to zero, / return it energy to hence delivered chrge i recovered. ue four phe clockg rule to efficiently recover the chrge delivered y. For detiled tudy follow the reference [11, 13]. m7 m8 1 m C1 C Fig.9 Schemtic of :1 Multiplexer / / m5 m m6 / / Fig.7 Schemtic of verter Fig.8 Simulted wveform of the verter gte / / Fig.1 Simulted wveform of the :1 Multiplexer / IV. IMPACT OF PARAMETER VARIATIONS ON THE ENERGY CONSUMPTION Energy conumption ditic circuit trongly depend on the prmeter vrition [19-1]. The impct of prmeter vrition on the energy conumption for the two logic fmilie i vetigted with repect of logic circuit, y men of TSPICE imultion. Simultion re crried t 5nm technology node. The W/L rtio of the PMOS nd 778

4 NMOS re tken 9λ λ nd where λ = 15nm. A. Trnition Frequency Vrition 3λ repectively, λ Fig.11 how the energy iption per cycle veru witchg frequency of the two ditic logic fmilie nd for the verter logic. Fig.1 how the energy iption per cycle veru witchg frequency of the two ditic logic fmilie nd for the :1 multiplexer. It i een tht for high frequency the ehvior i no more ditic nd therefore the energy iption cree. At low frequencie the iption energy will cree for oth nd ditic logic due to the lekge current of the trnitor. Thu the imultion re crried only t ueful rnge of the frequencie to how etter reult with repect to Frequency [Hz] Fig.11 Energy conumption per cycle veru frequency for n verter t V DD =.5V nd lod cpcitnce = ff Frequency [Hz] Fig.1 Energy conumption per cycle veru frequency for :1 multiplexer t V DD =.5V nd lod cpcitnce = ff. B. Lod Cpcitnce Vrition Fig.13 how the energy iption per cycle veru lod cpcitnce of the two ditic logic fmilie nd for the verter logic. Fig.14 how the energy iption per cycle veru lod cpcitnce of the two ditic logic fmilie nd for the :1 multiplexer. The Figure how tht ditic logic fmilie hvg etter energy vg thn logic over wide rnge of lod cpcitnce. how etter energy hvg thn t high lod cpcitnce Lod cpcitnce [ff] Fig.13 Energy conumption per cycle veru lod cpcitnce for n verter t V DD =.5V nd frequency = 1 MHz Lod cpcitnce [ff] Fig.14 Energy conumption per cycle veru lod cpcitnce for :1 multiplexer t V DD =.5V nd frequency = 1 MHz. C. Supply Voltge Vrition Fig.15 how the energy iption per cycle veru upply voltge of the two ditic logic fmilie nd for the verter logic. Fig. 16 how the energy iption per cycle veru upply voltge of the two ditic logic fmilie nd for the :1 multiplexer. It i een tht upply voltge decree, the gp etween nd logic fmilie i reduced. But nd till how lrge energy vg over wide rnge of upply voltge. 779

5 Supply voltge [v] Fig.15 Energy conumption per cycle veru upply voltge for n verter t lod cpcitnce = ff nd frequency = 1 MHz Supply voltge [v] Fig.16 Energy conumption per cycle veru upply voltge for :1 multiplexer t lod cpcitnce = ff nd frequency = 1 MHz.. V. CONCLUSION The different prmeter vrition gt ditic logic fmilie re vetigted, which how tht ditic logic fmilie highly depend upon it. But le energy conumption ditic logic fmilie cn e till chieved thn logic over the wide rnge of prmeter vrition. how etter energy hvg thn t the high frequency nd high lod cpcitnce. Hence ditic logic fmilie cn e ued for low power ppliction over the wide rnge of prmeter vrition. REFERENCES [1] W. C. Ath, L.J. Svenon, J.G. Koller, N. Tzrtzni, nd E. Chou, Low power digitl ytem ed on ditic-witchg prciple, IEEE Trn. VLSI Sytem, vol., no. 4, pp , Dec [] J. S. Denker, A review of ditic computg, IEEE Symp. on Low Power Electronic, pp , [3] A. P. Chndrkn, S. Sheng, nd R. W. Broderen, Low-power digitl deign, IEEE J. Solid-Stte Circ., vol. 7, no. 4, pp , Apr [4] A. G. Dickon nd J. S. Denker, Aditic dynmic logic, IEEE J. Solid-Stte Circuit, vol. 3, pp , Mr [5] J. G. Koller nd W. C. Ath, Aditic witchg, low energy computg, nd the phyic of torg nd erg formtion, IEEE Pre, Pmc. Workhop on Phyic nd Computtion, PhyCmp 9. oct [6] T. Gr, Puled Power Supply, Technicl Diget IEEE Sympoium Low Power Electronic, Sn Diego, pp , Oct [7] B. Vo nd M. Glener, A low power uoidl clock, In Proc. of the Interntionl Sympoium on Circuit nd Sytem, pp , Myl. [8] A. Krmer, J. S. Denker, S. C. Avery, A. G. Dickon, nd T. R. Wik, Aditic computg with the N-ND logic fmily, IEEE Symp. on VLSI Circuit Dig. of Tech. Pper, pp. 5-6, Jun [9] A. Krmer, J. Denker, B. Flower nd J. Moroney, Second Order Aditic Computtion with N-P nd N-NP Logic Circuit, Proceedg of terntionl ympoium on low power deign, pp , [1] Y. Moon nd D.K. Jeong, An efficient chrge recovery logic circuit, IEEE J. Solid-Stte Circuit, vol. 31, no. 4, pp , Apr [11] A. Vetuli, S. Di Pcoli, nd L. M. Reyneri, Poitive feedck ditic logic, Electron. Lett., vol. 3, pp , Sept [1] A. Blotti, S. D. Pcoli, R. Sletti, Smple Model for poitive feedck ditic logic power conumption etimtion, Electronic Letter, Vol. 36, No., pp , Jn.. [13] J. Ficher, E. Amirnte, A. B. Stoffi, nd D. S. Lndiedel, Improvg the poitive feedck ditic logic fmily, Advnce Rdio Science, pp. 1 5, 4. [14] C. K. Lo nd P. C. H. Chn, An ditic differentil logic for lowpower digitl ytem, IEEE Trn. Circuit Syt. II, vol. 46, pp , Sept [15] V.G. Oklodzij, D. Mkimovic, L. Fengcheng, P-trnitor ditic logic ug gle power-clock upply, IEEE Trn. Circ. Syt. II, Vol. 44, pp , Oct [16] W. C. Ath nd N. Tzrtzni, Energy Recovery for Low-Power, Chpel Hill Conf. on VLSI, pp , Proc [17] W. C. Ath, J. G. Koller, nd L. J. Svenon, An energy-efficient le driver ug ditic witchg, Proc. Fourth Gret Lke Symp. VLSI Deign, pp , Mr [18] T. Indermuer nd M. Horowitz, Evlution of Chrge Recovery Circuit nd Aditic Switchg for Low Power Deign, Technicl Diget IEEE Sym. Low Power Electronic, Sn Diego, pp. 1-13, Oct.. [19] E. Amirnte, A. B. Stoffi, J. Ficher, G. Innccone, nd D.S. Lndiedel, Vrition of the power iption ditic logic gte, Proc. 11th Int. Workhop PATMOS, Yverdon-Le-B, Switzerlnd, pp , Sept. 1. [] M. Eiele, J. Berthold, D. S. Lndiedel, R. Mhnkopf, The Impct of Intr-Die Device Prmeter Vrition on Pth Dely nd on the Deign for Yield of Low Voltge Digitl Circuit, IEEE Trnction on VLSI Sytem, Vol. 5, No. 4, pp , Dec [1] R. T. Hmn nd M. F. Schlecht, Power iption meurement on recovered energy logic, IEEE Symp. VLSI Circuit Dig. Tech. Pper, pp. 19, June