MULTILEVEL INVERTER TOPOLOGIES USING FLIPFLOPS

Transcription

1 MULTILVL INVRTR TOPOLOGIS USING FLIPFLOPS C.R.BALAMURUGAN S.SIVASANKARI Aruni ngineering College, Tiruvnnmli. Indi S.P.NATARAJAN Annmli University, Chidmbrm, Indi Abstrct: Multi s re used in high power pplictions for reducing the voltge rting of the semiconductor switching devices. This pper proposes three types of multi topologies by using flip flops nd logic gtes. The topologies re five cscded multi, five diode clmped multi nd five flying cpcitor multi. The switching sttes of the topologies re formed s the Boolen equtions by using the four bit counter. The equtions re given s the input to the ech switch of the multi by using the logic gtes. The proposed topologies cn produce the five output which re nerer to the sinusoidl wve. This proposed system is used to reduce the totl hrmonic distortion (THD) nd lso increses the performnce of the system. Key words: CMLI, DCMLI, FCMLI, flip flops, gtes. 1. Introduction. An is n electronic device used to convert the Direct Current (DC) into Alternting Current (AC). Multi s re clssified into three types: cscded multi, flying cpcitor multi nd diode clmped multi. Flip flop is dt storge element tht hs two stble sttes. It is used to store the stte informtion. s cn be splitted into types. It cn be simple or clocked. The simple one is ltches, while clocked devices re clled s flip flops. Bhrtkr et l [1] proposed cscded multi for high voltge nd high power output ppliction. Khoun jhn et l [] developed topology which reduces the number of switches nd cost. K. Sudheer Kumr et l [3] proposed new multi topology with reduced number of switches which is used to control the hybrid electric vehicles. Ayoub Kvousi et l [4] developed cscded multi, in which the hrmonics re minimized by using the Bee optimiztion method. Dmoun Ahmdi et l [5] proposed the hrmonic elimintion method for high power multi s. FeteFilho et l [6] presents eleven cscded multi. In this proposed method the hrmonics re eliminted by using the rtificil neurl networks. Mlinowski M et l [7] proposed different topologies, control strtegies nd modultion techniques for cscded multi s. Filho F et l [8] described the single phse eleven cscde multi DC-AC grid -tied. Villnuev et l [9] proposed single phse cscded H bridge converter for grid connected photovoltic ppliction. Hiwen Liu et l [10] described the PWM method for hybrid cscded multi. Dher.S et l [11] presented the multi topologies for stndlone photovoltic systems. Json R. Wells et l [1] developed modultion bsed method for hrmonic elimintion. José Rodríguez et l [13] proposed different topologies with seprte DC sources. It lso presents control nd modultion method for the topologies. S.Sirisukprsert et l [14] nlyses the multi voltge source converters bsed on modultion technique.. Five Cscded multi using s The generl structure of the multi is used to generte the sinusoidl wves from the severl s of input DC sources. The stress on ech switching device cn be reduced by using the multi which is proportionl to the number of s of multi. One of the proposed topology is five Cscded Multi Inverter (CMLI) which is shown in Fig. 1(). Logic gtes p 5 p 8 Fig. 1(). bsed five Cscded multi p 1 p 4 p7 p 3 p p 6 n 1

2 Tble 1 Switching sttes of five Cscded multi Switching sttes P1 P P3 P4 P5 P6 P7 P8 voltge Here A, A, B, B, C, C, D, D represents the output of the JK flip flop. These outputs re given s the input to the logic digrm which is formed by using logic gtes for ech switch. ch switch hs the seprte logic digrm. This topology produces the five output with reduced Totl Hrmonic Distortion (THD). The simultion output of the five flip flops bsed cscded multi is shown in Fig The bove tble represents the switching sttes of the five cscded multi. Here P1, P, P3, P4, P5, P6, P7, P8 represents the switches of the multi nd represents the input voltge source. To obtin, P1, P, P5, P6 switches will be turned ON nd the other switches should be turned OFF. For, P1, P3, P5, P6 switches re turned ON. For 0, P1, P3, P6, P8 switches will be turned ON. To get, P3, P4, P5, P7 switches will be turned ON nd the remining switches must turned OFF. The switches P3, P4, P7, nd P8 re turned ON for -. denotes the input voltge of the multi. By using these switching sttes nd the four bit counter, the following Boolen equtions re formed. P1=C B A +CBA+D (1) P=D CA +D B A+D C B () P3= C B A +CBA+D (3) P4= DCA +DB A+DC B (4) P5=C B +CB+D (5) P6=D CB +D C B (6) P7=C B +CB+D (7) P8=DCB +DC B (8) The bove equtions re given s the input by using the logic gtes nd flip flops. The logic digrm for these equtions is drwn by using the logic gtes. This logic digrm for ech switch is given s the input. The schemtic digrm for JK flip flop is shown in Fig.1(b). Fig.. Simultion output of bsed five Cscded multi A logic gte is physicl device which is used to implement Boolen function tht is, it performs logicl opertion on one or more logicl inputs nd produces logicl output. The flip flops cn be clssified into four types. JK flip flop, SR flip flop, D flip flop nd T flip flop. The THD nlysis for five CMLI is shown in Fig. 3. Fig. 1(b). Schemtic digrm of JK flip flop Fig. 3. THD nlysis for bsed five CMLI.

3 3. Five Diode Clmped multi using s The next proposed method is five Diode Clmped Multi Inverter (DCMLI). The schemtic digrm is shown in Fig. 4. s Logic gtes C 1 C D1 D1' D D3 S 1 S S 3 S 4 Boolen equtions re listed below. S1= D CB +D C B (9) S= D CA +D B A+D C B (10) S3= C B A +CBA+D (11) S4= C B +CB+D (1) S1 = C B +CB+D (13) S = C B A +CBA+D (14) S3 = DCA +DB A+DC B (15) S4 = DCB +DC B (16) Like the five CMLI, this proposed system lso cn produce five output with the help of flip flops nd the logic gtes. The simultion output of proposed five diode clmped multi is shown in Fig. 5. C3 D' S 1 ' S ' C4 D3' S 3 ' S 4 ' o Fig. 4. bsed five diode clmped multi This proposed method cn produce five output s. The s re V dc, V dc, 0V dc, -V dc, -V dc. The switching stte is shown in tble. Tble Switching sttes of five Diode clmped multi Fig. 5. Simultion output of bsed five Diode clmped multi The THD nlysis for five diode clmped multi is shown in Fig. 6. Switching sttes S1 S S3 S4 S1 S S3 S4 voltge In the of, the upper four switches will be turned ON. For, the upper switches S to S4 nd the lower switch S1 should be turned ON. For 0, turn ON the upper switches S3, S4 nd the lower switches S1, S. In the of, the upper switch S4 nd the lower switches S1 to S3 must be turned ON. For -, the lower four switches will be turned ON. The Fig. 6. THD nlysis for bsed five DCMLI. 4. Five Flying Cpcitor multi using s The next proposed topology is five Flying 3

4 Cpcitor Multi Inverter (FCMLI) using flip flops nd logic gtes. The schemtic digrm of this proposed method is shown in Fig. 7. S 1 S S 3 S= C B A +CBA+D (18) S3= D CA +D B A+D C B (19) S4= D CB +D C B (0) S1 = C B +CB+D (1) S = C B A +CBA+D () S3 = DCA +DB A+DC B (3) S4 = DCB +DC B (4) The simultion output of this proposed method is shown in Fig. 8. S 4 s Logic gtes C 3 C C 1 S 1 ' S ' S 3 ' o Fig. 7. bsed five flying cpcitor multi The switching sttes of the bove proposed method is shown in tble 3. These switching sttes re given s the input in the form of Boolen eqution s the bove two proposed topologies. Tble 3 Switching sttes of five flying cpcitor multi S 4 ' Fig. 8. Simultion output of bsed five flying cpcitor multi The totl hrmonic distortion nlysis of this five flying cpcitor multi topology is shown in Fig. 9. THD= V +V +...+V V1 3 n (5) Switching sttes S1 S S3 S4 S1 S S3 S4 voltge To obtin, the upper four switches will be turned ON. For, turn ON the upper three switches S1 to S3 nd the lower switch S1. In the of 0 the upper switches S1, S nd the lower switches S1, S should be turned ON. For the upper switch S1 nd lower switches S1, S, S3 must be turned ON. To get - the lower four switches will be turned ON nd the remining switches should be turned OFF. The Boolen equtions of proposed method is, S1= C B +CB+D (17) Fig. 9. THD nlysis for bsed five FCMLI. Tble 4 Prmeter of proposed three topologies. Topology Totl Hrmonic Distortion bsed five CMLI bsed five DCMLI bsed five FCMLI 0.44% 0.61% 0.44% RMS vlue

5 The bove tble represents the totl hrmonic distortion nd the RMS vlue of the three proposed topologies. These THD vlues re lower thn the conventionl topologies. Vp V RMS = (6) 5. Conclusion In this pper flip flop bsed multi topologies re presented. The topologies re five cscded multi, diode clmped multi nd flying cpcitor multi. By using the flip flops nd logic gtes, the proposed topologies cn synthesize high qulity output voltge ner to sinusoidl wve. The circuit configurtion is simple nd esy to control. This method is minly used to reduce the totl hrmonic distortion (THD) nd lso used to increse the performnce of the system. References 1. Bhrtkr, Schin S, Bhoyr Rju R, Khdtre Srng A: Anlysis of three phse cscded H-bridge multi for symmetricl & symmetricl configurtion. In: Proceedings of the First Interntionl Conference on Automtion, Control, nergy nd Systems (ACS), pp.1-6, Khoun jhn, Hossein, Bnei, Mohmd Rez, Tlei Mobrki, Seedollh: Combined H-bridge cells cscded trnsformers multi. In: Proceedings of the 5th Conference on Power lectronics, Drive Systems nd Technologies (PDSTC), pp , K. Sudheer Kumr,. Mohn, Ch. Rjesh Kumr, K. Lkshmi Gnesh: New Multi Inverter Topology with Reduced Switching Devices for Hybrid lectric Vehicles. In: Proceedings of the Interntionl Journl of Scientific & ngineering Reserch, Vol. 4, no.3, Mrch Ayoub Kvousi, Behrooz Vhidi, Rez Slehi, Mohmmd zem Bkhshizdeh, Neem Frokhni nd S.Hmid Fthi: Appliction of the Bee Algorithm for Selective Hrmonic limintion Strtegy in Multi Inverters. In: Proceedings of the I Trnsctions on power electronics, 01, vol. 7, no. 4, pp Dmoun Ahmdi, KeZou, Cong Li, Yi Hung nd Jin Wng: A Universl Selective Hrmonic limintion Method for High-Power Inverters. In: Proceedings of the I Trnsctions on power electronics, 011, vol. 6, no. 10, pp FeteFilho, Leon M. Tolbert, Yue Co nd BurkOzpineci: Rel-Time Selective Hrmonic Minimiztion for Multi Inverters Connected to Solr Pnels Using Artificil Neurl Network Angle Genertion. In: Proceedings of the I Trnsctions on industry pplictions, 011, vol. 47, no. 5, pp Mlinowski, M, Gopkumr, K., Rodriguez, J. Pérez, M.A.: A Survey on Cscded Multi Inverters. In: Proceedings of the I Trnsctions on Industril lectronics, July 010, vol.57, no.7, pp Filho, F:11-Level cscded H-bridge grid-tied interfce with solr pnels. In: Proceedings of the Applied Power lectronics Conference nd xposition (APC), Feb 010, pp Villnuev, : Control of Single-Phse Cscded H- Bridge Multi Inverter for Grid-Connected Photovoltic Systems. In: Proceedings of the I Trnsctions on Industril lectronics, Nov 009, vol. 56, no. 11, pp Hiwen Liu, Leon M. Tolbert, Surin Khomfoi, Burk Ozpineci, Zhong Du: Hybrid cscded Multi Inverter with PWM Control Method. In: Proceeding of the I, 008, , pp Dher.S, Schmid.J, Fernndo L. nd. Antunes.M: Multi topologies for stnd-lone PV systems. In: Proceedings of the I Trnsctions on Industril lectronics, July 008, Vol. 5, no.7, pp Json R. Wells, XinGengPtrick L. Chpmn Philip T. Kreinnd Brett M. Nee: Modultion-Bsed Hrmonic limintion. In: Proceedings of the I Trnsctions on power electronics, 007, vol., no. 1, pp José Rodríguez, Jih-Sheng Li, Fng Zheng Peng, Fellow Senior Member, I: Multi Inverters: A Survey Topologies, Controls, nd Applictions. In: Proceedings of the I Trnsctions on Industril lectronics, July 00, Vol. 49, no. 4, pp S. Sirisukprsert, J.-S. Li, nd T.-H. Liu: Optimum hrmonic reduction with wide rnge of modultion indices for multi converters. In: Proceedings of the I Trnsctions on Industril lectronics, Aug 00, vol. 49, no. 4, pp