Quad Precision, High Speed Operational Amplifier OP467

Transcription

1 Quad Precision, High Speed Operational Amplifier OP67 FEATURES High slew rate: 7 V/μs Wide bandwidth: 8 MHz Fast settling time: < ns to.% Low offset voltage: <5 μv Unity-gain stable Low voltage operation: ±5 V to ±5 V Low supply current: < ma Drives capacitive loads APPLICATIONS High speed image display drivers High frequency active filters Fast instrumentation amplifiers High speed detectors Integrators Photo diode preamps GENERAL DESCRIPTION The OP67 is a quad, high speed, precision operational amplifier. It offers the performance of a high speed op amp combined with the advantages of a precision op amp in a single package. The OP67 is an ideal choice for applications where, traditionally, more than one op amp was used to achieve this level of speed and precision. The internal compensation of the OP67 ensures stable unitygain operation, and it can drive large capacitive loads without oscillation. With a gain bandwidth product of 8 MHz driving a 3 pf load, output slew rate is 7 V/μs, and settling time to.% in less than ns, the OP67 provides excellent dynamic accuracy in high speed data acquisition systems. The channel-to-channel separation is typically 6 db at MHz. The dc performance of the OP67 includes less than.5 mv of offset, a voltage noise density below 6 nv/ Hz, and a total supply current under ma. The common-mode rejection ratio (CMRR) is typically 85 db. The power supply rejection ratio (PSRR) is typically 7 db. PSRR is maintained to better than db with input frequencies as high as MHz. The low offset and drift plus high speed and low noise make the OP67 usable in applications such as high speed detectors and instrumentation. The OP67 is specified for operation from ±5 V to ±5 V over the extended industrial temperature range ( C to +85 C) and is available in a -lead PDIP, a -lead CERDIP, a 6-lead SOIC, and a -terminal LCC. Contact your local sales office for the MIL-STD-883 data sheet and availability. Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. OUT A IN A +IN A V+ +IN B IN B OUT B NC PIN CONFIGURATIONS + OUT A OUT D IN A + 3 IN D +IN A 3 +IN D V+ OP67 V +IN B 5 +IN C IN B 6 9 IN C OUT B 7 8 OUT C Figure. Simplified Schematic One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved. + Figure. -Lead CERDIP (Y Suffix) and -Lead PDIP (P Suffix) OP OUT D IN D +IN D V +IN C IN C OUT C NC NC = NO CONNECT Figure. 6-Lead SOIC (S Suffix) IN A OUT A NC OUT D IN D 3 9 +IN A NC 5 OP67 V+ 6 (TOP VIEW) NC 7 +IN B IN B OUT B NC OUT C IN C 8 +IN D 7 NC 6 V 5 NC +IN C NC = NO CONNECT Figure 3. -Terminal LCC (RC Suffix) V+ +IN OUT IN V 3-3-3

2 TABLE OF CONTENTS Features... Applications... General Description... Pin Configurations... Revision History... Specifications... 3 Electrical Characteristics... 3 Wafer Test Limits... 5 Absolute Maximum Ratings... 6 Thermal Resistance... 6 Dice Characteristics... 6 ESD Caution... 6 Typical Performance Characteristics... 7 Applications Information... 3 Output Short-Circuit Performance... 3 Unused Amplifiers... 3 PCB Layout Considerations... 3 Grounding... 3 Power Supply Considerations... 3 Signal Considerations... 3 Phase Reversal... Saturation Recovery Time... High Speed Instrumentation Amplifier... MHz Biquad Band-Pass Filter... 5 Fast I-to-V Converter... 6 OP67 SPICE Marco-Model... 7 Outline Dimensions... 9 Ordering Guide... REVISION HISTORY / Rev. H to Rev. I Deleted Endnote From Table /9 Rev. G to Rev. H Changes to Table... 6 /9 Rev. F to Rev. G Changes to Power Supply Considerations Section /7 Rev. E to Rev. F Updated Format... Universal Changes to General Description... Changes to Table... 3 Changes to Table... Changes to Table Updated Outline Dimensions... 9 Changes to Ordering Guide... 3/ Rev. D to Rev. E Changes to TPC... 5 Changes to Ordering Guide... Updated Outline Dimensions... 6 / Rev. C to Rev. D Footnote added to Power Supply... Footnote added to Max Ratings... Edits to Power Supply Considerations Section... Rev. I Page of

3 SPECIFICATIONS ELECTRICAL VS = ±5. V, TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS..5 mv C TA +85 C mv Input Bias Current IB VCM = V 5 6 na VCM = V, C TA +85 C 5 7 na Input Offset Current IOS VCM = V na VCM = V, C TA +85 C 5 na Common-Mode Rejection CMR VCM = ± V 8 9 db CMR VCM = ± V, C TA +85 C 8 88 db Large Signal Voltage Gain AVO RL = kω db RL = kω, C TA +85 C 77.5 db Offset Voltage Drift ΔVOS/ΔT 3.5 μv/ C Bias Current Drift ΔIB/ΔT. pa/ C Long-Term Offset Voltage Drift ΔVOS/ΔT 75 μv OUTPUT CHARACTERISTICS Output Voltage Swing VO RL = kω ±3. ±3.5 V RL = kω, C TA +85 C ±.9 ±3. V POWER SUPPLY Power Supply Rejection Ratio PSRR ±.5 V VS ±8 V 96 db C TA +85 C 86 5 db Supply Current ISY VO = V 8 ma VO = V, C TA +85 C 3 ma Supply Voltage Range VS ±.5 ±8 V DYNAMIC PERFORMANCE Gain Bandwidth Product GBP AV = +, CL = 3 pf 8 MHz Slew Rate SR VIN = V step, RL = kω, CL = 3 pf AV = V/μs AV = 35 V/μs Full-Power Bandwidth BWρ VIN = V step.7 MHz Settling Time ts To.%, VIN = V step ns Phase Margin θ 5 Degrees Input Capacitance Common Mode. pf Differential. pf NOISE PERFORMANCE Voltage Noise en p-p f =. Hz to Hz.5 μv p-p Voltage Noise Density en f = khz 6 nv/ Hz Current Noise Density in f = khz.8 pa/ Hz Long-term offset voltage drift is guaranteed by hrs. Life test performed on three independent wafer lots at 5 C, with an LTPD of.3. Rev. I Page 3 of

4 @ VS = ±5. V, TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS.3.5 mv C TA +85 C mv Input Bias Current IB VCM = V 5 6 na VCM = V, C TA +85 C 5 7 na Input Offset Current IOS VCM = V na VCM = V, C TA +85 C 5 na Common-Mode Rejection CMR VCM = ±. V db CMR VCM = ±. V, C TA +85 C 76 8 db Large Signal Voltage Gain AVO RL = kω 8 83 db RL = kω, C TA +85 C 7 db Offset Voltage Drift ΔVOS/ΔT 3.5 μv/ C Bias Current Drift ΔIB/ΔT. pa/ C OUTPUT CHARACTERISTICS Output Voltage Swing VO RL = kω ±3. ±3.5 V RL = kω, C TA +85 C ±3. ±3. V POWER SUPPLY Power Supply Rejection Ratio PSRR ±.5 V VS ±5.5 V 9 7 db C TA +85 C 83 5 db Supply Current ISY VO = V 8 ma VO = V, C TA +85 C ma DYNAMIC PERFORMANCE Gain Bandwidth Product GBP AV = + MHz Slew Rate SR VIN = 5 V step, RL = kω, CL = 39 pf AV = + 9 V/μs AV = 9 V/μs Full-Power Bandwidth BWρ VIN = 5 V step.5 MHz Settling Time ts To.%, VIN = 5 V step 8 ns Phase Margin θ 5 Degrees NOISE PERFORMANCE Voltage Noise en p-p f =. Hz to Hz.5 μv p-p Voltage Noise Density en f = khz 7 nv/ Hz Current Noise Density in f = khz.8 pa/ Hz Rev. Page of

5 WAFER TEST VS = ±5. V, TA = 5 C, unless otherwise noted. Table 3. Parameter Symbol Conditions Limit Unit Offset Voltage VOS ±.5 mv max Input Bias Current IB VCM = V 6 na max Input Offset Current IOS VCM = V na max Input Voltage Range ± V min/max Common-Mode Rejection Ratio CMRR VCM = ± V 8 db min Power Supply Rejection Ratio PSRR V = ±.5 V to ±8 V 96 db min Large Signal Voltage Gain AVO RL = kω 83 db min Output Voltage Range VO RL = kω ±3. V min Supply Current ISY VO = V, RL = ma max Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult sales to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. Guaranteed by CMR test. Rev. Page 5 of

6 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage ±8 V Input Voltage ±8 V Differential Input Voltage ±6 V Output Short-Circuit Duration Limited Storage Temperature Range -Lead CERDIP and -Terminal LCC 65 C to +75 C -Lead PDIP and 6-Lead SOIC 65 C to +5 C Operating Temperature Range OP67A 55 C to +5 C OP67G C to +85 C Junction Temperature Range -Lead CERDIP and -Terminal LCC 65 C to +75 C -Lead PDIP and 6-Lead SOIC 65 C to +5 C Lead Temperature (Soldering, 6 sec) 3 C Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. For supply voltages less than ±8 V, the absolute maximum input voltage is equal to the supply voltage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Package Type θja θjc Unit -Lead CERDIP (Y) 9 C/W -Lead PDIP (P) C/W 6-Lead SOIC (S) 88 3 C/W -Terminal LCC (RC) C/W θja is specified for the worst-case conditions, that is, θja is specified for device in socket for CERDIP, PDIP, and LCC packages, and θja is specified for device soldered in circuit board for the SOIC package. DICE CHARACTERISTICS OUT A OUT D IN A 3 IN D +IN A 3 +IN D V+ V +IN B 5 +IN C IN B T B T C IN C OU 3-5 OU Figure 5.. Inch. Inch DIE Size,, sq. mils, Substrate Connected to V+, 65 Transistors ESD CAUTION Rev. Page 6 o f

7 TYPICAL PERFORMANCE CHARACTERISTICS R L = MΩ C L = 3pF 8 T A = 5 C OPEN-LOOP GAIN (db) 5 3 PHASE GAIN PHASE SHIFT (Degrees) IMPEDANCE (Ω) 6 A VCL = + A VCL = + k k k M M M Figure 6. Open-Loop Gain, Phase vs. Frequency 3-6 A VCL = + k k k M Figure 9. Closed-Loop Output Impedance vs. Frequency CLOSED-LOOP GAIN (db) 6 T A = 5 C GAIN ERROR (db) V S = ±5V k k M M M Figure 7. Closed-Loop Gain vs. Frequency k M M Figure. Gain Error vs. Frequency A VCL = OPEN-LOOP GAIN (V/mV) T A = +5 C 5 T A = +5 C T A = 55 C 5 ±5 ± ±5 ± SUPPLY VOLTAGE (V) Figure 8. Open-Loop Gain vs. Supply Voltage 3-8 MAXIMUM OUTPUT SWING (V) T A = 5 C R L = kω A VCL = + k k k M M Figure. Maximum VOUT Swing vs. Frequency 3- Rev. Page 7 of

8 MAXIMUM OUTPUT SWING (V) 8 6 V S = ±5V T A = 5 C R L = kω A VCL = + A VCL = OVERSHOOT (%) R L = kω V VIN = mv p-p A VCL = + A VCL = k k k M M Figure. Maximum VOUT Swing vs. Frequency LOAD CAPACITANCE (pf) Figure 5. Small Signal Overshoot vs. Load Capacitance 3-5 COMMON-MODE REJECTION (V) 8 6 T A = 5 C OVERSHOOT (%) R L = kω V VIN = mv p-p A VCL = + A VCL = k k k M M Figure 3. Common-Mode Rejection vs. Frequency LOAD CAPACITANCE (pf) Figure 6. Small Signal Overshoot vs. Load Capacitance 3-6 POWER SUPPLY REJECTION (db) 8 6 k k k M T A = 5 C 3- GAIN (db) pf k k M pf C IN = NETWORK ANALYZER M 5pF pf M 3-7 Figure. Power-Supply Rejection vs. Frequency Figure 7. Noninverting Gain vs. Capacitive Loads Rev. Page 8 of

9 CHANNEL SEPARATION (db) k k k M M M Figure 8. Channel Separation vs. Frequency 3-8 V OUT ERROR (mv) 3 3 V IN = ±5V C L = 5pF 3 5 TIME (ns) Figure. Settling Time, Negative Edge 3- UT CURRENT NOISE DENSITY (pa/ Hz) INP 8 6 ±5V V S 5V k 3-9 V OUT ERROR (mv) TIME (ns) V IN = ±5V C L = 5pF 3- Figure 9. Input Current Noise Density vs. Frequency Figure. Settling Time, Positive Edge 5 T A = 5 C TAGE NOISE DENSITY (nv/ Hz) INPUT VOLTAGE RANGE (V) 5 5 VOL.. k k 3-5 ±5 ± ±5 ± SUPPLY VOLTAGE (V) 3-3 Figure. Voltage Noise Density vs. Frequency Figure 3. Input Voltage Range vs. Supply Voltage Rev. Page 9 of

10 5 3 V S = ±5V V S = ±5V R L = kω C L = 5pF 5 T A = 5 C 5 OP AMPS GAIN (db) V S = ±5V V S = ±5V UNITS k k M M M INPUT OFFSET VOLTAGE (V OS µv) 3-7 Figure. Noninverting Gain vs. Supply Voltage Figure 7. Input Offset Voltage Distribution T A = 5 C 5 V S = ±5V T A = 5 C 5 OP AMPS OUTPUT SWING (V) 8 6 POSITIVE SWING NEGATIVE SWING UNITS 3 k LOAD RESISTANCE (Ω) k INPUT OFFSET VOLTAGE (V OS µv) 3-8 Figure 5. Output Swing vs. Load Resistance Figure 8. Input Offset Voltage Distribution 5 T A = 5 C 5 T A = 5 C 5 OP AMPS OUTPUT SWING (V) 3 POSITIVE SWING NEGATIVE SWING UNITS 3 k LOAD RESISTANCE (Ω) Figure 6. Output Swing vs. Load Resistance k TC V OS (µv/ C) Figure 9. TC VOS Distribution 3-9 Rev. Page of

11 5 V S = ±5V T A = 5 C 5 OP AMPS 35 3 V S = ±5V R L = kω A VCL =+ UNITS 3 SLEW RATE (V/µs) 5 5 +SR SR TC V OS (µv/ C) TEMPERATURE ( C) 3-33 Figure 3. TC VOS Distribution Figure 33. Slew Rate vs. Temperature PHASE MARGIN (Degrees) V S = ±5V R L = kω GBW ФM IN BANDWIDTH PRODUCT (MHz) SLEW RATE (V/µs) R L = kω A VCL = SR +SR GA TEMPERATURE ( C) TEMPERATURE ( C) Figure 3. Phase Margin and Gain Bandwidth vs. Temperature Figure 3. Slew Rate vs. Temperature 35 V S = ±5V R L = kω A VCL = 35 R L = kω A VCL =+ SLEW RATE (V/µs ) SR +SR SLEW RATE (V/µs) SR +SR TEMPERATURE ( C) Figure 3. Slew Rate vs. Temperature TEMPERATURE ( C) Figure 35. Slew Rate vs. Temperature 3-35 Rev. Page of

12 UTPUT STEP FOR ±5V SUPPLY (V) O %.%.%.% R F = 5kΩ T A =5 C UTPUT STEP FOR ±5V SUPPLY (V) O 3-36 INPUT BIAS CURRENT (na) V S =±5V SETTLING TIME (ns) TEMPERATURE ( C) Figure 36. Output Step vs. Settling Time Figure 38. Input Bias Current vs. Temperature 5 V S =±5V SUPPLY CURRENT (ma) 8 6 T A = +5 C T A = +5 C T A = 55 C INPUT OFFSET CURRENT (na) 5 5 ±5 ± ±5 ± SUPPLY VOLTAGE (V) Figure 37. Supply Current vs. Supply Voltage TEMPERATURE ( C) Figure 39. Input Offset Current vs. Temperature 3-39 Rev. Page of

13 APPLICATIONS INFORMATION OUTPUT SHORT-CIRCUIT PERFORMANCE To achieve a wide bandwidth and high slew rate, the OP67 output is not short-circuit protected. Shorting the output to ground or to the supplies may destroy the device. For safe operation, the output load current should be limited so that the junction temperature does not exceed the absolute maximum junction temperature. The maximum internal power dissipation can be calculated by TJ max T P D = A θ JA where: TJ and TA are junction and ambient temperatures, respectively. PD is device internal power dissipation. θja is the packaged device thermal resistance given in the data sheet. UNUSED AMPLIFIERS It is recommended that any unused amplifiers in the quad package be connected as a unity-gain follower with a kω feedback resistor with noninverting input tied to the ground plain. PCB LAYOUT CONSIDERATIONS Satisfactory performance of a high speed op amp largely depends on a good PCB layout. To achieve the best dynamic performance, follow the high frequency layout technique. GROUNDING A good ground plain is essential to achieve the optimum performance in high speed applications. It can significantly reduce the undesirable effects of ground loops and IR drops by providing a low impedance reference point. Best results are obtained with a multilayer board design with one layer assigned to the ground plain. To maintain a continuous and low impedance ground, avoid running any traces on this layer. POWER SUPPLY CONSIDERATIONS In high frequency circuits, device lead length introduces an inductance in series with the circuit. This inductance, combined with stray capacitance, forms a high frequency resonance circuit. Poles generated by these circuits cause gain peaking and additional phase shift, reducing the phase margin of the op amp and leading to an unstable operation. A practical solution to this problem is to reduce the resonance frequency low enough to take advantage of the power supply rejection of the amplifier. This is easily done by placing capacitors across the supply line and the ground plane as close as possible to the device pin. Because capacitors also have internal parasitic components, such as stray inductance, selecting the right capacitor is important. To be effective, they should have low impedance over the frequency range of interest. Tantalum capacitors are an excellent choice for their high capacitance/size ratio, but their effective series resistance (ESR) increases with frequency making them less effective. Rev. Page 3 of OP67 On the other hand, ceramic chip capacitors have excellent ESR and effective series inductance (ESL) performance at higher frequencies, and because of their small size, they can be placed very close to the device pin, further reducing the stray inductance. Best results are achieved by using a combination of these two capacitors. A 5 μf to μf tantalum parallel capacitor with a. μf ceramic chip capacitor is recommended. If additional isolation from high frequency resonances of the power supply is needed, a ferrite bead should be placed in series with the supply lines between the bypass capacitors and the power supply. Note that addition of the ferrite bead introduces a new pole and zero to the frequency response of the circuit and could cause unstable operation if it is not selected properly. +V S + µf TANTALUM.µF CERAMIC CHIP.µF CERAMIC CHIP µf TANTALUM V S Figure. Recommended Power Supply Bypass SIGNAL CONSIDERATIONS Input and output traces need special attention to assure a minimum stray capacitance. Input nodes are very sensitive to capacitive reactance, particularly when connected to a high impedance circuit. Stray capacitance can inject undesirable signals from a noisy line into a high impedance input. Protect high impedance input traces by providing guard traces around them, which also improves the channel separation significantly. Additionally, any stray capacitance in parallel with the input capacitance of the op amp generates a pole in the frequency response of the circuit. The additional phase shift caused by this pole reduces the gain margin of the circuit. If this pole is within the gain range of the op amp, it causes unstable performance. To reduce these undesirable effects, use the lowest impedance where possible. Lowering the impedance at this node places the poles at a higher frequency, far above the gain range of the amplifier. Stray capacitance on the PCB can be reduced by making the traces narrow and as short as possible. Further reduction can be realized by choosing a smaller pad size, increasing the spacing between the traces, and using PCB material with a low dielectric constant insulator (dielectric constant of some common insulators: air =, Teflon =., and FR =.7, with air being an ideal insulator). Removing segments of the ground plane directly under the input and output pads is recommended. 3-

14 Outputs of high speed amplifiers are very sensitive to capacitive loads. A capacitive load introduces a pair of pole and zero to the frequency response of the circuit, reducing the phase margin, leading to unstable operation or oscillation. 9 DLY 9.8µs Generally, it is good design practice to isolate the output of the amplifier from any capacitive load by placing a resistor between the output of the amplifier and the rest of the circuits. A series resistor of Ω to Ω is normally sufficient to isolate the output from a capacitive load. The OP67 is internally compensated to provide stable operation and is capable of driving large capacitive loads without oscillation. Sockets are not recommended because they increase the lead inductance/capacitance and reduce the power dissipation of the package by increasing the thermal resistance of the leads. If sockets must be used, use Teflon or pin sockets with the shortest possible leads. % 9 5V 5V ns Figure. Saturation Recovery Time, Positive Rail DLY.86µs 3- PHASE REVERSAL The OP67 is immune to phase reversal; its inputs can exceed the supply rails by a diode drop without any phase reversal. OUTPUT 9 INTPUT % V V ΔV 5.8V Figure. No Phase Reversal (AV = +) µs SATURATION RECOVERY TIME The OP67 has a fast and symmetrical recovery time from either rail. This feature is very useful in applications such as high speed instrumentation and measurement circuits, where the amplifier is frequently exposed to large signals that overload the amplifier. 3- % 5V 5V ns Figure 3. Saturation Recovery Time, Negative Rail HIGH SPEED INSTRUMENTATION AMPLIFIER The OP67 performance lends itself to a variety of high speed applications, including high speed precision instrumentation amplifiers. Figure represents a circuit commonly used for data acquisition, CCD imaging, and other high speed applications. The circuit gain is set by RG. A kω resistor sets the circuit gain to ; for unity gain, remove RG. For any other gain settings, use the following formula G = /RG (Resistor Value is in kω) RC is used for adjusting the dc common-mode rejection, and CC is used for ac common-mode rejection adjustments. V IN C C 3-3 kω kω kω R G kω kω OUTPUT kω.9kω kω 5pF R C Ω T +V IN Figure. A High Speed Instrumentation Amplifier 3- Rev. Page of

15 .5mV.5mV MHz BIQUAD BAND-PASS FILTER The circuit in Figure 8 is commonly used in medical imaging ultrasound receivers. The 3 MHz bandwidth is sufficient to accurately produce the MHz center frequency, as the measured response shows in Figure 9. When the bandwidth of the op amp is too close to the center frequency of the filter, the internal phase shift of the amplifier causes excess phase shift at MHz, which alters the response of the filter. In fact, if the chosen op amp has a bandwidth close to MHz, the combined phase shift of the three op amps causes the loop to oscillate. Careful consideration must be given to the layout of this circuit as with any other high speed circuit. V Step Input (Negative Slope) If the phase shift introduced by the layout is large enough, it can alter the circuit performance, or worse, cause oscillation..% V STEP NEG SLOPE Figure 5. Instrumentation Amplifier Settling Time to.% for a.% V STEP V S =±5V POS SLOPE 3-5 R6 kω C 5pF.5mV.5mV Figure 6. Instrumentation Amplifier Settling Time to.% for a V Step Input (Positive Slope) TO INPUT TO IN-AMP OUTPUT kω kω 6.9Ω +V S V S + + AD967 kω 59Ω Figure 7. Settling Time Measurement Circuit ERROR TO SCOPE kω GAIN (db) / OP67 3 R 3kΩ V IN R kω / OP67 V OUT R3 kω R kω / OP67 Figure 8. MHz Biquad Filter R5 kω C 5pF / OP67 k k M M M Figure 9. Biquad Filter Response Rev. Page 5 of

16 +V +5V V DD V REF A DAC88 DGND V REF C 8 7 +V OUT A OP67 3 C pf 3 5 R FB A I OUT A R FB C I OUT C I OUT A/ I OUT C/ I OUT B I OUT D 6 5 C3 pf 3 OP67 OUT D +5V 6 I OUT B I OUT D 3 OUT B.µF 7.µF 6 OP67 5 5V C pf 7 R FB B R FB D 8 V REF B V REF D +V 9 DB (LSB) DS +V DB DB DS 9 R/W 8 DIGITAL CONTROL SIGNALS C pf 9 OP67 8 OUT C DB3 A/B 7 3 DB (MSB) DB7 6 DB5 DB6 5 Figure 5. Quad DAC Unipolar Operation 3-5 FAST I-TO-V CONVERTER The fast slew rate and fast settling time of the OP67 are well suited to the fast buffers and I-to-V converters used in a variety of applications. The circuit in Figure 5 is a unipolar quad DAC consisting of only two ICs. The current output of the DAC88 is converted to a voltage by the OP67 configured as an I-to-V converter. This circuit is capable of settling to.% within ns. Figure 5 and Figure 5 show the full-scale settling time of the outputs. To obtain reliable circuit performance, keep the traces from the IOUT of the DAC to the inverting inputs of the OP67 short to minimize parasitic capacitance. 9 % V 5mV 5.ns ns ns Figure 5. Rising Edge Output Settling Time 9 DAC88 R FB I OUT 3pF I-V OP67 kω DC OFFSET kω AD87 kω 5kΩ 6Ω % 6.kΩ 3-53 V 5mV ns 3-5 Figure 53. DAC VOUT Settling Time Circuit Figure 5. Falling Edge Output Settling Time Rev. Page 6 of

17 OP67 SPICE MARCO-MODEL Node assignments noninverting input inverting input positive supply negative supply output. SUBCKT OP INPUT STAGE I 5 E 3 CIN E IOS 5E 9 Q 5 8 QN Q QN R R R R EOS 7 POLY () (,) 5E 6 EREF 98 (,) GAIN STAGE AND DOMINANT POLE AT.5 khz R E6 C E G 98 (5,6) E 3 V V 5. 6 D DX D DX RC 8. E3 CC 8 7 E COMMON-MODE STAGE WITH ZERO AT.6 khz ECM 3 98 POLY () (, ) (,) R8 3 E6 R C E POLE AT E6 R 5 98 E6 C E 5 G 98 5 (,) E 6 OUTPUT STAGE ISY E 3 RMP E3 RMP E3 RO 99 6 RO 6 5 L 6 7 E 7 GO 6 99 (99,5) 5E 3 GO 5 6 (5,5) 5E 3 G 3 5 (5,6) 5E 3 G5 5 (6,5) 5E 3 V3 6 5 V 6 5 D3 5 DX D 5 DX D DX D6 99 DX D7 5 3 DY D8 5 DY MODELS USED. MODEL QN NPN (BF=33.333E3). MODEL DX D. MODEL DY D (BV=5). ENDS OP67 Rev. Page 7 of

18 G 99 I SY RMP D R D V + C RMP 98 3 E + REF G D7 D8 G5 D5 5 5 D6 V3 + G G R R L R3 5 R 6 + V N Q Q 7 C3 I OS 8 9 C IN R5 R6 G R7 C 3 R8 E + CM R9 N+ + E 98 OS D E + REF I V D R C 8 C C Figure 5. SPICE Macro-Model Output Stage Figure 55. SPICE Macro-Model Input and Gain Stage Rev. Page 8 of

19 OUTLINE DIMENSIONS.775 (9.69).75 (9.5).735 (8.67). (5.33) MAX.5 (3.8).3 (3.3). (.79). (.56).8 (.6). (.36). (.5) BSC.7 (.78).5 (.7).5 (.) (7.).5 (6.35). (6.).5 (.38) MIN SEATING PLANE.5 (.3) MIN.6 (.5) MAX.5 (.38) GAUGE PLANE.35 (8.6).3 (7.87).3 (7.6).3 (.9) MAX.95 (.95).3 (3.3).5 (.9). (.36). (.5).8 (.) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 56. -Lead Plastic Dual In-Line Package [PDIP] (N-) P-Suffix Dimensions shown in inches and (millimeters) 766-A.5 (.3) MIN.98 (.9) MAX (7.87). (5.59) PIN. (5.8) MAX. (5.8).5 (3.8).3 (.58). (.36). (.5) BSC.785 (9.9) MAX.7 (.78).3 (.76).6 (.5).5 (.38).5 (3.8) MIN SEATING PLANE.3 (8.3).9 (7.37) 5.5 (.38).8 (.) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 57. -Lead Ceramic Dual In-Line Package [CERDIP] (Q-) Y-Suffix Dimensions shown in inches and (millimeters) Rev. I Page 9 of

20 .5 (.3). (.3976) (.99) 7. (.93) 8.65 (.93). (.3937).3 (.8). (.39) COPLANARITY.7 (.5) BSC.65 (.3).35 (.95)..5 (.) SEATING PLANE.33 (.3).3 (.). (.79) 8.75 (.95).5 (.98) 5.7 (.5). (.57) COMPLIANT TO JEDEC STANDARDS MS-3-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-6) S-Suffix Dimensions shown in millimeters and (inches) 377-B.358 (9.9).3 (8.69) SQ. (.5).6 (.63).358 (9.9) MAX SQ.88 (.).5 (.37).75 (.9) REF.95 (.).75 (.9). (.8).7 (.8) R TYP.75 (.9) REF.55 (.).5 (.) BOTTOM VIEW. (5.8) REF. (.5) REF (3.8) BSC.5 (.38) MIN.8 (.7). (.56).5 (.7) BSC 5 TYP CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 59. -Terminal Ceramic Leadless Chip Carrier [LCC] (E--) RC-Suffix Dimensions shown in inches and (millimeters) 6-A ORDERING GUIDE Model Temperature Range Package Description Package Option OP67GP C to +85 C -Lead PDIP N- OP67GPZ C to +85 C -Lead PDIP N- OP67GS C to +85 C 6-Lead SOIC_W RW-6 OP67GS-REEL C to +85 C 6-Lead SOIC_W RW-6 OP67GSZ C to +85 C 6-Lead SOIC_W RW-6 OP67GSZ-REEL C to +85 C 6-Lead SOIC_W RW-6 OP67ARC/883C 55 C to +5 C -Terminal LCC E-- OP67AY/883C 55 C to +5 C -Lead CERDIP Q- OP67GBC Die Z = RoHS Compliant Part. 993 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D3--/(I) Rev. I Page of