Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance

Transcription

1 Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance Randy Morris Ϯ, Avinash Kodi Ϯ and Ahmed Louri School of Electrical Engineering and Computer Science, Ohio University Ϯ Department of Electrical and Computer Engineering, University of Arizona th International Symposium on Microarchitecture (MICRO) December 1 December 5, 2012 Vancouver BC, Canada

2 Talk Outline Motivation & Background R-3PO: Architecture & Reconfiguration Performance Analysis Conclusions 2

3 Multicores & Network-on-Chips Tilera core Intel TeraFlops core FERMI (Nvidia) 3 With increasing cores, communication-centric design paradigm is becoming important (Network-on-Chips) Energy for communication is increasing Delivered throughput is decreasing

4 Power (watts) Energy Discrepancy & Throughput Energy discrepancy between computation and global communication with technology scaling Need to reduce global communication energy Relative On-die energy Compute Energy Interconnect Energy Technology (nm) Source: Shekar Borkar, Intel Reduced throughput due to aggressive voltage and clock scaling Need to provide scalable bandwidth without sacrificing performance => Potential solutions: Nanophotonics, 3D Stacking Tile Power: Intel Tera-Flops (65 nm) 1 1 Tflops at 97 W Voltage 1.33 Tflops At 230 W 1. Y. Hoskote, A 5-GHz Mesh Interconnect for A Teraflops Processor, IEEE Computer Society, 2007 pp

5 Nanophotonics & Optical 3D Stacking Nanophotonics offers several advantages: Low energy (7.9 fj/bit ) Small Footprint (~2.5 µm) High Bandwidth (~40 Gbps) CMOS compatibility 1. L. Xu, W. Zhang, Q. Li, J. Chan, H. L. R. Lira, M. Lipson, K. Bergman, "40-Gb/s DPSK Data Transmission Through a Silicon Microring Switch," IEEE Photonics Technology Letters Sasikanth Manipatruni, Kyle Preston, Long Chen, and Michal Lipson, "Ultra-low voltage, ultra-small mode volume silicon microring modulator," Opt. Express 18, (2010) Optical 3D stacking offers several advantages: Shorter interconnect length Higher bandwidth density Optical vias create power-efficient inter-layer communication Layer 2 Layer 1 3. P. Koonath and B. Jalali, Multilayer 3-d photonics in silicon, Opt. Express, vol. 15, pp , A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip multiprocessors, J. Emerg. Technol. Comput. Syst., vol. 7, pp. 1 25, July

6 Recent Work on Photonic NoC, among others Shared-Bus [Cornell, MICRO 06] Circuit Switch [Columbia, NoCs 07] CORONA [HP/Wisconsin, ISCA 08] Processor-DRAM [MIT, Hot Int 08] Firefly [Northwestern, ISCA 09] Phastlane [Cornell, ISCA 09] Flexishare [Northwestern, HPCA 10] Oblivious Router [Cornell, ASPLOS 10] ATAC [MIT, PACT 10] MPNoC [Arizona, DAC 10] Free-Space Architecture [ISCA 10] Optical Proximity [Sun, ISCA 10] PROPEL [Ohio, NoCs 10] System Level Trimming [UC Davis, HPCA 11] Atomic Coherence [Wisconsin/HP, HPCA 11] FeatherWeight [Northwestern/KAIST, MICRO 11] Resilient Microring Design [UCDavis, MICRO 11] Tolerating Process Variations [Pittsburgh, ISCA 12] However, there are several issues not addressed 2D planar connections have waveguide crossings Static network resource allocation Lack of fault tolerance 6

7 Talk Outline Motivation & Background R-3PO: Architecture & Reconfiguration Performance Analysis Conclusions 7

8 R-3PO Architecture Decomposed optical crossbar Reduces optical hardware complexity by having smaller crossbars Reduces crossover losses (~ 0.05 db/crossing) Optical vias Light switched via photonic rings (reduces electrical power) Eases fabrication as optical and electrical dies can be separately grown Reconfiguration of network resources by re-allocating bandwidth Reduces application execution time by monitoring link and buffer utilization Provides fault tolerance as faulty channels are bypassed 8

9 R-3PO Architecture (1/6) Electrical Contact Optical Die Optical Layer 3 Optical Layer 2 Optical Layer 1 Optical Layer 0 External Laser Electrical Die Heat Sink Electro-Optic Transceivers TSVs Core + Cache + MC 9

10 L1 Cache Shared L2 L1 Cache L1 Cache L1 Cache R-3PO Architecture (1/6) Core 0 Core 1 Core 2 Core 3 Electrical Die Heat Sink Core + Cache + MC 10

11 R-3PO Architecture (2/6) Buffer Chain Photodetector TIA Limiting Driver for Amplifier Electronics Off- Chip Laser Micro-ring resonator T x T x T x T x R x R x R x R x λ 1 λ 2 λ 3 λ 4 λ 1 λ 2 λ 3 λ 4 Core A Core B External Laser Electrical Die Heat Sink Electro-Optic Transceivers TSVs Core + Cache + MC 11

12 R-3PO Architecture (3/6) Group 0 Group 1 Group 2 Group 3 External Laser Electrical Die Heat Sink Optical Layer 0 Electro-Optic Transceivers TSVs Core + Cache + MC 12

13 R-3PO Architecture (4/6) Group 0 Group 1 Group 2 Group 3 External Laser Electrical Die Heat Sink Optical Layer 1 Optical Layer 0 Electro-Optic Transceivers TSVs Core + Cache + MC 13

14 R-3PO Architecture (5/6) Group 0 Group 1 Group 2 Group 3 External Laser Electrical Die Heat Sink Optical Layer 2 Optical Layer 1 Optical Layer 0 Electro-Optic Transceivers TSVs Core + Cache + MC 14

15 R-3PO Architecture (6/6) Group 0 Group 1 Electrical Contact Group 2 Group 3 Optical Die Optical Layer 3 Optical Layer 2 Optical Layer 1 Optical Layer 0 External Laser Electrical Die Heat Sink Electro-Optic Transceivers TSVs Core + Cache + MC 15

16 Router Microarchitecture Tile 0 Header Route Computation (RC) IB 0 Token Req + Rel E/O Tx Token capture release To Optical Layer 0 L2 Shared Cache demux Switch Allocator (SA) IB 3 0B 0 Token Req + Rel E/O Tx Token Control O/E Rx MRR Modulators To Optical Layer 3 Token Re-generation From Optical Layer 0 RC BW EO OL OL OL OE S BW D BW RC EO OL OL OL OE S RC: Route Computation BWS: Buffer Write (Source) EO: Electrical to Optical Driver OL: Optical link latency (1-3 cycles) SA BW D SA OE: Optical to Electrical (Dest) mux 0B 3 Token Control BWD: Buffer Write (Dest) SA: Switch Allocation O/E Rx From Optical Layer 3 MRR Filters 16

17 Static Communication Source Layer 2 Group 0 Group 1 Group 2 Group 3 Communication demand between Tile 0 and Tile 15 is high based on application If there are under-utilized links, then the bandwidth can be reallocated to improve the performance 17

18 Network Reconfiguration Source Layer 0 Group 0 Group 1 Group 0 Group 1 Layer 1 Switch point Combine point Layer 1 Group 2 Layer 0 Group 3 Group 2 Group 3 Destination 2x increase in bandwidth is obtained by routing half the data through two other nanophotonic channels 18

19 Reconfiguration Reconfiguration in R-3PO takes place between the different layers as follows: R-3P0-L1: Reconfiguration between Layer0/Layer1 & Layer2/Layer3 R-3P0-LA: Reconfiguration between adjacent layers R-3P0-L2: Reconfiguration between two adjacent layers R-3P0-L3: Reconfiguration between all layers Reconfiguration algorithm monitors network resources Link & Buffer utilization Accomplished with hardware counters & electrical circuitry 19

20 Reconfiguration Algorithm Step 1: Wait for Reconfiguration window, R W t Step 2: RC i sends a request packet to all local tiles requesting Link Util and Buffer Util for previous R W t-1 Step 3: Each hardware counter sends Link Util and Buffer Util statistics from the pervious R W t-1 to RC i Step 4: RC i classifies the link statistic for each hardware counter as: If Link util = 0.0 Not-Utilized: Use β 4 If Link util Lmin Under-Utilized: Use β 3 If Link util L min and Buffer util < B con Normal-Utilized: Use β 2 If Bufferutil > Bcon Over-Utilized: Use β 1 Step 5: Each RC i sends bandwidth available information to RC j, (i j). Step 6: If RC j can use any of the free links then notify RC i of their use, else RC j will forward to next RC j Step 7a: RC i receives response back from RC j and activates corresponding microrings Step 7b: RC j notifies the tiles of additional bandwidth and RC i notifies RC j that the additional bandwidth is now available Step 8: Goto Step 1 20

21 Fault Tolerance Channel faults cause communication breakdown isolating healthy cores due to transceiver failure (Eg., ring resonator failure due to thermal drift or process variation) As redundant channels are available in the decomposed crossbar, fault tolerance can be implemented Augment the reconfiguration algorithm to detect link faults When faults are detected, bandwidth from working links are shared with faulty links to communicate with the isolated core Fault tolerance techniques allow performance to degrade gracefully 21

22 Fault Tolerance Example Group 0 Group 1 Layer 0 Layer 1 Group 0 Group 1 Faulty Link Switch point Combine point Group 2 Group 3 Group 2 Group 3 Bandwidth from Group 0 s interconnects in Layer 0 are switch to the interconnects in Layer 1 that are used to communicate with Group 0 22

23 Talk Outline Motivation & Background R-3PO: Architecture & Reconfiguration Performance Analysis Conclusions 23

24 Performance Analysis Synthetic, SPLASH-2, PARSEC, & SPEC CPU 2006 application traces on a cycle accurate simulator SPLASH-2: FFT, LU, radix, ocean, & water PARSEC: blackscholes, facesim, fluidanimate, freqmin, & streamcluster SPEC CPU 2006: bzip & hmmer Power Analysis Optical Power (micro-ring resonators & laser power) Electrical Power (receiver & router) Compared to the following networks Electrical: Mesh & Flattened-Butterfly Optical: Firefly, Corona, & MPNoC 24

25 Energy Evaluation Pre-Driver and SERDES Buffer Chain Optical Receiver Circuitry & DESERDES Photodetector TIA Limiting Amplifier Driver for Electronics Ring Heating & Ring modulation Laser Power T x T x T x T x R x R x R x R x Ring Heating λ 1 λ 2 λ 3 λ 4 λ 1 λ 2 λ 3 λ 4 Off-Chip Laser Core Core Device Energy Device Energy Ring Heating 2.6 fj/bit Ring modulation 50 fj/bit Pre-Diver 19 fj/bit SERDES 1.5 fj/bit DESERDES 1.5 fj/bit Receiver Circuitry 66 fj/bit C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popović, H. Li, H. Smith, J. Hoyt, F. Kärtner, R. Ram, V. Stojanović, and K. Asanović. "Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics."16th Symposium on High-Performance Interconnects (HOTI-16), Aug

26 System Simulation Parameters R-3PO is compared to the following networks: Mesh, Flattened-Butterfly, Firefly, Corona, & MPNOC Parameter L1/L2 coherence L2 cache size/accos Value MOESI 4MB/16-way L2 access latency (cycles) 4 L1 cache/accoc 64KB/4-way L1 access latency (cycles) 2 Core Frequency (GHz) 5 Threads (core) 2 Issue Policy In-order Memory Size (GB) 4 Memory latency (cycles)

27 Energy per Bit (pj) 2.5 Energy per bit (256 Cores): Uniform % Mesh FB Firefly Corona MPNOC R-3PO-L1 R-3PO-LA R-3PO-L2 R-3PO-L3 Ring modulation Ring heating Laser Back-end circuit Electrical link Router R-3PO reduces energy consumption by 36% 27

28 Speed-Up Application Traffic (64 Cores) blackscholes facesim fluidanimate freqmin streamcluster bzip hmmer Mesh Flattened-Butterfly Firefly Corona MPNOC R-3PO-L1 R-3PO-LA R-3PO shows an increase in performance of about 2.5x 28

29 Speed-Up Synthetic Traffic (256 Cores) Uniform Bit-reversal Butterfly Compliment Matrix-Transpose Perfect Shuffle Neighbor Mesh FB FireFly Corona MPNOC R-3PO-L1 R-3PO-LA R-3PO shows an increase in performance of about 4x 29

30 Performance Degradation 1.2 Fault Tolerance blackscholes facesim fluidanimate freqmin streamcluster bzip hmmer R-3PO-L1 R-3PO-L1(10%) R-3PO-L1(25%) R-3PO-L1(50%) Degrades performance when compared to R-3PO as follows: With 10% faults, performance loss is 3% With 25% faults, performance loss is 13% With 50% faults, performance loss is 35% 30

31 Talk Outline Motivation & Background R-3PO: Architecture & Reconfiguration Performance Analysis Conclusions 31

32 Conclusions R-3PO combines the benefits of nanophotonic and 3D stacking to reduce energy consumption while eliminating waveguide crossing We evaluate power-performance trade-off by analyzing the design space of implementing reconfiguration across multiple layers We apply our reconfiguration algorithm to bypass faulty channels by sharing bandwidth Our results indicate that energy/bit can be decreased by 23-36% for various real applications while improving application speedup by 2-4X 32

33 Thank You Questions?

34 Speed-Up Application Traffic (64 Cores/16λ) blackscholes facesim fluidanimate freqmin streamcluster bzip hmmer Mesh Flattened-Butterfly Firefly Corona MPNOC R-3PO-L1 R-3PO-LA R-3PO shows an increase in performance of about 2.5x 34

35 Power Analysis Device Loss(dB) Device Loss(dB) Coupler (L c ) 1 Filter drop (L f ) 1 Non-Linearity (L n ) 1 Bending (L B ) 1 Photo-detector (L p ) 1 Waveguide Crossing (L wc ) 0.05 Modulator Insertion (L i ) 1 Receiver (L RS ) Sensitivity -26 dbm (R-3PO) Waveguide (per cm) (L W ) 1.3 Splitter (L s ) 3 Laser Efficiently 30% C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popović, H. Li, H. Smith, J. Hoyt, F. Kärtner, R. Ram, V. Stojanović, and K. Asanović. "Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics."16th Symposium on High-Performance Interconnects (HOTI-16), Aug

36 Laser Power (Watts) Laser Power (Watts) Variation in Laser Power Laser Power (Watts) X: 64 Y: -26 Z: 6.1 Laser Power (Watts) Receiver -25 Receiver Sensitivity (dbm) (a) Wavelengths Ring Ring Filter Loss (db) (b) Waveguide Loss (db) Waveguide Loss (db)

37 Reconfiguration Combinations R-3PO-L1 Layer 0 Layer 1 Layer 2 Layer 3 R-3PO-LA Layer 0 Layer 1 Layer 2 Layer 3 Layer 0 G0 <->G0 G1 <-> G2 G3 <-> G3 Layer 0 G0 <->G0 G1 <-> G2 G3 <-> G3 Layer 1 G0 <->G2 G1 <-> G3 Layer 1 G0 <->G2 G1 <-> G3 Layer 2 G1 <->G1 G0 <-> G3 G2 <-> G2 Layer 2 G1 <->G1 G0 <-> G3 G2 <-> G2 Layer 3 R-3PO-L2 G0 <->G1 G2 <-> G3 Layer 0 Layer 1 Layer 2 Layer 3 Layer 3 R-3PO-L3 G0 <->G1 G2 <-> G3 Layer 0 Layer 1 Layer 2 Layer 3 Layer 0 G0 <->G0 G1 <-> G2 G3 <-> G3 Layer 0 G0 <->G0 G1 <-> G2 G3 <-> G3 Layer 1 G0 <->G2 G1 <-> G3 Layer 1 G0 <->G2 G1 <-> G3 Layer 2 G1 <->G1 G0 <-> G3 G2 <-> G2 Layer 2 G1 <->G1 G0 <-> G3 G2 <-> G2 Layer 3 G0 <->G1 G2 <-> G3 Layer 3 G0 <->G1 G2 <-> G3 37