VLSI, MCM, and WSI: A Design Comparison

Transcription

1 VLSI, MCM, and WSI: A Design Comparison EARL E. SWARTZLANDER, JR. University of Texas at Austin Three IC technologies result in different outcomes performance and cost in two case studies. The author compares their designs in terms of silicon area, substrate size, and power consumption. DESPITE THE HIGH PERFORMANCE of today s systems, many applications demand still greater computing power and speed. Such relentless demands may be largely due to the apparent ease with which systems designers have achieved current performance levels. After all, vendors roll out new systems on what seems to be a regular basis. Each new system is more powerful than the last, and frequently the rollouts are scant months apart. Appearances aside, however, it takes time-consuming design iterations, followed by performance/cost evaluation, before a system design is implemented. Key factors in any design effort are performance and cost measurements. Performance measures include MIPS (million instructions per second) and Mflops (million floating-point operations per second). Yet another performance measurement is the time required to execute either synthetic or real benchmark programs. But performance measurements must always be balanced against cost, and system design objectives often impose a requirement to limit cost. Although cost can be measured in many ways, three key measurements are the amount of silicon needed to produce a working chip size of the substrate power consumption In this article, I compare the three costs for three leading chip technologies: VLSI (very large-scale integration), MCM (multichip module), and WSI (wafer-scale integration). See the Definitions, box, for more information. For discussion purposes I based my comparison on published data for two application case studies: a stand-alone computer and a DSP. I don t examine packaging costs because these vary considerably from one application to another; furthermore, packaging is not a direct result of the chip technology selection. Computer case study Computer fabrication is a good way to illustrate the cost estimation process. The computer in my design comparison is the Hitachi SH7600, 1 which is a -bit RISC processor that performs 16 MIPS (at a clock rate of 20 MHz). It has 1 million, -bit words of D, and an interface unit interconnected as shown in Figure 1. Although these parameters are somewhat dated, they allowed use of published chip information, which was an important consideration. The design is similar to an ultra large scale integrated system consisting of 44 Mbytes of D, 384 Kbytes of S, and an 18,000 gate array. 2 The chip size is , which includes on each edge for pads (the core area is ). The memory consists of eight 1M-word 4-bit dynamic chips. 3 Each of the chips is , which includes on each edge for pads. The interface is based on a preliminary design of an interface control unit for heterogeneous networks that measures This includes on each edge for pads. Silicon area. In determining the silicon area required by the different technologies, I used theoretical models. VLSI. The VLSI implementation of the computer uses 10 cells (one central processing /98/$ IEEE IEEE DESIGN & TEST OF COMPUTERS

2 Input Output Interface control unit Central processing unit Addresses 20 Data Memory (1M ) Figure 1. Block diagram of the computer selected for design comparison of three IC technologies Figure 2. VLSI floorplan of the computer Figure 3. MCM floorplan of the computer unit, eight s, and one interface control unit) as the floorplan in Figure 2 shows. The layout is an incomplete 6 2 array of cells with the and cells in the four spaces where cells are omitted. The array is The chip pad area increases the final size to I assumed the defect density to be 0.1 defect per cm 2, which gives an expected yield of 60% for this circuit. With these values, the silicon area, or SA v, is 8.4 cm 2. Figure 4. WSI floorplan of the computer. MCM. An MCM realization of this computer uses 10 dies, placed as shown in Figure 3. The floorplan differs somewhat from the VLSI s floorplan due to the - border around each die for bonding pads and the 1.5- space between adjacent dies. Table 1 lists the silicon area for each of the dies in the MCM. This calculation assumes that the bonding yield, Y b, is 95%. The total silicon area, SA m, is 6.3 cm 2. Table 1. MCM silicon area of the computer. WSI. Figure 4 shows the WSI floorplan. It uses pairs of cells for the and the. This is one-from-two pooled sparing, which simply means for example that there are two s Size Area Die Bonded Silicon Die Quantity ( ) (cm 2 ) yield (%) yield (%) area (cm 2 ) JULY SEPTEMBER

3 Silicon area cost model A chip s manufacturing cost is proportional to the silicon area; therefore, our first cost measure is the silicon area that must be fabricated to produce a functional chip. With a VLSI approach, the silicon area, SA v, is the chip area divided by the yield. The chip area is the sum of the core area of the chip, A c, and the pad area, A p. The yield is Y v. A simple model 1 for the chip yield as a function of the process defect density, D 0, and the chip area, A c + A p, is D ( Y A c + A p ) 0 v = exp Other models are possible, 1 but the negative exponential is a reasonable first approximation. The effect of the chip layout and floorplan on the yield is ignored in this first-order analysis, although they have been shown to be important for some cases. 2 With an MCM approach, the silicon area, SA m, is the sum of the silicon areas of the constituent dies. The silicon area of the dies is the die area with required pad area, divided by the bonded die yield. The bonded die yield is the product of the die yield and the bonding yield (the latter is assumed to be approximately the same for each chip). With a WSI approach, the silicon area, SA w, is the chip area divided by the wafer yield. Here the chip area is the sum of the wafer pad area and the area of the wafer (the sum of the core areas). Each core area is increased by a redundancy factor. Model comparison shows that relative to the VLSI implementation, the MCM approach incurs an itive area penalty for the pads required by each die, while the WSI implementation incurs a multiplicative redundancy factor penalty. References 1. I. Koren and C.H. Stapper, Yield Models for Defect-Tolerant VLSI Circuits: A Review, Proc. Int l Workshop on Defect and Fault Tolerance in VLSI Systems, Plenum Press, New York, 1988, pp Z. Koren and I. Koren, Does the Floorplan of a Chip Affect Its Yield? Proc. IEEE Int l Workshop on Defect and Fault Tolerance in VLSI Systems, IEEE Press, Piscataway, N.J., 1993, pp on the chip and that one of the two must be operational. Pooled sparing builds in redundancy. A WSI implementation calls for nine cells, of which at least eight must be good (that is, eight-from-nine pooled sparing). I arrived at the average redundancy factor by calculating the ratio of area of the WSI realization without the chip pad area to the (nonredundant) VLSI realization without the chip pad area. The factor is 1.3 in this case. The redundancy factor is 2 for the and, but only 1.1 for the. For more information about redundancy, see the box, Silicon area cost model. With a defect density of 0.1 defect per cm 2, the yield of a single cell (A v = 0.65 cm 2 ) is 93.6%. The probability that at least one of the two cells in the pool is good is 99.6%. The pool s yield is the product of the probability that at least one cell is good times the interconnection and selection logic yield. (I assumed that to be 99% due to its small size and simplicity). This gives a 98.6% yield for the pool. For the, I computed the yield of the two-cell pool by calculating the probability that at least one of the two cells is good (99.8%). I multiplied that by the yield of the interconnection and selection logic (99%), thereby arriving at a 98.8% yield for the pool. For the, I computed the yield of the nine-cell pool by calculating the probability that at least eight of the cells are good (95.7%). I multiplied that by the yield of the interconnection and selection logic. (I assumed that to be 95% due to the greater size and complexity than for the and pools). This gave a 90.9% yield for the pool. Dividing the wafer size (6.7 cm 2 ) by the expected wafer yield (the product of the,, and pool yields, or 88.6%), I determined the SA w to be 7.5 cm 2. Substrate size. I determined the size of the VLSI, MCM, and WSI implementations of the example computer by inspecting the floorplans in Figures 2, 3, and 4. The VLSI substrate is for an area of 5.1 cm 2. The MCM substrate is for an area of 8.9 cm 2. The WSI substrate is for an area of 6.7 cm 2. For details, see the box, Substrate size cost model. Power consumption. Power consumption is a particularly relevant cost measure in this era of portable and battery-operated systems. It is, however, difficult to estimate because of many contributing variables. For static CMOS technology, the buffer power consumption is proportional to the product of the load capacitance times the frequency. For MCM implementations, the inter-die driver power consumption is the primary penalty relative to VLSI. With WSI, the inputs to the redundant circuits would normally be disabled so that they consume only generally negligible quiescent power. 30 IEEE DESIGN & TEST OF COMPUTERS

4 Definitions VLSI A very large scale integrated circuit is a single IC without redundancy. MCM A multichip module is an assemblage of multiple dies onto a ceramic or silicon substrate. WSI A wafer-scale integrated circuit that includes redundancy to allow correct operation even if the chip contains faults as manufactured. From these definitions, then, we can see that VLSI requires the fabrication of large fault-free chips; MCM provides many small dies that are assembled to create the MCM; and WSI uses redundancy to provide chips that produce correct results even though they may contain some faults. There is some overlap in these definitions: Current large D chips include extra rows and columns for fault circumvention. These are best viewed as VLSI, however, because only a small amount of circuitry is redundant. Substrate size cost model A second way to measure cost is the size of the packaged part. The size or weight of an implementation is proportional to the substrate size. Approximately the same number of package pins is required for implementation, whether for VLSI, MCM, or WSI. The VLSI implementation size is the sum of the chip pad area and the sum of the cell areas. The MCM implementation size is the sum of the module pad area, the die areas (which include the pad areas), and the spacing between dies. Designers use the spacing between dies to route signals, clocks, and power. I assume here that the inter-die spacing is three times the pads width. Similarly, the WSI implementation size is equal to that of the VLSI design multiplied by the redundancy factor. To compare the power consumption, I ignored the internal consumption of the,, and cells. I could ignore it because the power consumed by chip output buffers, not the internal consumption, is the primary difference between the various approaches. I assumed that the output buffer consumption is proportional to the product of the load capacitance times the frequency. Table 2 lists the loadings and frequencies. The power depends on the actual loading, not the maximum load that the buffer is designed to drive. On the VLSI and WSI chips, I assumed point-to-point connections to present a - pf load. As the ress bus lines have 8 destinations, I assumed them to present a 4-pf load. For the MCM implementation, I assumed the point-to-point connections and the ress bus lines to present 5-pf and 40-pf loads. In all three cases, the outputs (with 50-pf loading) dominate. For VLSI power, P W = 0.47 W; for MCM, P W = 1.1 W; and for WSI, P W = 0.47W. Table 2. Signal loading of the computer. Number Frequency VLSI load MCM load WSI load Connection of lines (MHz) (picofarads) (picofarads) (picofarads) (resses) (data) Output Table 3. Comparison of three technologies for implementation of a stand-alone computer. Parameter VLSI MCM WSI Silicon area 8.4 cm cm cm 2 Substrate size Substrate area 5.1 cm cm cm 2 Driver power 0.47 watts 1.1 watts 0.47 watts Comparison results. Table 3 suarizes my findings for the three approaches to the design of a stand-alone computer. The MCM implementation has the smallest silicon area, and as a result, it should cost less in mass production to produce the required silicon chips than either of the other approaches. The VLSI chip is the smallest, so it should cost less to package and will weigh less than the other two approaches. The VLSI and WSI implementations use about half the power of the MCM. JULY SEPTEMBER

5 Data input Stage 1 multiply multiply multiply Stage 2 Stage 3 Transform output is a building block for a highperformance pipeline FFT processor. 4 It consists of three complex multipliers and eight complex ers, interconnected as Figure 5 shows. A complex multiplier implementation requires four real multipliers and two real ers; a complex er s implementation requires two real ers. As a result, the radix-4 element requires a total of 12 real multipliers and 22 real ers. Sine/ cosine ROM Figure 5. Radix-4 FFT butterfly processing element for the DSP in the second case study comparison of IC technologies. Silicon area. I compared VLSI, MCM, and WSI approaches to the DSP in a manner similar to what I did for the stand-alone computer Figure 6. VLSI floorplan of the radix-4 butterfly processing DSP case study To compare VLSI, MCM, and WSI technologies in the context of a high-speed DSP, I selected the design of a radix-4 fast Fourier transform butterfly processing This element VLSI. As described, the VLSI implementation of the radix-4 FFT butterfly processing element uses 12 multipliers and 22 ers. My comparison assumed an aggressive 0.6-micron fabrication process with three metal layers. Consequently, the core area of either a - bit floating-point er or a -bit floating-point multiplier is approximately As Figure 6 shows, the required 34 cells in a 6 6 array have two unoccupied positions (these could be sine/cosine ROMs and clock drivers). The 6 6 array is The chip pad area increases the final size to With a defect density of 0.1 defect per cm 2, the expected yield for a circuit of this size is 60% and the silicon area, SA v, is 8.5 cm 2. MCM. The MCM realization uses 34 arithmetic chips, which can be mounted in a 6 6 array, as Figure 7 shows. The multiplier and er chips are comparably sized. Adding the pad area, which an MCM implementation requires, increases the die size to for which the yield is 97.7%. With a bonding yield of 95%, the bonded yield is 92.8%. Since the die area is 0.23 cm 2, the silicon area of one die is 0.25 cm 2, and the SA m is 8.44 cm 2. WSI. The WSI realization uses six pools of cells floatingpoint ers or multipliers for the 34 needed arithmetic elements, as Figure 8 shows. Pools 1, 2, and 3 are four-fromfive pools of multipliers that provide the real multipliers needed to implement the three complex multipliers. Pool 4 is a six-from-seven pool of ers that provides the six ers needed for the three complex multipliers. IEEE DESIGN & TEST OF COMPUTERS

6 Figure 7. MCM floorplan of the radix-4 butterfly processing Finally, pools 5 and 6 are eight-from-nine pools of ers. These provide the eight ers needed for the four complex ers in the last two stages of the radix-4 butterfly processing The 40 cells are laid out in a 6 7 array with two positions unoccupied, as shown in Figure 8. Table 4 shows the yield of the six pools. In each case the yield of the sparing and interconnection logic (assumed to be 95%) chiefly determines the total pool yield. I divided the wafer area (5.9 cm 2 ) by the wafer yield (the product of the yields of the six pools (69.3%) and determined the silicon area, SA w, to be 8.5 cm 2. Substrate size. I determined the size of the VLSI, MCM, and WSI implementations of the butterfly processing element by inspecting the floorplans in Figures 6, 7, and 8. The VLSI substrate is for an area of 5.1 cm 2. The MCM substrate is for an area of 13.0 cm 2. The WSI substrate is for an area of 5.9 cm 2. Power consumption. Each of the 34 arithmetic elements produces a -bit result. Eight of these -bit results are butterfly outputs that exit the module, and I assumed these to drive a 50-pf load. I assumed the 26 elements that drive other cells for either the VLSI or the WSI implementation to drive a -pf load. The total power required for the buffers is 8.3 W. The 26 elements that drive other chips within an MCM Figure 8. WSI floorplan of the radix-4 butterfly processing The er and multiplier pools have been shaded to distinguish one from the other. Table 4. Pool yield for the WSI radix-4 butterfly processing Pool Pool Interconnect Total Pool size yield (%) yield (%) yield (%) 1 4 from from from from from from module I assumed to drive a 5-pf load. The total power required for the MCM buffers is 10.6 W. Comparison. Table 5 on the next page suarizes my findings for the three approaches to the design of a butterfly processing element in the DSP case study. The MCM implementation uses less silicon, and as a result, its chips should cost less in mass production than either of the other JULY SEPTEMBER

7 Table 5. Comparison of radix-4 butterfly processing element implementations for a DSP. Parameter VLSI MCM WSI Silicon area 8.5 cm 2 8.4cm cm 2 Substrate size Substrate area 5.1 cm cm cm 2 Driver power 8.3 watts 10.6 watts 8.3 watts approaches. The VLSI chip is the smallest, so it should cost less to package and will weigh less than the other two approaches. The VLSI and WSI implementations use about 20% less power than the MCM. I DEALT WITH A COMPARISON of VLSI, MCM, and WSI technologies on the basis of silicon area, substrate size, and power consumption for two example applications: a general-purpose computer and a specialized DSP. An important extension to this work concerns packaging. Packaging affects both performance and cost. Performance effects result from the length and the parasitics of lines from the chips to the board. Cost effects depend on the size and type of the substrate. Packaging is likely to have the greatest negative impact on the MCM (since it must include a multilayer substrate) and least impact on the VLSI approach. Another important issue for MCM is the availability of known-good dies. To the extent that good dies are available, testing and rework costs decrease markedly. Earl E. Swartzlander, Jr. is a professor of electrical and computer engineering at the University of Texas at Austin where he holds the Schlumberger Centennial Chair in Engineering. His research interests are in application-specific processing and the interaction between computer architecture, computer arithmetic, and VLSI technology. Swartzlander received a BS from Purdue University, an MS from the University of Colorado, and a PhD from the University of Southern California. He is an IEEE fellow and an Outstanding Electrical Engineer and a Distinguished Engineering Alumnus of Purdue University. He has also received the Distinguished Engineering Alumnus Award from the University of Colorado. Contact the author at Dept. of Electrical and Computer Engineering, Univ. of Texas, Austin, TX 78712; e.swartzlander@compmail.com. References 1. K. Noguchi, S. Kawasaki, and Y. Akao, New Generation RISC Microcomputer for Personal Information and Counication Equipment, Hitachi Review, Vol. 43, 1994, pp K. Sato et al., A System-Integrated ULSI Chip Containing Eleven 4MB s, Six 64KB Ss and an 18K Gate Array, IEEE Int l Solid-State Circuits Conf. Digest of Tech. Papers, IEEE Press, Piscataway, N.J., 1992, pp. 52, 53, and T. Nagai et al., A 17ns 4Mb CMOS D Using Direct Bit-Line Sensing Technique, IEEE Int l Solid-State Circuits Conf. Digest of Tech. Papers, IEEE Press, Piscataway, N.J., 1991, pp E.E. Swartzlander, Jr., VLSI Signal Processing Systems, Kluwer Academic, Boston, 1986, pp World Wide Web CS Members: You have electronic access to Abstracts and Articles weeks before publication The IEEE Computer Society Online via World Wide Web Abstracts and tables of contents of IEEE Design & Test and other Computer Society publications Conference calendar Career opportunities General membership and subscription information Calls for papers IEEE Computer Society Press Catalog Volunteer and staff directory 34 IEEE DESIGN & TEST OF COMPUTERS