Benjamin G. Lee, Member, IEEE, Aleksandr Biberman, Student Member, IEEE, Johnnie Chan, Student Member, IEEE, and Keren Bergman, Fellow, IEEE

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1 6 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 16, NO. 1, JANUARY/FEBRUARY 2010 High-Performance Modulators and Switches for Silicon Photonic Networks-on-Chip Benjamin G. Lee, Member, IEEE, Aleksandr Biberman, Student Member, IEEE, Johnnie Chan, Student Member, IEEE, and Keren Bergman, Fellow, IEEE (Invited Paper) Abstract The stringent on- and off-chip communications demands of future-generation chip multiprocessors require innovative and potentially disruptive technology solutions, such as chip-scale photonic transmission systems. A space-switched, wavelength-parallel photonic network-on-chip has been shown to equip users with high-bandwidth, low-latency links in an energyefficient manner. Here, experimental measurements on fabricated silicon photonic devices verify a large set of the components needed to construct these networks. The proposed system architecture is reviewed to motivate the demanding performance requirements of the components. Then, systems-level investigations are delineated for multiwavelength electrooptic modulators and photonic switching elements arranged in 1 2, 2 2, and 4 4formations. Compact ( 10 µm), high-speed (4 Gb/s) modulators, having a large degree of channel scalability (four channels demonstrated), are demonstrated with excellent data integrity (bit error rates (BERs) <10 12 ). Meanwhile, switches are shown to transfer extensive throughput bandwidths (250 Gb/s) with fast switching speeds (<1 ns) and sufficient extinction ratios (>10 db). Data integrity is also verified for the switches (BERs < ) with power penalty measurements amid dynamic operation. These network component demonstrations verify the feasibility of the proposed system architecture, while previous works have verified its efficacy. Index Terms Charge injection devices, circuit switching, computer networks, multiprocessor interconnection, optical resonators, photonic switching systems, supercomputers. I. INTRODUCTION MICROPROCESSORS have enjoyed many decades of steady performance gains and speed increases due in large part to progress in CMOS device integration and increased instruction-level parallelism. Nevertheless, as a result of diminishing returns in traditional performance-scaling techniques and practical power limitations, modern chip design is shifting focus away from continued advancements in uniprocessor perfor- Manuscript received May 4, 2009; revised June 29, First published October 6, 2009; current version published February 5, This work was supported by the National Science Foundation under Contract ECS and Contract CCF , by the Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office under Contract ARL W911NF , and by the Interconnect Focus Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation and DARPA program. B. G. Lee was with the Department of Electrical Engineering, Columbia University, New York, NY USA. He is now with IBM T. J. Watson Research Center, Yorktown Heights, NY USA ( bglee@us.ibm.com). A. Biberman, J. Chan, and K. Bergman are with the Department of Electrical Engineering, Columbia University, New York, NY USA ( biberman@ee.columbia.edu; johnnie@ee.columbia.edu; bergman@ ee.columbia.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /JSTQE X/$ IEEE mance toward processor-level parallelism. Chip multiprocessors (CMPs), which leverage parallelism to perform the program execution by integrating two or more processor cores onto the same chip, have emerged as the new paradigm [1] [4]. Consequently, new fields of research are emerging to address the many challenges in implementation and scaling brought about by the growing number of cores in the processor challenges that can be fundamentally different from those faced during the uniprocessor era. One of the largest changes in focus is the new emphasis on intrachip communications. As the number of on-chip communicators grows, and as programmers learn to more efficiently utilize the chip s parallel resources, the communication throughput must rapidly scale to maintain global performance. Therefore, networks-on-chip (NoCs) have become a vital focus of emerging research [5], and significant attention has been given to implementing mesh and torus network topologies (e.g., [6]), due to their ease in directly mapping to a 2-D processor plane. Additionally, electronic signaling methods have been the status quo for on-chip communication, but these solutions require significant amounts of power to interconnect even just several cores together. As a result, creative new topologies leverage large-radix switches to reduce hop counts of electronic message transfers, thereby alleviating, to some extent, the overconsumption of power and latency caused by these sizable NoCs [7]. Electrical links induce growing signal losses and distortions as the data rate is increased. Although complex equalization techniques can compensate over relatively short distances, ultimately repeaters are required at regular intervals along an electronic link, dissipating more power as the link grows in distance, and as the signals increase in data rate. The problem is exacerbated in the longer links required for off-chip communication. For this reason, NoC solutions that rely on electronic signaling alone may not be able to provide adequate on- and off-chip bandwidths for future CMP generations while remaining within allotted power budgets. It is envisioned that photonics may provide a solution to the daunting problems facing future CMP scaling [8] [16]. Optical communications have been exploited for decades in long-haul systems due in part to the inherently low loss and low signal distortion arising from data rate transparency and minimal dispersion and nonlinearity. These properties lead to superior performance in signal integrity. Optical media are capable of transporting tremendous bandwidths (tens of terahertz for both optical fibers and silicon waveguides); these bandwidths can be realized through wavelength-division multiplexing (WDM).

2 LEE et al.: HIGH-PERFORMANCE MODULATORS AND SWITCHES FOR SILICON PHOTONIC NETWORKS-ON-CHIP 7 Furthermore, optical transport latencies are limited only by the optical time-of-flight. Optical technologies are continually being leveraged in systems with shorter characteristic distances, such as local- and metro-area networks, as well as high-performance computing (HPC) environments. Commercial HPC systems commonly employ optical fiber in rack-to-rack links [17], and significant research into shorter distance optical technologies is occurring as well, including card-to-card backplane interconnects using optical printed circuit boards [18] [20]. Advancements in CMOS-compatible silicon photonics, including the development of compact, energy-efficient, and high-bandwidth modulators and switches, have now provided the path toward chip-scale optical transmission. The goal of this paper is to motivate and showcase the use of silicon photonic devices for modulating and switching within photonic NoCs. Initially, a few of the many investigations by other research groups into chip-scale photonic interconnection networks are briefly reviewed in Section II. Then, in Section III, our proposed photonic NoC architecture is explained in order to provide context to the device-related measurements. Experimental investigations of devices that make up many of the photonic components required to construct such systems are described in Section IV. In this section, works on passive devices and detectors are reviewed, but special attention is given to modulators and switches. Subsequently, concluding remarks are disclosed in Section V. II. OTHER PROPOSED PHOTONIC NOC ARCHITECTURES Photonic NoCs are gaining significant attention as a plausible means of alleviating on- and off-chip bandwidth bottlenecks and power limitations in scaled CMP systems. Architectures for both on- and off-chip photonic infrastructures and access points, along with specific network topologies, are being developed by many different research groups, which are leveraging silicon photonic device advancements to envision novel systems that can meet critical performance requirements in future CMPs. Kirman et al. explore hierarchical optoelectronic bus architectures with a moderate number (4 12) of wavelength channels per waveguide [8]. Although the photonic bus design is a fairly straightforward extrapolation of modern homogeneous electronic interconnects, the investigation elucidates that the performance improvements gained by using optics on-chip are related to the depth at which the photonic components penetrate into the bus and the amount of electronics that can be avoided within the communications pathway. These pioneering results show the potential performance benefits that are available when optical communications are brought into the chip s infrastructure. Another group proposes Corona, a system architecture that uses on-chip photonic components to address both intercore and off-stack memory communications [9], [10]. Corona contains several optically enabled topologies, one of which is a wavelength-routed crossbar arranged in a serpentine fashion that interconnects up to 256 cores. Other independent topologies implement broadcast mechanisms for cache coherency and optically activated arbitration schemes. Several other groups have proposed network designs aimed exclusively at addressing challenges in off-chip memory access using silicon photonics. Optically connected dual inline memory module (OCDIMM), an architecture proposed by Hadke et al. for optically connected memory, uses a single loop employing wavelength-selective routing to transmit to the intended receiver [11]. Batten et al. focus their attention on how on-chip optics can ameliorate the off-chip communication problem, with the design of a wavelength-routed optoelectronic crossbar switch that interconnects up to 256 processing cores with up to 16 dynamic RAM modules using monolithically integrated silicon photonics [12]. III. OUR PROPOSED PHOTONIC NOCARCHITECTURE One commonality between all the proposed network architectures in Section II is the use of wavelength-selective routing to direct messages from source to destination. The advantage of such a scheme is that routing can be accomplished through deterministically selected transmission wavelengths using passive wavelength-selective optics that are tuned to the specific wavelengths required. While this provides low latency, messages are restricted to a single wavelength channel per waveguide. The architecture studied here, which we have previously proposed and investigated [13] [16], takes an alternative approach aggregating multiple wavelength channels into a single extremely high bandwidth optical message that is routed using active switches. The space-switched system leverages the optical domain to: 1) reduce power consumption through transparent optical routing and 2) increase message bandwidth through wavelength parallelism (rather than wavelength-routed systems in which wavelength parallelism is leveraged to provide increased granularity). Meanwhile, the electronic domain remains a vital part of the system, providing decentralized routing control for the photonic network. In this section, we will describe how the hybrid (i.e., photonic and electronic) architecture is envisioned and designed. A. Physical Implementation The proposed hybrid interconnection network is envisioned to overlay the CMPs in a three-dimensionally stacked monolithically integrated structure, providing low-latency and lowpower access into the network for the on-chip cores. Much progress has been achieved in 3-D integration (3DI) of CMOS systems [21], [22]. This important research area attempts to extend the scaling of Moore s law into the third dimension by physically stacking traditionally planar chip layers, maximizing the area allotted to CMOS devices over the limited chip footprint, as well as decreasing the critical wiring distance between communicators. In a purely traditional CMOS environment, 3DI has practical advantages such as reductions in required link dimensions, which ultimately reduce power dissipation, noise, and latency in conventional electrical wiring. Moreover, the different planes in a stack can take on more specialized roles, allowing, for example, the integration of dedicated memory planes that overlay the processors for high-capacity local cache. In addition, 3DI makes practical the inclusion of revolutionary

3 8 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 16, NO. 1, JANUARY/FEBRUARY 2010 Fig. 1. Illustration of a 3DI stack with dedicated computation, storage, and communication planes (not to scale). technologies within the CMOS stack. CMOS-compatible photonics are uniquely poised to take advantage of this opportunity due to demonstrated physical performance and their potential to greatly impact system performance. In this scenario, one or more planes of the 3DI stack would be entirely dedicated to the communication links and enabling photonic and electronic devices. The critical enabling technologies for 3DI are the advancements in high density through silicon vias (TSV), which electrically connect the layers within a stack. 3DI utilizing TSVs showcases inherently short interconnect paths with reduced resistance and capacitance, as well as lower power consumption. According to the International Technology Roadmap for Semiconductors, TSVs for the 32 nm technology node are expected to scale to 1.4 µm contact pitches, 0.7 µm diameters, almost cm 2 maximum densities, and 15 µm maximum layer thicknesses [23]. Of course, there are yet many challenges for 3DI, including power dissipation and heat flow solutions as well as process manufacturability, but the potential advantages of success for such a system merit continued analysis. The vision for our system, proposed for the 32 nm CMOS technology node, is depicted in Fig. 1. The bottom plane in the figure illustrates the CMOS layer, containing all the traditional processing elements. As Moore s law continues to scale the size of the transistor to this technology node, this layer is envisioned to comprise an array of the ever-smaller CMPs. Subsequent planes directly above the CMOS plane (shown in the center of the stack in the figure) are dedicated on-chip memory planes, enabling shorter memory access latencies and reducing the off-chip bandwidth requirement. The final plane (shown on top of the stack in the figure) is the dedicated global communications plane, housing the photonic and electronic networks interconnecting all the users in the CMOS plane. The communication plane provides both intra- and interplane connectivity, while also interfacing the three-dimensionally stacked chip with external resources such as main memory. B. Routing Algorithm Within the communication plane, responsibilities are delegated to electronic and photonic technologies by weighing the relative costs and benefits of each for a given task. While elec- Fig. 2. Schematic of a 4 4 torus topology. The gateway switches (G), injection switches (I), routing switches (X), and ejection switches (E) are correspondingly labeled in the diagram. Thick lines represent the transmission network, while thin lines represent the access network. tronic solutions provide extensive buffering and processing, they are limited in transmission bandwidth and efficiency. On the other hand, photonics can transmit high-quality high-speed signals, virtually irrespective of distance at the chip scale. Nevertheless, buffering and processing, especially on chip, is not currently feasible. Consequently, we advocate executing message transmissions in the photonic domain and control and processing in the electronic domain. The outcome is a circuit-switched hybrid NoC, where photonic pathways are reserved before transmission begins. This is accomplished via electronic control packets, which set the proper states of the photonic switching elements making up the photonic NoC as they route themselves through the network. As a result, a very low bandwidth (and thus, low power) electronic network overlays the high-bandwidth photonic NoC. Since the electronic control packets are self-routing, no central arbiter is required to map transmission requests into service grants over a specific traffic pattern. C. Network Topologies Previous works have shown performance and power benefits of these hybrid NoCs over equivalent purely electronic solutions [13], [14]. The photonic and electronic layers of the hybrid NoC are logically arranged as 2-D folded-torus topologies. By combining waveguides and switching elements together, a complete transmission network (arranged in a torus topology) and access network (for enabling messages to enter and exit the torus) are formed (Fig. 2). Note that the rows and columns forming the grid of the 2-D torus each form a ring, rather than alinesegmentasina2-dmesh. The correct propagation of an optical message between the access points, or gateways, of its source and destination is

4 LEE et al.: HIGH-PERFORMANCE MODULATORS AND SWITCHES FOR SILICON PHOTONIC NETWORKS-ON-CHIP 9 accomplished through the use of four distinct photonic switching elements. Transmitted messages originate from a gateway (not shown in Fig. 2) that contains an arrangement of modulators and receivers that are electrically connected to an underlying processing core through the 3DI structure. The set of modulators transmit data concurrently on different wavelengths, enabling high-bandwidth WDM transmission. The resulting message is first routed from the gateway at a gateway switch (G), which handles inbound and outbound photonic traffic to and from the access point. Messages are routed toward a nearby injection switch (I), which places the messages onto the rows of the torus. The torus implements dimension-ordered routing, which sends a message fully along one dimension of the grid before sending it along the other. A message traverses the network along the row on which it was injected until it reaches a 4 4 routing switch (X) located in the same column as the destination. The message then propagates in the column to the appropriate ejection switch (E), where it exits the torus and enters the destination s gateway switch. The message is then detected within the gateway. In this example, there is a one-to-one mapping of gateways to routing switches, such that exactly one routing switch and one gateway are located over each of the tiles, which represent network users (e.g., processing cores). However, overprovisioning may be useful in certain cases to increase path diversity. Careful attention has been placed on the design of the 4 4 routing switch, which is a critical component to the performance of the network [15]. Former iterations of the switch exhibited blocking behavior. This occurs when a message is not allocated a path through the switch due to the existence of a second message, which requests a separate input and output port, but occupies desired resources within the switch (e.g., a waveguide). The use of nonblocking switches simplifies routing and allows improved system performance in terms of throughput and latency [15]. In addition, they enable the design of strictly nonblocking networks via overprovisioning, providing a source with a path to any idle destination, regardless of the current network traffic load. Various arrangements of the 4 4 nonblocking switch have been proposed. Each has unique optical properties, affecting metrics such as the network s aggregate optical insertion loss in different ways for a given traffic pattern. These variations, in turn, affect the topology scalability for a specific application or routing algorithm [16]. Here, we focus on one arrangement only, but future topology implementations will require similar design decisions to optimize performance. IV. SILICON PHOTONIC NOC ENABLING COMPONENTS Advances in nanoscale fabrication and dense integration of silicon devices has led to the development of many viable photonic integrated circuit (PIC) solutions for short-reach applications currently dominated by electronics. The silicon-oninsulator (SOI) material system is attractive for realizing PICbased interconnection networks due to its high index contrast and compatibility with the well-developed CMOS fabrication process. Furthermore, microring resonators enable the assembly of many valuable building blocks, including passive filters [25], [26], [34], [66], [69] [71], [73], electrooptic modulators [73], [52] [58], and multifarious broadband switches and routers [61], [63] [65], [67], [68], [72], [74]. In order to achieve a full link between communicating access points, many passive and active components are necessary. Spatially parallel electrical signals from the source are first translated into the wavelength-parallel optical domain using electrooptic modulators. Once the data are in the optical domain, the cohesive WDM signal is spatially routed using broadband electrooptic switches, which consist of the aforementioned gateway, injection, routing, and ejection switches. Along with the required passive components (e.g., waveguides, waveguide crossings, and waveguide-to-fiber couplers for offchip destinations), the switches direct the signal eventually to the destination s photodetectors, which subsequently translate the wavelength-parallel optical signal back into the spatially parallel electrical domain for processing. In this section, the experimental progress of the passive components (Section IV-A) and photodetectors (Section IV-B) is outlined. Then, recent demonstrations of fabricated modulators (Section IV-C) and switches (Section IV-D) based on silicon ring resonator technology are described. A. Passive Components Low-loss (<2 db/cm) rectangular single-mode waveguides have been shown to operate over large spectral bandwidths in the 1.5 µm wavelength region [24] [26]. These waveguides are well suited for intrachip photonic communication, and are a necessary part of more complex passive and active NoC components. Recently, an etch-less approach to fabrication has brought about slightly less confined waveguides that have demonstrated propagation loss as low as 0.3 db/cm [27]. In addition to waveguides, photonic NoCs will require numerous waveguide crossings and I/O couplers for interfacing to off-chip resources. Compact, lowloss, and low-crosstalk waveguide crossings have been demonstrated [28] [30]. Using a double-etched structure, the insertion loss has been reduced to 0.16 db with a crosstalk of 40 db and a footprint of 6 6 µm 2 [30]. Two approaches to I/O coupling horizontal [31] [33] and vertical [34], [35] have achieved fruitful results. The horizontal couplers have demonstrated efficiencies as low as 1.0 db, and may operate over a large spectral bandwidth. B. Detectors and Receivers Another vital technology development for chip-scale silicon photonic communications has been CMOS-compatible photodetectors, which are required to transfer data back into the electronic domain at the destination. Detectors employing either silicon germanium (SiGe) or germanium-on-silicon (Ge-on-Si) technologies are likely candidates, since germanium provides absorption at near-infrared (NIR) wavelengths. Further, germanium is already employed, at least in low concentrations, within CMOS fabrication lines. Ge-on-Si detectors have demonstrated bandwidths and responsivities up to 40 GHz and 1 A/W, respectively, though not simultaneously [36] [41]. These detectors have also been integrated with CMOS receiver postamplifier circuits showing near picojoules per bit energy

5 10 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 16, NO. 1, JANUARY/FEBRUARY 2010 dissipation in addition to high-data-rate operation at 15 Gb/s [42]. More energy improvements are still required in CMOScompatible receiver circuit designs; as a result, many researchers foresee receiver-less operation of SiGe detectors, obtained by achieving very low detector capacitance, as a feasible means of drastically reducing the energy/bit contribution of the optoelectronic conversion [43]. Other material options for detectors include ion-implanted all-silicon detectors, which experience more NIR absorption than crystalline silicon. These detectors have shown 0.8 A/W responsivities at wavelengths near 1550 nm and bandwidths up to 10 GHz [44]. Finally, III V compound semiconductor integration with the silicon platform has recently been realized. Although it is not yet clear whether these exotic materials may feasibly be included in the back-end CMOS process, the detector performance is quite good. Since it is possible to directly integrate preamplifiers with the detector and receiver, demonstrations of 5.7 A/W at 1550 nm wavelengths and 17.5 dbm sensitivities at 2.5 Gb/s have been shown [45], [46]. C. Modulators The conversion of data from the electrical domain into the optical domain is an essential process for hybrid NoCs, making modulator performance crucial to the feasibility of chipscale photonic communications. Ideally, the modulator is fast, compact, low-power, scalable, and reliable. As the modulator will likely become one of the most recurring photonic elements on-chip, any gains achieved through simplicity within the electrooptic interface will be multiplied many times throughout the system. Typically, electronic links scale in data capacity by increasing the number of parallel wires in a bus [1] [4]. Alternatively, optical signal capacity may scale by increasing the number of parallel wavelengths on a single waveguide [47]. Therefore, the electrooptic translating device should convert between space-parallel electronics and wavelength-parallel photonics as simply and directly as possible. Previously, modulators based on both the thermooptic [48] and free-carrier [49] effects have been demonstrated in silicon. Thermooptic modulators, however, are limited to low-speed operation (on the order of a few megahertz) by the thermal time constant of silicon. Fast electrooptic modulators have been developed using carrier injection/depletion to modulate silicon s refractive index [50] [56]. Since this effect is relatively weak, lengthy carrier injection/depletion regions are required to accumulate appreciable changes in phase. This limits both the minimum footprint and the minimum power consumption of modulators based on linear phase accumulation, such as Mach Zehnder interferometers [50], [51]. To circumvent this limitation, resonator-based devices may be employed, enhancing the effects of the index modulation by circulating the photonic pathway recursively through the same compact region, allowing small-area devices to achieve high-speed modulation with low power consumption [52] [56]. Microring-resonator-based modulators consist of a ring waveguide coupled to a single straight bus waveguide [Fig. 3(a)]. Wavelengths that resonate within the ring are extracted from the Fig. 3. (a) Schematic of space-parallel (x) electronic to wavelength-parallel (λ) photonic translation using cascaded microring modulators. Dashed outlines signify doping regions, solid lines depict photonic waveguides, and dotted lines represent electronic links. (b) Microscope image showing two rings of a fabricated four-ring modulator cascade. waveguide and scattered in the ring. Carrier injection or depletion may be instigated by integrating a p-i-n diode across the microring waveguide, shifting the ring s resonance via index modulation. Functionally, the wavelength of a probe signal is aligned in the center of a transmission minimum with no applied bias. The change in carrier concentration then shifts the resonance mode away from the probe. Consequently, the probe signal, with no change in wavelength, experiences increased transmission. Electrooptic modulation results as carrier concentrations are varied at high speeds. Microdisk modulators with 4 µm diameter using carrier depletion have been demonstrated at 10 Gb/s, consuming a measured 85 fj/bit [56], while microring modulators with 12 µm diameter using carrier injection have been demonstrated at speeds up to 18 Gb/s [55]. As a result, the microresonator-based modulators show promising performance in terms of speed, size, and power consumption. Leveraging the narrow-band properties of the resonators provides a path toward achieving simplicity in the interface between electronic and photonic links as well. Because each modulator occupies a narrow spectral bandwidth (often designed with approximately 10 GHz bandwidths), the entire message translation can be implemented without wavelength multiplexing and demultiplexing by cascading a series of ring modulators along a single bus waveguide. The wavelength-parallel continuouswave (CW) lightwaves are incident on the bus waveguide, and each ring modulator encodes data onto one of the wavelength channels, ideally without affecting the other channels. As a result, no complex wavelength multiplexing and demultiplexing is required, minimizing the footprint and reducing the optical insertion loss. Furthermore, the spatially parallel electrical connections can be directed to a series of cascaded rings in close proximity [Fig. 3(a)]. Device: To demonstrate the performance of the cascaded microring modulator with respect to data integrity, measurements were taken on a four-ring cascade fabricated at the Cornell Nanofabrication Facility [57]. The device, originally reported in [58], contains four microrings [two of which are shown in

6 LEE et al.: HIGH-PERFORMANCE MODULATORS AND SWITCHES FOR SILICON PHOTONIC NETWORKS-ON-CHIP 11 Fig. 4. Transmission spectrum of the bus waveguide, displaying the four resonances associated with the four-ring cascade under no applied voltage. Fig. 3(b)] coupled to the same bus waveguide. Independent p-i-n junctions are included for independent data modulation capabilities. The rings are spaced by approximately 0.5 mm to make room for contact pads for electrical probing, but much closer spacing is possible when contact pads are not required. The rings were designed with radii of 4.98, 5.00, 5.02, and 5.04 µm to distribute a resonance mode of each ring across one freespectral range (FSR) within the C-band (around 3.6 nm channel spacing by design). The full-widths at half maximum (FWHM) of the rings transmission spectra are all approximately 0.1 nm (Fig. 4). The extinction ratios of each of the resonators modes vary from 5 to 16 db. The microring with the worst extinction displays a double dip in the shape of the ring s resonance limiting performance (inset of Fig. 4). Such a resonance splitting has been shown to result when a counterpropagating mode is induced via backscattering within the waveguide [59], [60]. Further improvements in sidewall roughness will likely mitigate future occurrences of such phenomena. Experimental setup: The experimental setup involves four lasers multiplexed onto a single fiber and inserted into an erbium-doped fiber amplifier (EDFA). The CW light is coupled to an inverse-tapered waveguide through a tapered fiber. Once on chip, it traverses a number of waveguide bends before encountering the four-ring modulator cascade. As the encoded, wavelength-parallel signal exits the chip, it passes through a polarizer. Next, the signal enters an EDFA preamplifier followed by a wavelength-tunable bandpass filter. A high-speed receiver with a transimpedance amplifier (TIA) and a limiting amplifier (LA) sends the detected channel to a BER tester (BERT) and a communications signal analyzer (CSA) for evaluation. To drive the ring modulators, a pulse pattern generator (PPG) supplies four electrically decorrelated 4-Gb/s nonreturn-to-zero (NRZ) ON OFF keyed (OOK) signals encoded with a pseudorandom bit sequence (PRBS). The space-parallel electronic signals receive amplification and bias adjustments before being injected into the contact pads through high-speed RF probes with a ground signal ground configuration. Because of the relatively large impedance mismatch (several kilohms for the Fig. 5. BER bathtub curves for the longest wavelength channel modulated by one ring of the four-ring cascade, both while only one ring and all four rings are being driven. particular device), the voltage supplied is approximately 5 V PP. More details of the experimental setup can be found in [57]. Results: For each of the four modulated optical signals, errorfree operation (defined as a BER < ) at 4 Gb/s is observed during simultaneous operation of the four rings. The BER timing margin is then recorded for the eye diagram corresponding to the longest wavelength resonance (Fig. 5). The measurement investigates the eye sampling margin with and without modulation on the other three rings. This provides information about the degradation that results when one wavelength channel passes by an active microring intended to modulate another channel. Despite some added jitter at high error rates (BER > 10 7 ), the results indicate that near the error rates of interest, the eye margin is not significantly degraded by operating the three other microring modulators. The primary challenge to such a modulation scheme is the sensitivity of the modulator performance to temperature variations, evidenced in Fig. 5 by the somewhat narrow error-free sampling region. A solution to this problem is necessary, as the microrings cannot operate in a CMP environment without some degree of temperature insensitivity. Possible directions for alleviating thermal instability in the microrings are twofold. First, through feedback, designers can implement control circuitry to monitor and tune the temperature of the rings actively during operation. This path is feasible because of the large thermooptic time constant in silicon. However, the drawbacks of this method include the added power consumption of tuners and control circuitry. Second, multiple rings can be coupled together to form a single modulator, creating higher order transmission responses [61]. The resulting broader bandwidths implement a more thermally stable device, as heat fluctuations will have to vary over a wider range to move the resonance completely away from the channel wavelength. Disadvantages of this method are the added complexity and increased channel spacing. Fortunately, the two approaches are not mutually exclusive and can be used in combination to provide additional thermal tolerance while meeting the design constraints of a particular system.

7 12 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 16, NO. 1, JANUARY/FEBRUARY 2010 In doing so, the microring modulator cascades will be able to achieve their best performance, making conversion of data from the electrical computation layers into the photonic communication layer fast, compact, low-power, scalable, and reliable. D. Switches and Routers One of the most important components of space-switched systems is the broadband switch. Not surprisingly, the performance of the switch can greatly affect the throughput, latency, and power consumption of the network. The switch may be characterized by metrics related to the time domain (e.g., switching speed and latency), frequency domain (e.g., throughput bandwidth), or space domain (e.g., footprint), in addition to power performance and data integrity. The simplest ring resonator switch is constructed from a ring resonator with two coupled bus waveguides, in contrast to the previous discussion of modulators that only require a single bus waveguide. The resonances are shifted in wavelength to create a state change so that a signal originally exiting the on-resonance (drop) port is redirected to the off-resonance (through) port. The state change allows space switching, and is implemented physically by way of the free-carrier plasma dispersion effect [62], which provides an index change within the waveguide as the electronic carrier concentration is varied. Ultimately, this can be implemented in a manner similar to the ring-based modulators [52] [56], using diode structures around the waveguides to inject or extract carriers. Experimentally, the switching can also be implemented by injecting carriers optically via absorption, avoiding complex fabrication procedures for initial proof-ofconcept devices. The absorption may be initiated using photons with energies above the bandgap of silicon, or it may be carried out through two-photon absorption (TPA) by photons between the half-bandgap and full-bandgap of silicon, so that the flexibility and availability of telecommunications components can be used to generate the control signals at the sacrifice of some efficiency. These switches leverage comb-switching to support wavelength-parallel message formats over broad optical-domain bandwidths [63]. Many wavelengths simultaneously satisfy the resonance condition within a ring resonator, and rings with larger circumference provide more resonance modes over a given optical bandwidth. Since all of the resonance wavelengths are shifted simultaneously as carriers are injected into the ring waveguide, the switch can route a wavelength-parallel message despite the narrow-band properties of each resonance mode when the wavelength channels of the optical message are aligned to the resonance wavelengths of the ring. Furthermore, all of the ring s resonances are shifted, with or without a wavelength channel aligned to the mode, when carriers are injected so that additional throughput bandwidth is provided without additional power dissipation. 1) 1 2 Ring-Resonator Switch: Now,asimple1 2ring resonator switch is described. Then, measurements showing nanosecond-scale switching speeds and hundreds of gigabitsper-second of throughput bandwidths are reviewed. Fig. 6. (a) Microscope image of the fabricated 1 2 switch with dimensional labels [63], courtesy Michal Lipson. (b) Experimental transmission spectrum of the through and drop ports of the device [64]. Device: This device was fabricated at the Cornell Nanofabrication Facility, and consists of a 200-µm-diameter ring, designed for transmission along the quasi-tm polarization (Fig. 6) [63]. The waveguide cross sections are 250 nm in height and 450 nm in width. Inverse-taper mode converters are used at the waveguide ends for efficient coupling to fiber. To demonstrate the comb-switching concept, Dong et al. initially injected two CW probe beams aligned in wavelength to two separate resonance modes of the ring, while simultaneously directing a femtosecond pulsed pump beam operating at a wavelength of 415 nm onto the ring from a vertically incident fiber [63]. The light from both tunable lasers is initially transmitted through the drop port. When the pump pulse hits the ring, carriers are generated within the ring waveguide, and both probe channels are redirected to the through port. As the free carriers recombine, the resonance of the ring is restored to its original value, and the input signals return to the drop port. The measured impulse response of the ring switch demonstrates 20% 80% rise and fall times of 100 ps and 0.93 ns, respectively. However, the measured rise time is detector-limited, and is theoretically expected to be only 15 ps. The dual wavelength-channel demonstration was an initial confirmation of multiwavelength comb-switching. Leveraging the relatively small FSR provided by the device, many channels can be switched simultaneously for multiwavelength network routing. Since the FSR of the ring resonator ( 104 GHz) is not precisely the same as the channel spacing

8 LEE et al.: HIGH-PERFORMANCE MODULATORS AND SWITCHES FOR SILICON PHOTONIC NETWORKS-ON-CHIP 13 of the dense WDM (DWDM) used to combine the laser outputs onto a single fiber (100 GHz), the overlap of the passbands is limited. This misalignment creates bands of utilizable channels approximately six or seven channel slots wide. Experimental setup: Pump and probe signals are combined onto a single fiber, passed through the switch, and analyzed. The pump and probe wavelengths are not limited to the C-band theoretically, but the wavelengths are chosen in this region in order to take advantage of amplification readily available from EDFAs. The probes are obtained from 20 distributed feedback (DFB) lasers, occupying wavelength channels C21 C27, C33 C38, and C46 C52 of the International Telecommunications Union (ITU) C-band. These CW outputs are multiplexed together using the 32-channel, 100-GHz-spaced DWDM. The channels are modulated at data rates up to 12.5 Gb/s with an NRZ-OOK signal, encoded using a PRBS of length 2 7 1, which has been generated by a PPG. Leaving the modulator, the wavelength-parallel signal travels through a 25-km singlemode-fiber (SMF) decorrelator and couples into the chip. After exiting the chip, the signal is passed through an EDFA, a wavelength-tunable bandpass filter, and a variable optical attenuator (VOA), and is then received by a high-speed receiver with a TIA/LA. The signal is analyzed with a CSA and a BERT synchronized to the PPG through a clock source. A power tap directly following the chip allows spectral monitoring on an optical spectrum analyzer (OSA). Here, the switching is performed using copropagating highspeed optical control signals within the C-band, leveraging TPA to inject carriers into the ring waveguide. The copropagating pump, located at channel C41, is provided by a tunable laser, and is externally modulated with a user-defined signal generated by a 625-MHz data timing generator (DTG), which is synchronized to the PPG. The pump is amplified using an EDFA, and combined with the probe signal before injection into the chip. The pump signal is composed of 12.8 ns pulses with a period of ns, and has an approximate average power of 20 dbm before waveguide injection. More details of the experimental setup can be found in [64]. Steady-state results: Initially, the interchannel crosstalk within the device is tested with channels on resonance [64]. All channels are first verified to operate at BERs below while simultaneously passing through the drop port of the device at 10 Gb/s. To measure the increase in power penalty due to wavelength-channel crosstalk within the ring, a BER curve is taken for channel C36 at the drop port when 16 channels are enabled (C21 C27, C34 C38, and C49 C52). The probe channels have average powers of 6 dbm before injection. The same measurement is then repeated after turning off all channels in the second group (C34 C38) except C36, leaving 12 channels, and taken again after turning off all channels except C36. No significant penalty due to wavelength crosstalk is observed (Fig. 7), indicating the possibility of further signal bandwidth scaling. Dynamic results: Multiwavelength switching is demonstrated at the nanoseconds scale by simultaneously passing the 20 channels through the drop port in the presence of the modulated pump waveform (Fig. 8) [64]. Here, the probes bypass the modulator Fig. 7. BER plots recorded at the drop port showing no observable power penalty due to wavelength crosstalk as the number of channels are increased. Fig. 8. Switched waveforms exiting the drop port with corresponding ITU channels and measured active extinction ratios labeled. A 32-point average and 50-ns time span is used in each window. No LA is used. in the setup, injecting CW light so that the switching envelope may be clearly seen. The active extinction ratios are measured from the CSA screen images, and are labeled in Fig. 8. Although the resonator modes have passive extinction ratios (i.e., the ratio of transmission through a given port at wavelengths on and off resonance) ranging from 15 to 30 db, significantly degraded extinction ratios are observed during active operation, with an average over the 20 channels of 5.6 db. Although amplified spontaneous emission (ASE) noise from the EDFA is a partial contributor to the rise in the OFF-state level, much of the degradation is expected to result from insufficiently shifted resonances due to the inefficient optical pumping scheme. Nevertheless, the concept of multiwavelength comb-switching is demonstrated over 20 channels simultaneously. The concerns about what limits the active extinction ratios using the optical pumping scheme led us to investigate the extinction ratios on both ports as a function of injected optical pump power [65]. Replacing the multichannel data source with a

9 14 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 16, NO. 1, JANUARY/FEBRUARY 2010 Fig. 9. Measured active extinction ratios versus time-averaged optical pump power inserted into the tapered fiber for both output ports. Insets show: 1) sample CSA traces using a 16-point average and 2) the geometrical layout and port labels of the switching device. Fig. 10. BER curves recorded for the through ( ), drop ( ), and reference ( ) ports on 5 of the 20 dynamically switched wavelength channels. A per-channel data rate of 12.5 Gb/s is used. single CW wavelength channel, active extinction ratios are measured at both ports for varying injected pump powers (Fig. 9). The extinction ratios continue to improve on both ports as pump power is increased until the extinction ratio measurement accuracy is exceeded (for the through port) or the maximum injection power limits of the experimental setup are reached (for the drop port). The through port performs remarkably better than the drop port. At the drop port, the extinction ratio reaches 7 db at the maximum pump power, and the steepness of the curve near this region suggests that more improvements are possible with increased pump power. At the through port, the extinction ratio is improved beyond the measurement ability of the setup with pump powers 5 db below the maximum injection levels. The next experiment attempts to dynamically switch the maximum throughput bandwidth that the experimental setup can provide to the ring switch [65]. Consequently, at the expense of slightly higher power penalty due to a higher degree of narrow-band filtering, the individual channel modulation rate is increased to 12.5 Gb/s, again using the 20 wavelength channels, achieving an aggregate data rate of 250 Gb/s on the probe signal. The pump consists of 20-ns pulses that recur every 80 ns. BER measurements are taken on the through and drop ports with back-to-back measurements taken on a reference port consisting of a single waveguide. The appropriate BERT gating signals are provided from the DTG for each port. Curves are recorded for 5 of the 20 wavelength channels spanning the spectrum (Fig. 10). Measured power penalties at the drop port for the five channels range from 2.5 to 4.1 db, with an average of 3.3 db, and at the through port, from 2.3 to 4.1 db, with an average of 3.2 db. From simulations consistent with those reported in [66], at least 1.2 db of each measured drop port power penalty is expected to result from narrow-band filtering imposed by the resonator modes on the channel s signal spectrum at the increased data rate. 2) 2 2 Ring-Resonator Switch: Next, a 2 2ringswitch, utilizing the same high-speed multiwavelength comb-switching technique described earlier, is experimentally investigated [67], [68]. Device: The device here is also fabricated at the Cornell Nanofabrication Facility. The waveguides have cross sections of 250 nm 450 nm (height width), and inverse-taper mode converters are used at each edge of the chip. The switch geometry [similar structure shown in Fig. 17(c)] consists of a crossing between two straight waveguides with two ring waveguides coupled to vertical angles of the intersection. The waveguides undergo adiabatic tapering at the crossing, expanding over a length of 30 µm toawidthof2µm prior to the 90 waveguide intersection, in order to reduce reflection losses at the crossing. The resonator modes have 3 db bandwidths of 0.1 nm (12.5 GHz) on average, designed to accommodate 10 Gb/s optical data. The present device may also be designed with a much smaller footprint by implementing the resonators in noncircular geometries, because the high confinement afforded by the SOI waveguides permits very small bending radii [26]. Moreover, the adiabatically tapered waveguide crossing may be replaced with more compact crossings, such as the one demonstrated in [30]. Ideally, the two rings have a series of resonator modes that coincide in wavelength. As with the previous 1 2 switch, when no pump is applied, the input signal wavelength is set to overlap one of these modes. As the light enters on resonance, it is coupled into the first ring resonator, then through the ring to the alternate waveguide, where it exits the switch. Therefore, without an applied pump, the switch implements the bar state. As before, an optical pump signal is used to change the state of the switch. Thus, when the pump is applied, the input lightwave is no longer affected by either of the two ring resonators, and as a result, propagates through the waveguide crossing. Consequently, when the pump is enabled, the switch implements the cross state. Once again, rings with relatively large diameters (100 µm) are employed to maximize the bandwidth of the wavelength-parallel signal. Consequently, the resonator FSR and system channel spacing are 1.6 nm.

10 LEE et al.: HIGH-PERFORMANCE MODULATORS AND SWITCHES FOR SILICON PHOTONIC NETWORKS-ON-CHIP 15 Experimental setup: The assumption that the resonator modes of the two rings in the switch overlap may not always be realized due to fabrication tolerances. Improvements may be made along this front with careful fabrication calibrating techniques [69], and by the addition of ohmic heaters placed over the ring waveguides to provide localized thermal tuning [70], [71]. For these experiments, light is simply directed from a 532-nm diode-pumped solid-state laser over one of the two rings using an optical fiber vertically incident to the chip. The appropriate ring is heated, red-shifting its resonator modes to overlap those of the unheated ring. In addition to this localized tuning, global tuning is achieved by mounting the chip on a thermoelectric cooler (TEC). The TEC provides aggregate alignment of the rings resonances with off-chip resources, such as the WDM. As with the 1 2 switch, carrier injection is performed with a TPA-inducing 1.5-µm-wavelength optical control signal. In the 2 2 switch, the pump must be applied to both rings simultaneously for proper operation. Therefore, we employ one copropagating and one counterpropagating pump signal (with respect to the probe signal s direction of propagation). Generally, the experimental setup is very similar to the one used for the 1 2 switch experiments, with the addition of the second optical pump. The setup consists of: 1) probe signal generation; 2) pump signal generation; 3) fiber waveguide coupling; 4) test and measurement. The probe signals are again generated by DFB lasers and occupy six ITU C-band channels: C22 ( nm), C24 ( nm), C33 ( nm), C35 ( nm), C37 ( nm), and C43 ( nm). The outputs are combined with the 32-channel DWDM, and are then simultaneously encoded with a 10-Gb/s NRZ-OOK signal that carries a PRBS of length generated by a PPG. The channels are decorrelated by 25 km of SMF. The pump signals are generated, modulated, and amplified using tunable lasers, modulators, and EDFAs, respectively. Pump 1, which copropagates with the probe channels, occupies channel C51 ( nm). It is combined with the probes using a single-channel 100-GHz WDM. Pump 2, located on channel C18 ( nm), is injected using an optical circulator such that it counterpropagates with the probes. The pump waveforms are again provided by the DTG. The signals are coupled to and extracted from waveguides using tapered fibers. The multichannel output is monitored using an OSA, while one probe channel propagates through a wavelength-tunable bandpass filter, an EDFA, a second filter, and a VOA, before being received by a p-i-n photodetector and a TIA/LA. The output is observed on a CSA and analyzed using a BERT, which is directly synchronized to the PPG. For the dynamic BER measurements only, a semiconductor optical amplifier (SOA) is used to gate the optical signal into 9.6 ns packets, recurring every 12.8 ns. When the SOA is used, it is driven by a signal generated from the DTG, and the DTG sends an additional signal to gate the BERT over the arrival of the packetized data. A VOA precedes the SOA to prevent satura- Fig. 11. BER curves depicting the steady-state power penalty of a six-channel WDM signal in the (a) bar state and (b) cross state. Each character corresponds to measurements on one ITU channel. The back-to-back measurements are shown using dashed lines and open characters, while the switched measurements are shown using solid lines and filled characters. tion and minimize crosstalk between the WDM channels. More details of the experimental setup can be found in [68]. Steady-state results: Initially, the switching state is toggled manually by enabling and disabling the pump, rather than providing modulated pump signals. Dynamic measurements on the 2 2 switch are discussed subsequently. The steady-state power penalty is measured for each of the six channels in bar-state [Fig. 11(a)] and cross-state [Fig. 11(b)] configurations. When the signal exits from the switch in the bar state, the pump is not activated; therefore, we expect the power penalty to result mostly from insertion loss and narrow-band spectral filtering. When the signal exits from the switch in the cross state, the pump is activated. Since the probe signals do not couple to the resonator, only a simple waveguide crossing is encountered in the optical pathway. We therefore expect the power penalty to result mostly from effects induced by the pump signals, such as TPA, free-carrier absorption (FCA), and ASE noise emitted from the EDFA.

11 16 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 16, NO. 1, JANUARY/FEBRUARY 2010 Fig. 13. CSA traces showing the switched CW single-channel probe through the (left) bar and (right) cross states. The CSA uses a time and amplitude scale of 10 ns/division (80 ns span) and 100 µw/division (800 µw span), respectively, with a 16-point average. The zero-power level is emphasized by overlaying a lighter trace that was taken with the input disconnected. Fig. 12. BER curves depicting the interchannel crosstalk for varying multichannel injection powers. Curves are shown for a six-channel (solid lines, filled symbols) and single-channel (dashed lines, open symbols) signal propagating through the bar state. All measurements are taken on channel C35. The inset plots the points at which the trendlines intersect a BER of 10 9 as a function of the injection power of channel C35. To measure the bar-state power penalties, the input signal wavelengths are aligned along the resonator modes while no pump is applied, and six BER curves are recorded, one for each channel. The back-to-back curves are obtained by cooling the TEC on which the chip is mounted until the resonator modes are shifted away from the signal wavelengths so that the signals no longer pass through the ring. The output is then gathered from the cross-state port, and six back-to-back BER curves are recorded. An attenuator is inserted prior to the EDFA for the back-to-back curves to compensate the ring insertion losses, ensuring that consistent powers enter the EDFA. The cross-state power penalties are measured using the same channels at the same wavelengths. The pump is activated, shifting the resonator mode wavelengths, and the signals are collected from the switch in the cross state. Six BER curves are recorded. The back-to-back curves are obtained in the same manner as before. The resulting power penalties range between 0.1 and 1.2 db for the bar state and between 0.0 and 0.5 db for the cross state. The larger bar-state power penalties are consistent with previous measurements [64] [66]. Next, the interchannel crosstalk within the ring is characterized as a function of injected optical power. Since the optical intensities are increased within ring resonators due to constructive interference, which lowers the input power thresholds required to observe nonlinear phenomena, the bar-state paths will have the strongest opportunity for interchannel wavelength crosstalk. Therefore, BER curves are taken for channel C35, as it propagates through the switch in the bar state during two cases: 1) with the other five wavelength channels enabled and 2) with the other channels disabled (Fig. 12). Here, the probe channels propagate through a VOA, an EDFA, and a second VOA before injection into the chip. The first VOA is set to provide appropriate input power levels to the EDFA, while the second is varied over five settings. A BER curve is recorded for channel C35 for each of the five settings. Then, all channels are disabled except C35, and a BER curve is recorded for five new settings that match the five previous injection powers of channel C35. (The five VOA settings differ slightly between the one-channel and six-channel experiments because the EDFA provides more gain in the single-channel case than it does in the six-channel case.) The power values listed in Fig. 12 represent the time-averaged power using a 50% duty cycle for PRBS-encoded data. The values listed in the legend show the sum of the powers over the six channels (total time-averaged power) before injection into the tapered fiber. The inset of Fig. 12 plots the receiver sensitivity at a BER of 10 9 for each of the ten BER curves as a function of the power of channel C35 before injection into the tapered fiber. The inset shows that the receiver sensitivity curve shifts inconsequentially (about 0.1 db on average) when the five additional channels are enabled, indicating negligible interchannel crosstalk in the switch for total injection powers up to 23 mw. The measurement was limited in the maximum injection power by the saturation output power of the available multichannel EDFA. Dynamic results: To take nanosecond-scale dynamically switched measurements, the two pump signals are modulated with square pulses having duration of 12.8 ns and periodicity of ns, giving a 12.5% duty cycle. The two pumps are synchronized so that the pulses coincide in time at the switch. By inserting a single-channel CW probe signal into the device, we observe the envelope profile of the switched signal on the CSA. From the scope traces (Fig. 13), it can be seen that the rise and fall times are less than 2 ns each for both switch outputs. The ringing in the signal, seen just after the pumps are disabled, is attributed to undershoot in the waveform of the drive voltage supplied to the modulator. The ringing observed over the duration of the state in which the pumps are enabled is caused by instability in the optical pumping scheme. As the high-power pump changes the ring waveguide s index of refraction, it not only provides switching of the probe signal, but also simultaneously decouples itself from the resonator, because the pump is of fixed wavelength. As a result, the ring index returns to its previous state when the injected carriers decay, and the pump is again coupled to the ring, restarting the process. The active extinction ratios and relative insertion losses of the switch are determined from the CSA traces. Extinction ratios of

12 LEE et al.: HIGH-PERFORMANCE MODULATORS AND SWITCHES FOR SILICON PHOTONIC NETWORKS-ON-CHIP 17 Fig. 15. BER curves depicting the dynamic power penalty of a six-channel WDM signal propagating through the bar and cross states. Fig. 14. CSA traces of packetized data encoded on C35 (a) before injection; (b) at the output of the switch under the bar state; and (c) at the output of the switch under the cross state. The time scale is 20 ns/division; no averaging is used. The apparent eye diagram is a digital sampling artifact (bar) and 7.8 db (cross) are observed. The insertion loss through the cross state is about 4 db higher than that observed through the bar state. This is believed to occur mostly because of the TPA-induced FCA generated by the high-power pumps. The absorption causes higher losses for the probe during the section of the scope trace representing when the probe coincides with the pump in time. In the present case, the probe copropagates with one of the pump signals over centimeter-scale distances in the cross state. Much of this loss can be avoided in electronic injection schemes, where the carrier injection will be localized near the ring waveguide. In addition to affecting the switch path uniformity, the nonlinear loss also degrades the interport crosstalk. The interport crosstalk is defined for a 2 2 switch with input ports A and B and output ports C and D, while injecting on port A with the switch configuration set as A-to-C (or A-to-D). It is defined as the ratio of the leakage power through A-to-D (A-to-C) to the transmitted power through A-to-C (A-to-D). This metric is important for characterizing the effect of the finite extinction ratios on other messages in the switch, as it describes the amount of power that may be leaked to the undesired port adversely affecting another message in the switch. The interport crosstalk experienced for the cross-state path (the path degraded by the nonlinear loss) is 7.0 db; in the case of the bar-state path, the interport crosstalk is 12.3 db. Finally, the dynamic power penalty of the switch is measured using the same six-channel probe source. Here, the probe channels are gated into 9.6-ns packets recurring in 12.8-ns slots using an SOA, giving a packet duty cycle of 75%. The same pump signal is used so that every eighth packet is switched to the cross-state output port, while the rest travel through the bar state (Fig. 14). The back-to-back curves (Fig. 15) are taken with the pumps disabled and the resonances realigned to the wavelength channels using the TEC controller. The BERT is also gated over the arrival of the switched data packets, separately for each measurement (cross and bar states). The results show approximately 1.1 db of difference between the two back-toback curves, attributed to the narrow-band filtering penalty since one port passes through a ring and one does not. An additional bar-state power penalty of 1.9 db is incurred under dynamic operation. This is caused by slight power fluctuations imposed on the switched data packets, which exist under the dynamic operation of the switch and likely result from small thermal variations. Since the thermal time constant is longer than the pump periodicity, these variations occur slowly across many pumping cycles, but affect parameters such as the optimal receiver threshold setting over the course of measuring one BER curve. For the cross state, an overall power penalty of 3.5 db is measured. The causes of this penalty are divided between the nonlinear losses, the ASE noise from the pumps, and the dynamic operation. Note that the nonlinear losses and ASE accumulation were also present during the static BER measurements, which resulted in power penalties of less than or equal to 0.5 db. However, the power fluctuations within the packets that are switched into the cross state, which are manifest by the declining power seen across the switched packet [Fig. 14(c)], are now observable over the duration of a single packet. Therefore, the fluctuations must be attributed to carrier dynamics, as they occur much too fast for thermal effects. Thus, the pump signal is not able to maintain an adequate level of charge over the entire length of the 9.6 ns data packet. This is validated by the opposite shape of the suppressed packet in Fig. 14(b), and is clearly an example of the performance problems that can be mitigated using electronic means of carrier injection. As in [54], voltage waveforms may

13 18 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 16, NO. 1, JANUARY/FEBRUARY 2010 Fig. 17. (a) Schematic of the original 4 4 photonic router highlighting a contention state where one signal, represented by the white arrows, requests the path east-to-north, while another signal, represented by the black arrows, requests the path north-to-west. A contention exists on the lower horizontal waveguide. Images of the fabricated 4 4 switch: (b) optical microscope image showing gold contacts to nichrome heaters placed above the ring waveguides and (c) scanning electron microscope image showing the details of one of the 2 2 switches within the device before metal deposition. Fig. 16. (a) Schematic of the original 4 4 photonic router with four 2 2 switches and an electronic router (ER). (b) Schematic of the redesigned 4 4 photonic router with two 2 2 switches, four 1 2 switches, and an ER. be shaped to provide a constant level of carriers within the ring waveguide over a given length of time. Furthermore, when electronic injection is used, the instabilities of the in-plane optical pumping scheme are not encountered. 3) 4 4 Nonblocking Photonic Router: In our former work [13], a 4 4 switch was created using an arrangement of the 2 2 ring switches. A 4 4 switch is highly desirable given the usefulness of 2-D grid-based network topologies for communications systems that will be laid out in a single physical plane of a CMP. In initial 4 4 switch designs, simplicity was the primary goal, and the arrangement shown in Fig. 16(a) was adopted. Ports are labeled geographically (north, south, east, and west) for convenience. In this structure, 2 2 switches are arranged into four quadrants and interconnected by waveguides. Each quadruplet of 2 2 switches is controlled by an electronic router, forming a 4 4 switch. Electronic control packets are received in the electronic router, where they are processed, and sent to their next hop along the electronic network layer, while the individual rings within the 4 4switchareset(ON or OFF) according to the information in the control packet. Once an electronic control packet completes its journey through a sequence of electronic routers, an optical pathway is established through a series of rings and waveguide crossings to route the optical message from source to destination. The previously studied 4 4 switch was internally blocking, requiring the implementation of network-level routing algorithms in order to obtain acceptable performance [13], [14]. Fig. 17(a) demonstrates a case of internal blocking that may occur when multiple messages are routed through the initial 4 4 switch simultaneously. A new strictly nonblocking switch [Fig. 16(b)] has been designed by increasing the number of internal paths [14]. However, the number of ring resonators remains the same, which implies that the electrical power dissipation may not be increased. Moreover, the maximum number of times a signal may pass through a ring resonator drop port within a single 4 4 switch is still only once, which is important for meeting the optical loss budget. The redesigned switch guarantees an internal path from any input port to any output port, as long as no two packets are destined for the same output (output port contention), and as long as packets are not allowed to ingress and egress from the same port (U-turn). Due to the small footprint of the individual components and the simplicity of the electronic router, which only handles small control packets, the new routing switch can still occupy a very small area. Device: The photonic elements of the 4 4switchwerefabricated on a monolithic SOI platform at the Cornell Nanofabrication Facility by Sherwood-Droz et al. [72]. Ohmic heaters were constructed over each ring to allow low-speed switching and postfabrication tuning of the resonators [Fig. 17(b)]. All the waveguides have dimensions of 450 nm 250 nm, and the rings have a 10 µm radius. The waveguide crossings are implemented with tapers to expanded widths at the intersecting region, reducing losses and reflections [Fig. 17(c)]. The crossing is simulated to have an insertion loss of 0.18 db with crosstalk to the intersecting waveguide below 20 db [72]. Experimentally, the rings resonances have a 3 db bandwidth of about 0.3 nm. Experimental setup: In previous experiments, a single input path and a single output path have been used to characterize the devices, due to the large physical size of the fiber holders and positioners relative to the chip, which make it infeasible

14 LEE et al.: HIGH-PERFORMANCE MODULATORS AND SWITCHES FOR SILICON PHOTONIC NETWORKS-ON-CHIP 19 Fig. 18. CSA images showing pattern traces on each output port (columns) and in each switching state (rows) with a single-wavelength signal injected at the north input port. Each trace window spans 5 ns in time, and has amplitude scales of 100 µw/division, except for the input pattern and the east output under the north-to-east configuration, both of which have 200 µw/division amplitude scales. A PRBS pattern with a length of is used to lock the CSA to the pattern trace. Fig. 19. Eye diagrams for the three wavelength-parallel channels (columns) routed through the three switch configurations (rows), with a time span of 200 ps each and a PRBS pattern length of to mount two or more fibers on the same side of the chip. Nevertheless, the redesigned 4 4 switch is fabricated with both north and both west waveguides directed to one side of the chip, and both south and both east waveguides directed to the other side. As a result, the former coupling setup is inadequate to fully characterize the switch operation. To circumvent this limitation, a modification to the experimental coupling setup is carried out that allows three coupling paths. The modification involves replacing the tapered fiber on one side of the chip with free-space coupling, as in [73], so that one side of the chip is coupled with a tapered fiber, and the other side of the chip uses a single lens to couple two free-space beams to two waveguides. The modification, while increasing coupling losses, allows the full investigation of all three output ports when injecting into a single input port [74]. The experimental setup includes three tunable laser sources with the outputs combined using a 33/33/33% directional coupler. The lightwaves are simultaneously modulated with a 10-Gb/s NRZ-OOK signal, decorrelated by 3.4 ns between adjacent channels, and amplified in an EDFA; the optical message is subsequently injected into the chip. At the output of the chip, part of the extracted signal is monitored on an OSA, while the remainder is preamplified by another EDFA, filtered to select the desired wavelength channel, and received. The signal is evaluated on a CSA and a BERT. More details of the experimental setup can be found in [74]. Steady-state results: The operation of the device is demonstrated by evaluating the signal that egresses from the east, south, and west ports while injecting into the north port. The rings are tuned statically via the heaters to change the switch state. Pattern traces of the signal exiting the destination ports, along with crosstalk observed on the other ports, are illustrated for all switch configurations (Fig. 18). Fig. 20. BER curves for the three wavelength-parallel channels routed through the three switch configurations. The top, center, and bottom plots represent the shortest, center, and longest wavelength channels, respectively. Utilizing three consecutive resonance modes of the ring resonators, a three-channel wavelength-parallel signal is routed through the aforementioned switch configurations. Wavelengths of 1538, 1546, and 1554 nm are employed. Eye diagrams before injection into the chip and at each destination port are recorded for all three wavelength channels (Fig. 19). Additionally, BER curves are taken for the three wavelength channels in each switch configuration (Fig. 20). The back-to-back curves are taken by replacing the chip with a VOA set to mimic the minimum fiber-to-fiber losses through the chip, which are observed for the path from north to east. Power penalties are approximately 1.3 db for the north-to-west configuration, which observed the largest fiber-to-fiber losses due to passing through the free-space coupling portion of the setup twice. Both of the other states

15 20 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 16, NO. 1, JANUARY/FEBRUARY 2010 demonstrate power penalties below 1 db for each wavelength channel. V. CONCLUSION We have experimentally demonstrated the functionality and practicability of multiple subsystems required for photonic onchip networks, showing the ability of modulators and switches to surpass the speeds and bandwidths required by next-generation CMPs. Meanwhile, increasing levels of silicon photonic integration have been displayed, with devices scaling from one to eight resonators. Substantial opportunities for innovation remain within this effort to integrate CMOS-compatible photonics with commercial processing systems, however. Creative solutions for thermal management, optical packaging, and process flow will be required. Although the future integration of these subsystems, and the joining of electronic and photonic elements, will present a formidable set of challenges, the potential rewards in terms of CMP performance will be well worth the effort for a large class of computing applications. REFERENCES [1] P. Kongetira, K. Aingaran, and K. Olukotun, Niagara: A 32-way multithreaded SPARC processor, IEEE Micro, vol. 25, no. 2, pp , Mar./Apr [2] J. Dorsey, S. Searles, M. Ciraula, S. Johnson, N. Bujanos, D. Wu, M. Braganza, S. Meyers, E. Fang, and R. Kumar, An integrated quad-core Opteron processor, in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2007, pp [3] U. G. Nawathe, M. Hassan, K. C. Yen, A. Kumar, A. Ramachandran, and D. Greenhill, Implementation of an 8-core, 64-thread, power-efficient SPARC server on a chip, IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 6 20, Jan [4] B. Stackhouse, B. Cherkauer, M. Gowan, P. Gronowski, and C. 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17 22 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 16, NO. 1, JANUARY/FEBRUARY 2010 Benjamin G. Lee (S 04 M 09) received the B.S. degree from Oklahoma State University, Stillwater, in 2004, and the M.S. and Ph.D. degrees from Columbia University, New York, in 2006 and 2009, respectively, all in electrical engineering. He is currently a Postdoctoral Researcher at IBM T. J. Watson Research Center, Yorktown Heights, NY. His research interests include silicon photonic devices, integrated optical switches and networks for high-performance computing systems, and all-optical processing systems. Dr. Lee is a member of the IEEE Photonics Society and the Optical Society of America. Aleksandr Biberman (S 05) received the B.S. degree (with honors) in electrical and computer and systems engineering from Rensselaer Polytechnic Institute, Troy, NY, in 2006, and the M.S. degree in electrical engineering in 2008 from Columbia University, New York, where he is currently working toward the Ph.D. degree at the Department of Electrical Engineering. Johnnie Chan (S 08) received the B.S. degree in computer engineering and the M.S. degree in electrical engineering from the University of Virginia, Charlottesville, in 2005 and 2007, respectively. He is currently working toward the Ph.D. degree at the Department of Electrical Engineering, Columbia University, New York. Keren Bergman (S 87 M 93 SM 07 F 09) received the B.S. degree from Bucknell University, Lewisburg, PA, in 1988, and the M.S. and Ph.D. degrees from Massachusetts Institute of Technology, Cambridge, in 1991 and 1994, respectively, all in electrical engineering. She is currently a Professor of electrical engineering at Columbia University, New York, where she is also the Director of the Lightwave Research Laboratory. Her current research interests include optical interconnection networks for advanced computing systems, photonic packet switching, and nanophotonic networks-on-chip. She is the Editor-in-Chief of the Journal of Optical Networking. Prof. Bergman is a Fellow of the Optical Society of America and an Associate Editor of the IEEE PHOTONICS TECHNOLOGY LETTERS.