Customized Computing for Power Efficiency. There are Many Options to Improve Performance

Transcription

1 ustomized omputing for Power Efficiency Jason ong ULA omputer Science Department There are Many Options to Improve Performance Page 1

2 Past Alternatives -- Frequency Scaling Source : Shekhar Borkar, Intel urrent Alternatives: Parallelization Parallelization Source : Shekhar Borkar, Intel Page 2

3 Multi-core Processors Sun UltraSPAR T2 Microprocessor 8 ores 64 threads Tilera TILE64 multi-core Processor Warehouse of omputers IBM BlueGene/L No.1 in the newest Top500 Page 3

4 But Power Remain to Be a Limiting Factor ost of computing HW acquisition Energy bill Heat removal Space Power Will Be the Driver for Acceptance of ustomized omputing Parallelization ustomization Source : Shekhar Borkar, Intel Page 4

5 ULA Experience -- Lithography Simulation Acceleration Simulation of the optical imaging process omputational intensive and quite slow for full-chip simulation Synthesized into Stratix-II FPGA on XDI platform using AutoPilot Experiment Results [FPGA 2008] 15X speedup using a 5 by 5 partitioning over Opteron 2.2G 4G RAM Logic utilization around 25K ALUT (and 8K is used in the interface framework rather than design) Power utilization less than 15W in FPGA comparing with 86W in Opteron248 lose to 100X (5.8 x 15) improvement on energy efficiency Page 5

6 A Lot More is Needed for Power-Efficient ustomized omputing More power-efficient efficient programmable fabrics apability to do power gating, voltage and frequency scaling A A powerful, fully automated /++ to FPGA compiler Taking full advantages of various power optimization options in a transparent way ustomization beyond just FPGA fabrics Application-specific instruction-set set processors (ASIP) Application-specific processor networks (ASPN) More power efficient programmable (global) interconnects E.g., RF-interconnects RF-Interconnects -- Power Efficient Programmable (Global) Interconnect Solution Page 6

7 Limited R Wires Bandwidth f 45nm MOS Technology Data Rate: 4 Gbit/s f T of 45nm MOS can be as high as 240GHz Baseband signal bandwidth only about 4GHz 98.4% of available bandwidth is wasted Open Question: How to take advantage of full-bandwidth of modern MOS? ULA 90nm MOS VO at 324GHz (ISS 2008) GHz VO -80 MOS VO designed by Frank hang s group at ULA, fabricated in 90nm process Pout (dbm) Frequency (GHz) MOS Voltage ontrolled Oscillator, measured with a subharmonic mixer and driven with a 80 GHz synthesizer local oscillator. The mixing frequency is (f( VO - 4*f LO )=f IF, or f VO -4*(80 GHz)= 3.5 GHz, yielding f VO = GHz! On-Wafer VO Test Setup at JPL *Huang, D., LaRocca T., hang, M.-. F., 324GHz MOS Frequency Generator Using Linear Superposition Technique IEEE International Solid-State ircuits onference (ISS), , (Feb 2008) San Francisco, A Page 7

8 Multiband RF-Interconnect Signal Spectrum Signal Power Signal Power Signal Power Signal Power In TX, each mixer up-converts individual baseband streams into specific frequency band (or channel) N different data streams (N=6 in exemplary figure above) may transmit simultaneously on the shared transmission medium to achieve higher aggregate data rates In RX, individual signals are down-converted by mixer, and recovered after low-pass filter Advantages of RF-Interconnect (RF-I) Latency speed-of of-light data transmission Bandwidth high aggregate data rate through simultaneous transmissions on multiple bands of RF modulated signals Area avoid extensive use of repeaters Energy low overall energy bit Reconfigurability efficient bidirectional and tunable communications via shared on/off-chip transmission lines or off-chip antennas Page 8

9 Simple RF-I I Topology Four No omponents Tunable Tx/Rx /Rx s Arbitrary topologies Arbitrary bandwidths RF-I Transmission Line Bundle > > > > > > > > No omponent One physical topology can be configured to many virtual topologies Tx/Rx Pipeline/Ring Bus Multicast Fully rossbar onnected RF-I I for Multi-ore On-hip ommunication [HPA 2008, MIRO 2008] 10x10 mesh of pipelined routers No runs at 2GHz XY routing 64 4GHz 3-wide 3 processor cores Labeled aqua 8KB L1 Data ache 8KB L1 Instruction ache 32 L2 ache Banks Labeled pink 256KB each Organized as shared NUA cache 4 Main Memory Interfaces Labeled green RF-I I transmission line bundle Black thick line spanning mesh Page 9

10 RF-I I Logical Organization Logically: - RF-I behaves as set of N express channels - Each channel assigned to src, dest router pair (s,d) Reconfigured by: - remapping shortcuts to match needs of different applications LOGIAL BA Power Savings bytes bytes A Requires high bw to communicate w/ B We can thin the baseline mesh links From 16B to 8B to 4B B RF-I I makes up the difference in performance while saving overall power! RF-I I provides bandwidth where most necessary Baseline R wires supply the rest Over 60% power reduction A lot of potential for global interconnects in programmable fabrics Page 10

11 oncluding Remarks -- A Lot Opportunities in Power- Efficient ustomized omputing More power-efficient efficient programmable fabrics Options to do power gating, voltage and frequency scaling A A powerful, fully automated /++ to FPGA compiler Taking full advantages of power optimization options in a transparent way ustomization beyond just FPGA fabrics Application-specific instruction-set set processors (ASIP) Application-specific processor networks (ASPN) More power efficient programmable (global) interconnects E.g., RF-interconnects Page 11