N Channel Enhancement Mode Silicon Gate
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1 SEMICONDUCTOR TECHNICAL DATA Order this document by MTP2NE/D N Channel Enhancement Mode Silicon Gate This advanced TMOS E FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain to source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Designed to Eliminate the Need for External Zener Transient Suppressor Absorbs High Energy in the Avalanche Mode Commutating Safe Operating Area (CSOA) Specified for Use in Half and Full Bridge Circuits Source to Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and (on) Specified at Elevated Temperature G D S Motorola Preferred Device TMOS POWER FET 2 AMPERES VOLTS RDS(on) =.6 OHM CASE 22A 6, Style 5 TO 22AB MAXIMUM RATINGS (TC = 25 C unless otherwise noted) Rating Symbol Value Unit Drain Source Voltage S Drain Gate Voltage (RGS =. MΩ) VDGR Gate Source Voltage Continuous Gate Source Voltage Single Pulse (tp 5 µs) VGS ±2 ± Drain Current Continuous Drain Current Single Pulse (tp µs) ID IDM 2 3 Adc Total Power TC = 25 C Derate above 25 C PD Watts W/ C Operating and Storage Temperature Range TJ, Tstg 55 to 75 C UNCLAMPED DRAIN TO SOURCE AVALANCHE CHARACTERISTICS (TJ 75 C) Single Pulse Drain to Source Avalanche Energy Starting TJ = 25 C (VDD = 25 V, VGS = V, L =.3 mh, RG = 25 Ω, Peak IL = 2 A) (See Figures 5, 6 and 7) THERMAL CHARACTERISTICS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient EAS 29 mj RθJC RθJA C/W Maximum Lead Temperature for Soldering Purposes, / from case for seconds TL 26 C Designer s Data for Worst Case Conditions The Designer s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves representing boundaries on device characteristics are given to facilitate worst case design. E FET and Designer s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV Motorola, Inc. TMOS 996 Power MOSFET Transistor Device Data
2 ELECTRICAL CHARACTERISTICS (TJ = 25 C unless otherwise noted) OFF CHARACTERISTICS Drain to Source Breakdown Voltage (VGS =, ID = 25 µadc) Temperature Coefficient (positive) Zero Gate Voltage Drain Current ( = V, VGS = ) ( = V, VGS =, TJ = 5 C) Characteristic Symbol Min Typ Max Unit V(BR)DSS Gate Body Leakage Current, Forward (VGSF = 2, = ) IGSSF nadc Gate Body Leakage Current, Reverse (VGSR = 2, = ) IGSSR nadc ON CHARACTERISTICS* Gate Threshold Voltage ( = VGS, ID = 25 µadc) Temperature Coefficient (negative)µ IDSS VGS(th) Static Drain Source On Resistance (VGS =, ID = 6. Adc) RDS(on).25.6 Ohm Drain Source On Voltage (VGS = ) (ID = 2 Adc) (ID = 6. Adc, TJ = 5 C) (on) Forward Transconductance ( 5 V, ID = 6. A) g FS. 5. mhos mv/ C µa mv/ C DYNAMIC CHARACTERISTICS Input Capacitance Reverse Transfer Capacitance Output Capacitance ( = 25 V, VGS =, f =. MHz) See Figure Ciss 6 pf Crss 7 Coss 23 SWITCHING CHARACTERISTICS (TJ = C) Turn On Delay Time td(on) ns Rise Time (VDD = 5 V, ID = 2 A, tr 6 VGS = V, RG = 2 Ω) Turn Off Delay Time See Figure 7 td(off) 2 Fall Time tf 3 Gate Charge QT 26 nc ( = V, ID = 2 A, Q. VGS = ) See Figures 5 and 6 Q2 Q3. SOURCE DRAIN DIODE CHARACTERISTICS* Forward On Voltage (IS = 2 A, VGS = ) VSD. 2.5 (IS = 2 A, VGS =, TJ = 5 C).3 Reverse Recovery Time (IS = 2 A, VGS =, dis/dt = A/µs, VR = 5 V) trr ns INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead.25 from package to center of die) Internal Source Inductance (Measured from the source lead.25 from package to source bond pad) * Pulse Test: Pulse Width 3 µs, Duty Cycle 2.%. Ld Ls 7.5 nh 2 Motorola TMOS Power MOSFET Transistor Device Data
3 TYPICAL ELECTRICAL CHARACTERISTICS TJ = 25 C VGS = V 9 V V 7 V 6 V 5 V V TJ = 55 C 25 C C 2 3, DRAIN TO SOURCE VOLTAGE (VOLTS) VGS, GATE TO SOURCE VOLTAGE (VOLTS) Figure. On Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN TO SOURCE RESISTANCE (OHMS) VGS = V TJ = C 25 C 55 C RDS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED) VGS = V ID = 6 A TJ, JUNCTION TEMPERATURE ( C) Figure 3. On Resistance versus Drain Current Figure. On Resistance Variation with Temperature Vin k 5 V 7 k + V VDD 7 k 2N39 ma 2N39 V k FERRITE BEAD. µf Figure 5. Gate Charge Test Circuit SAME DEVICE TYPE AS DUT DUT Vin = 5 Vpk; PULSE WIDTH µs, DUTY CYCLE %. V GS, GATE TO SOURCE VOLTAGE (VOLTS) Q VGS QT Q2 ID = 2 A = V TJ = 25 C Q Qg, TOTAL GATE CHARGE (nc) Figure 6. Gate To Source and Drain To Source Voltage versus Gate Charge 6 2 V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Motorola TMOS Power MOSFET Transistor Device Data 3
4 SAFE OPERATING AREA INFORMATION FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum drain to source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25 C and a maximum junction temperature of 75 C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, Transient Thermal Resistance General Data and Its Use provides detailed instructions. SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) of Figure 9 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, BS. The switching SOA shown in Figure 9 is applicable for both turn on and turn off of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than: TJ(max) TC RθJC t, TIME (ns) VDD = 5 V ID = 2 A VGS = V TJ = 25 C RG, GATE RESISTANCE (OHMS) Figure 7. Resistive Switching Time versus Gate Resistance tr tf td(off) td(on) OPERATION LIMITED IN THIS AREA BY RDS(on) VGS = 2 V SINGLE PULSE TC = 25 C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT.., DRAIN TO SOURCE VOLTAGE (VOLTS) dc 3 µs ms ms 2 TJ 75 C 2 6, DRAIN TO SOURCE VOLTAGE (VOLTS) 2 Figure. Maximum Rated Forward Biased Safe Operating Area Figure 9. Maximum Rated Switching Safe Operating Area r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = SINGLE PULSE P(pk) t, TIME (ms) t t 2 DUTY CYCLE, D = t/t2 Figure. Thermal Response RθJC(t) = r(t) RθJC RθJC =.9 C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t TJ(pk) TC = P(pk) RθJC(t) Motorola TMOS Power MOSFET Transistor Device Data
5 COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure 2 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the source-drain diode has undergone forward bias. The curve shows the limitations of IFM and peak for a given rate of change of source current. It is applicable when waveforms similar to those of Figure are present. Full or half-bridge PWM DC motor controllers are common applications requiring CSOA data. Device stresses increase with increasing rate of change of source current so dis/dt is specified with a maximum value. Higher values of dis/dt require an appropriate derating of IFM, peak or both. Ultimately dis/dt is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. (pk) is the peak drain to source voltage that the device must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of commutation. VR is specified at rated BS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances in Motorola s test circuit are assumed to be practical minimums. 5 V 9% IS % VGS IFM ton Vf IRM (pk) dls/dt d/dt VdsL Figure. Commutating Waveforms trr.25 IRM VR MAX. CSOA STRESS AREA I S, SOURCE TO DRAIN CURRENT (AMPS) TJ 75 C IS = 2 A dis/dt A/µs VR V VGS VR + IFM + 2 V RGS IS DUT Li , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2 VR = % OF RATED BS VdsL = Vf + Li dls/dt Figure 2. Commutating Safe Operating Area (CSOA) Figure 3. Commutating Safe Operating Area Test Circuit Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola TMOS Power MOSFET Transistor Device Data 5
6 C, CAPACITANCE (pf) = V VGS = V Ciss Coss Crss VGS GATE TO SOURCE OR DRAIN TO SOURCE VOLTAGE (VOLTS) Figure. Capacitance Variation E AS, SINGLE PULSE AVALANCHE ENERGY (mj) PEAK IL = 2 A VDD = 25 V TJ, STARTING JUNCTION TEMPERATURE ( C) Figure 5. Maximum Avalanche Energy versus Starting Junction Temperature BS L IL VDD IL(t) t RG VDD Figure 6. Unclamped Inductive Switching Test Circuit tp t, (TIME) Figure 7. Unclamped Inductive Switching Waveforms PACKAGE DIMENSIONS H Q Z L V G B 2 3 N D A K F T U R J S C T SEATING PLANE NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. CASE 22A 6 TO 22AB ISSUE Y STYLE 5: PIN. GATE 2. DRAIN 3. SOURCE. DRAIN INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G H J K L N Q R S T U V.5.5 Z. 2. How to reach us: USA / EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi SPD JLDC, Toshikatsu Otsuki, P.O. Box 292; Phoenix, Arizona F Seibu Butsuryu Center, 3 2 Tatsumi Koto Ku, Tokyo 35, Japan MFAX: RMFAX@ .sps.mot.com TOUCHTONE (62) HONG KONG: Motorola Semiconductors H.K. Ltd.; B Tai Ping Industrial Park, INTERNET: NET.com 5 Ting Kok Road, Tai Po, N.T., Hong Kong Motorola TMOS Power MOSFET Transistor MTP2NE/D Device Data
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