Designer s Data Sheet TMOS E FET. High Energy Power FET

Size: px

Start display at page:

Download "Designer s Data Sheet TMOS E FET. High Energy Power FET"

Violet Palmer
5 years ago
Views:

1 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP2NEZL/D Designer s Data Sheet TMOS E FET. High Energy Power FET N Channel Enhancement Mode Silicon Gate This advanced TMOS power FET is designed to withstand high energy in the avalanche and mode and switch efficiently. This new high energy device also offers a gate to source zener diode designed for 4 kv ESD protection (human body model). ESD Protected 4 kv Human Body Model 4 V Machine Model Avalanche Energy Capability Internal Source To Drain Diode Designed to Replace External Zener Transient Suppressor Absorbs High Energy in the Avalanche Mode D MTP2NEZL TMOS POWER FET 2 AMPERES VOLTS R DS(on) =.8 OHM G S CASE 22A, Style 5 TO 22AB MAXIMUM RATINGS (T C = 25 C unless otherwise noted) Rating Symbol Value Unit Drain Source Voltage V DSS Drain Gate Voltage (R GS =. MΩ) V DGR Gate Source Voltage Continuous Gate Source Voltage Non Repetitive (t p ms) Drain Current Continuous C Single Pulse (t p µs) Total Power T C = 25 C Derate above 25 C V GS ±5 V GSM ±2 I D I D I DM P D 45.3 Vpk Adc Apk Watts W/ C Operating and Storage Temperature Range T J, T stg 55 to 5 C Single Pulse Drain to Source Avalanche Energy Starting (V DD = 25, V GS = 5., I L = 2 Apk, L =. mh, R G = 25 Ω) E AS 72 mj Thermal Resistance Junction to Case Junction to Ambient R θjc 2.78 R θja 2.5 C/W Maximum Lead Temperature for Soldering Purposes, /8 from case for seconds T L 2 C Designer s Data for Worst Case Conditions The Designer s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves representing boundaries on device characteristics are given to facilitate worst case design. E FET and Designer s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Motorola, Inc. TMOS 995 Power MOSFET Transistor Device Data

2 MTP2NEZL ELECTRICAL CHARACTERISTICS ( unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain Source Breakdown Voltage (V GS =, I D =.25 madc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (V DS =, V GS = ) (V DS =, V GS =, T J = 25 C) Gate Source Breakdown Voltage (V DS = V, I G = ma) V (BR)DSS I DSS. mv/ C µadc 8 Gate Body Leakage Current (V GS = ±, V DS = V, ) (V GS = ±, V DS = V, T J = 5 C) I GSS 5 nadc µadc ON CHARACTERISTICS () Gate Threshold Voltage (V DS = V GS, I D = 25 µadc) Temperature Coefficient (Negative) V GS(th). Static Drain Source On Resistance (V GS = 5., I D =. Adc) R DS(on).8 Ohm Drain Source On Voltage (V GS = 5. ) (I D = 2 Adc) (I D =. Adc, T J = 25 C) V DS(on) Forward Transconductance (V DS = 8., I D =. Adc) g FS 3..8 mhos mv/ C DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (V DS = 25, V GS =, f =. MHz) C iss 43 pf C oss C rss 5 SWITCHING CHARACTERISTICS (2) Turn On Delay Time t d(on) 7 9 ns Rise Time (V DS = 3, I D = 2 Adc, t r Turn Off Delay Time V GS =5 5., R G = 9. Ω) t d(off) Fall Time Gate Charge (See Figures 8 & 9) SOURCE DRAIN DIODE CHARACTERISTICS Forward On Voltage () (I S = 2 Adc, V GS = ) (I S = 2 Adc, V GS =, T J = 25 C) Reverse Recovery Time (See Figure 4) t f 8 34 Q T. 4 nc (V DS = 48, I D = 2 Adc, Q.4 V GS = 5. ) Q Q 3. V SD..5.4 t rr 325 ns (I S = 2 Adc, V GS =, t a 24 di S /dt = A/µs) t b 2 Reverse Recovery Stored Charge Q RR 2.3 µc INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead.25 from package to center of die) Internal Source Inductance (Measured from the source lead.25 from package to source bond pad) L D 4.5 nh L S 7.5 nh () Pulse Test: Pulse Width 3 µs, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data

3 TYPICAL ELECTRICAL CHARACTERISTICS MTP2NEZL I D, DRAIN CURRENT (AMPS) V GS = V 8 V V 7 V 5 V 4 V I D, DRAIN CURRENT (AMPS) V DS V T J = 55 C C 25 C V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure. On Region Characteristics V GS, GATE TO SOURCE VOLTAGE (VOLTS) Figure 2. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE (OHMS) V GS = 5 V T J = C 25 C 55 C R DS(on), DRAIN TO SOURCE RESISTANCE (OHMS) V GS = V 5 V I D, DRAIN CURRENT (AMPS) I D, DRAIN CURRENT (AMPS) Figure 3. On Resistance versus Drain Current and Temperature Figure 4. On Resistance versus Drain Current and Gate Voltage R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED) V GS = 5 V I D = 2 A IDSS, LEAKAGE (na) V GS = V T J = 25 C C 25 C T J, JUNCTION TEMPERATURE ( C) Figure 5. On Resistance Variation with Temperature V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure. Drain To Source Leakage Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 3

4 MTP2NEZL POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals ( t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (I G(AV) ) can be made from a rudimentary analysis of the drive circuit so that t = Q/I G(AV) During the rise and fall time interval when switching a resistive load, V GS remains virtually constant at a level known as the plateau voltage, V SGP. Therefore, rise and fall times may be approximated by the following: t r = Q 2 x R G /(V GG V GSP ) t f = Q 2 x R G /V GSP where V GG = the gate drive voltage, which varies from zero to V GG R G = the gate drive resistance and Q 2 and V GSP are read from the gate charge curve. During the turn on and turn off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: t d(on) = R G C iss In [V GG /(V GG V GSP )] t d(off) = R G C iss In (V GG /V GSP ) The capacitance (C iss ) is read from the capacitance curve at a voltage corresponding to the off state condition when calculating t d(on) and is read at a voltage corresponding to the on state when calculating t d(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. 2 V DS = V C, CAPACITANCE (pf) C iss C oss C rss GATE TO SOURCE OR DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data

5 V GS, GATE TO SOURCE VOLTAGE (VOLTS) QT 5 5 V GS Q Q2 3 2 I D = 2 A Q3 V DS Q T, TOTAL CHARGE (nc) Figure 8. Gate To Source and Drain To Source Voltage versus Total Charge 2 V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) t, TIME (ns) V DD = 3 V I D = 2 A V GS = 5 V t r t f t d(off) t d(on) MTP2NEZL R G, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN TO SOURCE DIODE CHARACTERISTICS 2 V GS = V, SOURCE CURRENT (AMPS) IS V SD, SOURCE TO DRAIN VOLTAGE (VOLTS).2 Figure. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain to source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (T C ) of 25 C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN59, Transient Thermal Resistance General Data and Its Use. Switching between the off state and the on state may traverse any load line provided neither rated peak current (I DM ) nor rated voltage (V DSS ) is exceeded and the transition time (t r,t f ) do not exceed µs. In addition the total power averaged over a complete switching cycle must not exceed (T J(MAX) T C )/(R θjc ). A Power MOSFET designated E FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non linearly with an increase of peak current in avalanche and peak junction temperature. Although many E FETs can withstand the stress of drain to source avalanche at currents up to rated pulsed current (I DM ), the energy rating is specified at rated continuous current (I D ), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 2). Maximum energy at currents below rated continuous I D can safely be assumed to equal the values indicated. Motorola TMOS Power MOSFET Transistor Device Data 5

6 MTP2NEZL SAFE OPERATING AREA I D, DRAIN CURRENT (AMPS) V GS = 2 V SINGLE PULSE T C = 25 C ms ms dc µs R DS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT µs V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) T J, STARTING JUNCTION TEMPERATURE ( C) E AS, SINGLE PULSE DRAIN TO SOURCE AVALANCHE ENERGY (mj) I D = 2 A 5 Figure. Maximum Rated Forward Biased Safe Operating Area Figure 2. Maximum Avalanche Energy versus Starting Junction Temperature r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE. D = SINGLE PULSE P (pk) t, TIME (s) t t 2 DUTY CYCLE, D = t /t 2 R θjc (t) = r(t) R θjc D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T J(pk) T C = P (pk) R θjc (t)..e 5.E 4.E 3.E 2.E.E+.E+ Figure 3. Thermal Response di/dt I S t rr t a t b TIME t p.25 I S I S Figure 4. Diode Reverse Recovery Waveform Motorola TMOS Power MOSFET Transistor Device Data

7 PACKAGE DIMENSIONS MTP2NEZL H Q Z L V G B N D A K F T U S R J C T SEATING PLANE STYLE 5: PIN. GATE 2. DRAIN 3. SOURCE 4. DRAIN NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G H J K L N Q R S T U V.45.5 Z CASE 22A ISSUE Y Motorola TMOS Power MOSFET Transistor Device Data 7

8 MTP2NEZL Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE: Motorola Literature Distribution; P.O. Box 292; Phoenix, Arizona MFAX: RMFAX@ .sps.mot.com TOUCHTONE (2) INTERNET: NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi SPD JLDC, Toshikatsu Otsuki, F Seibu Butsuryu Center, Tatsumi Koto Ku, Tokyo 35, Japan HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 5 Ting Kok Road, Tai Po, N.T., Hong Kong CODELINE TO BE PLACED HERE Motorola TMOS Power MOSFET Transistor MTP2NEZL/D Device Data *MTP2NEZL/D*

Vdc Vpk Drain Current Continuous Drain Current 100 C Drain Current Single Pulse (t p 10 µs) Total Power Dissipation Derate above 25 C

Vdc Vpk Drain Current Continuous Drain Current 100 C Drain Current Single Pulse (t p 10 µs) Total Power Dissipation Derate above 25 C MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP4N8E/D Designer s Data Sheet TMOS E FET. Power Field Effect Transistor N Channel Enhancement Mode Silicon Gate This high voltage MOSFET uses