EEM411 DIGITAL ELECTRONICS

Transcription

1 GAZI UNIVERSITY FACULTY OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EEM411 DIGITAL ELECTRONICS LABORATORY MANUAL FALL

2 TABLE OF CONTENTS Page LABORATORY RULES...2 EXP# 1 - TRANSISTOR-TRANSISTOR LOGIC (TTL)...3 EXP # 2 - OTHER TTL GATES...10 EXP # 3 - SCHOTTKY TRANSISTOR-TRANSISTOR LOGIC (STTL)...14 EXP # 4 EMITTER-COUPLED LOGIC (ECL)...19 EXP # 5 NMOS Inverters...22 EXP # 6 NMOS GATES...28 EXP # 7 - CMOS...33 Laboratory Schedule Laboratory Laboratory 1 Laboratory 2 Laboratory 3 Laboratory 4 Laboratory 5 Laboratory 6 Laboratory 7 Homework 1 Deadline Project Deadline Final Exam Date 18 March 25 March 1 April 22 April 29 April 6 May 13 May 1 April 20 May 20 May EEM411 Digital Electronics 1

3 LABORATORY RULES Attendance There will be NO make-up experiment. Students who cannot attend an experiment get zero from the report and quiz of that experiment. Students who miss 2 or more experiment fail from the laboratory. There will be a pop-up quiz at the first 15 minutes of your laboratory session. If you come to class during a quiz, you can attend to that quiz with remaining time. Students who come after the end of quiz, cannot have the quiz and will not be accepted to the experiment. Experiment Reports Reports will be prepared personally via computer. Reports are delivered at the next experiment. Grade of delayed reports will be reduced by 15pts for each day. Cheated reports will be graded with 0pts Contents of the reports; Theory %10 Exp. Work %20 Results %45 Comment %25 During the experiment; Circuits will be simulated on PSpice at laboratory. Results of experiment must send via to adress given below at the end of each laboratory. Subject of Lab.No_StudentID_Name adress:kizilogluvolkan@gmail.com Degrees At the end of the term, your final laboratory degree will be calculated as follows; Final Lab. Degree: Quizes %15 Homeworks %10 Reports %35 Lab. Final Exam %40 EEM411 Digital Electronics 2

4 EXPERIMENT 1 - TRANSISTOR-TRANSISTOR LOGIC (TTL) In 1965, transistor-transistor logic (TTL) was introduced. As the name implies, the usage of diodes in DTL is replaced with transistors (BJTs) in TTL. The resulting TTL circuits provide increase fun-out, improved transient response, and a reduction in chip area required. TTL circuits are the first of the 54x00/74x00 series of BJT logic families. The 74x00 series are adequate for most commercial applications and operate over at temperature of 0 to 70 o C. The 54x00 series have the same logic circuit design as the 74x00 circuits but operate over the superior temperature range -55 to 125 o C and are primarily used for military applications. BASIC TTL INVERTER The basic TTL inverter is shown in Figure 1. The input and level-shifting diodes of the basic DTL inverter have been replaced with a single BJT Q1 at the input. The advantage of the input BJT over the diodes is two-fold. The BJT requires less silicon surface area than the two diodes and propagation delay time is improved by an order of magnitude. To determine the voltage transfer characteristic, we consider VIN to vary from low values through high values and determine the corresponding output voltage range. Figure 1 TTL The current IB,I is given by EEM411 Digital Electronics 3

5 Outputs are taken at the collectors of QO and with different input voltages the output changes its values. Voltage transfer characteristic is shown in Figure 2. Figure 2 TTL Transfer Function EEM411 Digital Electronics 4

6 STANDARD TTL NAND GATE Figure 3 displays the circuit diagram for the series 5400/7400 Standard TTL gate in a 2- input NAND arrangement. The stacking of two BJTs, a resistor, and a diode in the output branch is called a totem pole output. Figure 3 Standard TTL Function Figure 4 Standard TTL Transfer To determine the voltage transfer characteristic (VTC) of the standard TTL gate in Figure 4 consider the two inputs connected together with VINA=VINB= VIN. The resulting VTC is displayed in Figure 4 with all critical points labeled. TTL FAN-OUT As with DTL, the maximum fan-out for TTL is dependent on the output low state of the driver gate. The maximum fan-out is again determined by how much current the driving gate can sink from multiple load gates. Maximum fan-out is obtained from EEM411 Digital Electronics 5

7 LOW POWER TTL (LTTL) To decrease the power dissipated in TTL logic gates, the resistor magnitudes must be increased. With increased resistances, less current conducts in the gate and ICC x VCC product is decreased. Figure 5 shows the 54Lx00/74Lx00 low power TTL (LTTL) with increased resistances. EEM411 Digital Electronics 6

8 Figure 5 Low TTL HIGH SPEED TTL(HTTL) As mentioned in the previous section, a decrease in power dissipation is accompanied by a reduction in speed. This suggests that the transient response of TTL might be improved by decreasing resistance values and increasing the power dissipation. This is in fact the case and prompted the development of high speed TTL (HTTL). Figure 6 shows the 54Hx00/74Hx00 series high speed TTL. Figure 6 High (Speed) TTL EEM411 Digital Electronics 7

9 PRELIMINARY WORK How can you calculate operating frequency using Rise time and Fall time EXPERIMENTAL PROCEDURE Simulation1: Figure 7 shows a standard 54x00/74x00 TTL inverter. Setup the circuit and; 1) Plot Vout and Vin vs time 2) Plot voltage transfer characteristics (VTC) of output. 3) Plot the transient response of output. 4) Calculate the operating frequency 5) Calculate the fan out for standard TTL inverter. 6) Calculate Fan out experimentally. (Assume your transistor has maximum 100mA collector current) 5 VCC RB 4 k RC 1600 RCP 120 QP V1 = 5 Qi QS D1N4148 V2 = 0 Output TD = 0 TR = 2n V1 D1N4148 QO TF = 2n PW = 200n PER = 400n RD 1 k Figure 7 Standard TTL Inverter 0 Simulation2: EEM411 Digital Electronics 8

10 Change the Rb,Rc and Rcp values of Figure 7 for LTTL and; 1) Plot Vout and Vin vs time 2) Plot voltage transfer characteristics (VTC) of output. 3) Plot the transient response of output. 4) Calculate the operating frequency 5) Calculate the fan out for standard LTTL inverter. Rc=20kΩ / Rcp=500Ω / Rb=40kΩ / Rd=12k Ω Simulation3: Figure 8 shows a HTTL inverter. Setup the circuit and; 1) Plot Vout and Vin vs time 2) Plot voltage transfer characteristics (VTC) of output. 3) Plot the transient response of output. 4) Calculate the operating frequency 5) Calculate the fan out for standard HTTL inverter. D1N4148 Figure 8 HTTL EEM411 Digital Electronics 9

11 EXPERIMENT 2 - OTHER TTL GATES Throughout the TTL experiments, the inverter and multi-input NAND gates are used to demonstrate the design and analysis of TTL gates. In fact, TTL logic families can also realize the other basic logic functions AND, OR and NOR as well as AND-OR invert. TTL AND Gate Circuit Figure 9 shows the 5408/7408 standard TTL AND gate circuit and circuit symbol for this gate. Note that the input section consisting of Q1 and RB and the output section consisting Q0, DL,QP and RCP are identical to the experiment 1 TTL NAND gate The drive split section, however, contains some additional circuit components which are QS2, QSD, DS, RSD, RCS. These are enclose in the shaded block and provide a second level of inversion between the input and output. Thus, with two inversions the circuit realizes the logic AND function. Figure 9 TTL AND Gate EEM411 Digital Electronics 10

12 Output Low Voltage (VOL): With either or both inputs low, a large current flows into the base of Q1. Furthermore, for either input low, the collector current of Q1 essentially zero. The voltage at the base of QS2 is then; Hence, QS2 and therefore QSD are cut off for VIN low. With QS2 and QSD cut off, QO and QS are easily seen to be saturated along with DS conducting by following path 2 of figure 1.The output low voltage is therefore Input Low Voltage (VIL): To determine the input low voltage, note that Q1, RB, QS2, QSD, RSC, RSD collectively resemble the portion of the TTL NAND gate (first experiment) containing Q1,RB, QS, QO, RC and RD. Hence, the collector voltage of QSD will be high for any input low in a NAND-like fashion and the output will be low with QS and QO in saturation. As the input voltage increases, the collector current of QS2 increases, the base voltage of QS2 increases, and QS2 becomes forward active. Also, as the input voltage is increased further, the current through the diode DS decreases. However, the magnitude of the diverted current through QS2 is insufficient to take QS and QO out of saturation. Thus, the voltage at the collector of QS2 remains approximately fixed at As the input voltage is further increased VOUT begins to increase and VC,S2 begins to decrease. Input High Voltage (VOH): When VBS drops below VBE,O(FA)+VBE,S(FA), Q0 becomes cutoff and the output begins to go high. When QSD enters saturation, the voltage VB,S=VCE,SD(SAT) is definitely low enough to cut both QO and QS. The input voltage necessary to saturate QS2 and QSD is then the input high voltage, given by; EEM411 Digital Electronics 11

13 Output High Voltage (VOH): With all inputs high, Q1 becomes reverse active. QS2 and QSD are in saturation which can be verified by following dashed path 3 of figure 1. With QSD in saturation VB,S=VCE,SD(SAT) and thus QS and QO are cutoff. The output voltage is then found by following dashed path 4 of figure 1. Voltage Transfer Function: Figure 10 Voltage Transfer Function for TTL AND gate EEM411 Digital Electronics 12

14 EXPERIMENTAL PROCEDURE Simulation1: Figure 11 shows a standard TTL AND gate. Setup the circuit and ; 1) Plot Vout and VIN1,VIN2 vs time 2) Plot VC,SD and VIN1,VIN2 vs time 3) Plot voltage transfer characteristics (VTC) of output. 4) Plot the transient response of output. Figure 11 TTL AND Gate EEM411 Digital Electronics 13

15 EXPERIMENT 3- SCHOTTKY TRANSISTOR-TRANSISTOR LOGIC (STTL) In 1970, Schottky transistor-transistor logic was introduced. This logic family is obtained by replacing the BJTs (SBJTs). The primary advantage of using Schottky-clamped BJTs is their improved transient time. Since the Schottky-clamped BJTs cannot operate in saturation, the switching speed and associated time delays are considerable shortened. SCHOTTKY BARRIER DIODES A Schottky-barrier diode is made up of adjoining metal and N-type semiconductor region. The MN SBD differs from an ohmic contact in that a barrier to electron flow exists at the MN junction. As in case of a PN diode this barrier is reduced only by applying a forward voltage. For the MN diode, a forward voltage is positive on M relative to N. This polarity of voltage reduces the barrier to electron flow from N to M and depending upon the magnitude of the voltage may correspond to a large current from M to N. The circuit symbol for the MN SBD is shown in Figure 12.A typical value for a Silicon MN diode is VSBD(ON)=0.3 V Figure 12 Schottky Diode EEM411 Digital Electronics 14

16 SCHOTKKY-CLAMPED BJTs A serious problem that severely limits the switching speed of a BJT inverter is the amount of time required to remove the enormous stored charge from the base of a saturated BJT. Since the saturation mode of operation for a BJT is characterized by a forward biased base-collector voltage of VBC(SAT)=VBE(SAT)-VCE(SAT) = =0.6 the saturation region can be avoided by limiting the forward-biased base-collector voltage to values less than 0.6V. This is accomplished by replacing a SBD across the base and collector terminals of a BJT as in Figure 13. Figure 13 Schottky-clamped BJT On-Hard Mode: The mode of operation where the BJT is forward active and the Schotkky diode is conducting is referred to as the on-hard mode. This mode is similar to saturation with VBE increased to 0.8, except VBC is only forward biased to 0.3 V. Reverse Schotkky Mode: With the base-collector junction of a SBJT limited to a forward-bias of VBC(HARD)=VSBD(ON)=0.3V, an SBJT cannot operate in the reverse-active mode of operation. EEM411 Digital Electronics 15

17 SCHOTKKY CLAMPED TTL (STTL) The basic 54Sx00/74Sx00 STTL gate is displayed in Figure 14. This arrangement provides more source current to charge the load capacitance when the driver output is switched low to high, thus reducing the transition time. Figure 14 SCHOTKKY CLAMPED TTL Figure 15 STTL Inverter Voltage Transfer Characteristic When QP and QP2 are on, the collector emitter voltage of QP2 has a minimum value of VCE,P2(FA)=VBE,P2(FA)+VCE,P(HARD)>VCE(SAT) and QP2 therefore cannot saturate. Hence all of the BJTs have been replaced with SBJTs except the QP2 and the input clamp diode have been replaced with SBD. STTL FAN-OUT The fan-out is dependent on how much current the driver gate can sink from the load during the low output state of the driving gate or EEM411 Digital Electronics 16

18 For the low state input; For the low state output current; EXPERIMENTAL PROCEDURE MODEL for SBD and NPN Transistor: SBD: IS=7.3E-11 VJ=0.5V CJO=0.05PF EG=0.69 XTI=2.0 NPN Transistor: IS=1E-14 BF=49 VA=80 TF=0.45NS TR=5NS CCS=3PFD CJE=2.6PFD CJC=2PFD RB=13OHM RC=6.2OHM EEM411 Digital Electronics 17

19 Simulation1: Figure 16 shows a standard STTL inverter. Setup the circuit and; 1) Plot Vout and Vin vs time 2) Plot voltage transfer characteristics (VTC) of output. 3) Plot the transient response of output. 4) Calculate the operating frequency 5) Calculate the fan out for standard STTL inverter. 6) Compare STTL inverter with Standart TTL, HTTL and LTTL. Figure 16 Standard STTL inverter EEM411 Digital Electronics 18

20 EXPERIMENT 4- EMITTER-COUPLED LOGIC Emitter-Coupled Logic gets its name from a multi-transistor emitter-coupled configuration. The emitter-coupled configuration that is the basis of ECL is a current switch analogous difference amplifier. Output inverting BJTs are not used in ECL digital circuits. The BJTs in ECL circuits therefore avoid the saturation region of operation, operating only in forwardactive and cutoff regions. The design improvements in ECL over TTL subfamilies result in an improved fan-out and the fastest switching time of available digital circuits. Typical propagation delay times are on the order of 1ns, allowing for clock frequencies up to 1GHz. This improved performance is achieved at the expense of the highest power dissipation of all logic families, typically 25mW per gate. The current IRE is given by Outputs are taken at the collectors of QI and QR, giving both an inverting and noninverting output: and VINV =VC,I =VCC IC,I RCI VNINV =VC,R =VCC IC,RRCR The states of the inverting and non-inverting outputs are determined by whether the input voltage VIN is less than or greater than the reference voltage VBB. EEM411 Digital Electronics 19

21 Input Input State Inverting Output State VIN < VBB Low High Low VIN > VBB High Low High Non-Inverting Output State EXPERIMENTAL PROCEDURE Simulation1: Figure 17shows a ECL NOR/OR gate. Setup the circuit and; 1) Plot VOR and VIN1,VIN2 vs time 2) Plot VNOR and VIN1,VIN2 vs time 3) Plot voltage transfer characteristics of outputs(start:-1.5 End:0 Step:10m). 4) Plot the transient response of output. 5) Draw Truth table for each output Figure 17ECL NOR/OR Gate EEM411 Digital Electronics 20

22 Simulation2: Setup the circuit in Figure 18 and; 1) Plot F1 and VIN1,VIN2 vs time 2) Plot F2 and VIN1,VIN2 vs time 3) Plot F3 and VIN1,VIN2 vs time 4) Plot F4 and VIN1,VIN2 vs time 5) Draw Truth table for each output 6) Determine logical function for each output. Figure 18 Quad ECL Current switch Series Gated Decoding Tree EEM411 Digital Electronics 21

23 EXPERIMENT 5 -NMOS Inverters (Resistor Loaded, Saturated Enhancement Only Loaded, Linear Enhancement Only Loaded) In this laboratory, inverter characteristics are described in details for various MOSFET cases with different loads. Resistor Loaded NMOS Inverter Figure 19 Shows the NMOS inverter with resistive load, RL. The input to the inverter is at the gate of the N-channel output transistor NO and VIN = VGS. The output is at the drain and VOUT = VDS = VDD IRL RL. For VIN < Vt, NO is cut off and does not conduct drain current. Since the resistor current is equal to the drain current, with VIN Vt IRL = ID(OFF) = 0 and the output is VOUT = VDD. As the input is increased slightly above the threshold voltage NO begins to conduct. At this point only a small current flows and the drain voltage is lightly less than VDD. As long as VDS >= VGS Vt, NO is operating in the saturation region. With further increase of the input, a larger drain current conducts and the output voltage continues to fall. In summary, for a low input the output is high. Conversely for a high input the output is low. Figure 19 Resistor Loaded NMOS Inverter EEM411 Digital Electronics 22

24 Saturated Enhancement Only Loaded NMOS Inverter Figure 20 shows the NMOS inverter with an enhancement-only N-channel MOSFET as a load device. With the gate and drain of the load transistor NL connected, we have VDS,L =VGS,L >VGS,L VT,L and thus the load transistor NL operates in saturation only. The input to this inverter is at the gate of the output transistor NO and VIN = VGS,O. the output is at the drain of NO and VOUT = VDS,O = VDD VDS,L. For VIN < VT,O, transistor NO is cutoff and does not conduct drain current. As the input is increased above VT,O, transistor NO, and NL begin to conduct with equal drain currents. Since VDS,O >= VGS,O VT,O, transistor NO is operating in the saturation region of operation. Figure 20 Saturated Enhancement Only Loaded NMOS Inverter (a) Source-body connected load, (b) load with body-bias EEM411 Digital Electronics 23

25 Linear Enhancement Only Loaded NMOS Inverter The output high voltage of an enhancement-only loaded NMOS inverter can be raised to VDD by using a load that operates in the linear region. This is accomplished by applying a separate, larger voltage source to the gate of NL, as shown in Figure 21 (c) (d) Figure 21 Linear Enhancement Only Loaded NMOS Inverter:(a) Source-body connected load, (b) Load with body-bias, (c) Graphical determination Voltage transfer characteristic, (d) Voltage transfer characteristic obtained from curve intersections of (c) EEM411 Digital Electronics 24

26 EXPERIMENT PROCEDURE MODEL for NMOS: NMOS: VTO=1 KP=20U GAMMA=0.37 PHI=0.6 CBD=3.1E-15 CBS=3.1E-15 Simulation1 Figure 22 shows a Resistor Loaded NMOS Inverter. Setup the circuit and; 1) Plot VOUT and VIN vs time 2) Plot voltage transfer characteristics of output. 3) Plot the transient response of output 4) Show rise time, fall time and also calculate maximum frequency using risefall times. 5) Practically show transition voltages using VTC slope. Figure 22 Resistor Loaded NMOS Inverter EEM411 Digital Electronics 25

27 Simulation2 Figure 23 shows a Saturated Enhancement Only Loaded NMOS Inverter. Setup the circuit and; 1) Plot VOUT and VIN vs time 2) Plot voltage transfer characteristics of output. 3) Plot the transient response of output 4) Show rise time, fall time and also calculate maximum frequency using rise-fall times. 5) Practically show transition voltages using VTC slope. Figure 23 Saturated Enhancement Only Loaded NMOS Inverter EEM411 Digital Electronics 26

28 Simulation3 Figure 24 shows a Linear Enhancement Only Loaded NMOS Inverter. Setup the circuit and; 1) Plot VOUT and VIN vs time 2) Plot voltage transfer characteristics of output. 3) Plot the transient response of output 4) Show rise time, fall time and also calculate maximum frequency using rise-fall times. 5) Practically show transition voltages using VTC slope.. Figure 24 Linear Enhancement Only Loaded NMOS Inverter EEM411 Digital Electronics 27

29 EXPERIMENT 6 - NMOS Gates Each of more complex logic gates has a single load device that is between the logic gate output and VDD in the same fashion as the NMOS inverters. Furthermore, the single output transistor NO is replaced with multiple N- channels either in parallel (NOR) or series (NAND) or both (AOIs). The gate terminal of each non-load N- channel MOSFET serves as a separate logical gate input. Figure 25 NMOS NOR Gates Figure 26 NMOS NAND Gate Figure 27 AND - OR - invert gate Figure 28 Exclusive OR/NOR gate EXPERIMENTAL PROCEDURE MODEL for NMOS: EEM411 Digital Electronics 28

30 Mbreakn: VTO=1.3 KP=20U GAMMA=0.43 PHI=0.6 CBD=3.1E-15 CBS=3.1E-15 MbreaknD: VTO=-3.2 KP=20U GAMMA=0.43 PHI=0.6 CBD=3.1E-15 CBS=3.1E-15 Simulation1 Setup SPICE model of circuit shown in Figure 29 NMOS XNOR/XOR. Plot Voltage transient response of output. Draw Truth table for output. Figure 29 NMOS XNOR / XOR EEM411 Digital Electronics 29

31 Simulation2 Setup SPICE model of circuit shown in Figure 30 NMOS NOR. Plot Voltage transient response of output. Draw Truth table for output. Figure 30 NMOS NOR EEM411 Digital Electronics 30

32 Simulation3 Setup SPICE model of circuit shown in Figure 31 NMOS NAND. Plot Voltage transient response of output. Draw Truth table for output. Figure 31 NMOS NAND EEM411 Digital Electronics 31

33 Simulation4 Setup SPICE model of circuit shown in Figure 32 NMOS Schmitt Trigger. 1) Plot Voltage transient response of output. 2) Plot Voltage transfer characteristic. Figure 32 NMOS Schmitt Trigger EEM411 Digital Electronics 32

34 EXPERIMENT 7 - CMOS EXPERIMENTAL PROCEDURE MODEL for NMOS and PMOS: NMOS: VTO=1 KP=40U GAMMA=0.37 PHI=0.6 CBD=3.1E-15 CBS=3.1E-15 PMOS: VTO=-1 KP=16U GAMMA=0.4 PHI=0.6 CBD=3.1E-15 CBS=3.1E-15 Simulation 1 Setup SPICE model of circuit shown in Figure 33 : CMOS Invertor with Capacitive Load, 1) Plot Vout, Vin vs time 2) Plot source current(idd vs VIN), source power of output. 3) Plot voltage transfer characteristics of output. 4) Calculate rise time, fall time and maximum frequency for the circuits. 5) Why we used 1pF capacitor as a load? 6) Give the function of output. 7) What is the difference between power consumption of CMOS and other gates. 8) Assume that your computer has been made of 1M CMOS gate. And your computer running at full speed which NMOS gate below supported. Then calculate the required power for your computer. Assume your computer has been made of bipolar transistor. Then calculate required power. Is it applicable? Figure 33 : CMOS Invertor with Capacitive Load EEM411 Digital Electronics 33

35 Simulation 2 Setup SPICE model of circuit shown in Figure 34: Two input CMOS NOR gate, 1) Plot Vout, Vin vs time 2) Plot voltage transfer characteristics of output. 3) Calculate rise time, fall time and maximum frequency for the circuits. 4) Draw Truth table for output 5) Give the ouput function of output. Figure 34: Two input CMOS NOR gate EEM411 Digital Electronics 34

36 Simulation 3 Setup SPICE model of circuit shown in Figure 35: Four input CMOS AND-OR gate, 1) Plot Vout, Vin vs time 2) Plot voltage transfer characteristics of output. 3) Draw Truth table for output 4) Give the ouput function of output. Figure 35 : Four Input CMOS AND-OR gate EEM411 Digital Electronics 35

37 Simulation 4 Setup SPICE model of circuit shown in Figure 36: Four input CMOS XOR gate, 1) Plot Vout, Vin vs time 2) Draw Truth table for output 3) Give the ouput function of output. Figure 36: Two input CMOS XOR gate EEM411 Digital Electronics 36