ABSTRACT. ZHU, WENCONG. Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistors by using Focused Ion Beam. (Under the Dr. John Muth).

Transcription

1 ABSTRACT ZHU, WENCONG. Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistors by using Focused Ion Beam. (Under the Dr. John Muth). Compared with other transparent semiconductors, amorphous indium gallium zinc oxide (α-igzo) has both good uniformity and high electron mobility, which make it as a good candidate for displays or large-scale transparent circuit. The goal of this research is to fabricate α-igzo thin film transistor (TFT) with channel milled by focused ion beam (FIB). TFTs with different channel geometries can be achieved by applying different milling strategies, which facilitate modifying complex circuit. Technology Computer-Aided Design (TCAD) was also introduced to understand the effect of trapped charges on the device performance. The investigation of the trapped charge at IGZO/SiO2 interface was performed on the IGZO TFT on p-silicon substrate with thermally grown SiO2 as dielectric. The subgap density-of state model was used for the simulation, which includes conduction band-tail trap states and donor-like state in the subgap. The result shows that the de-trapping and donor-state ionization determine the interface trapped charge density at various gate biases. Simulation of IGZO TFT with FIB defined channel on the same substrate was also applied. The drain and source were connected intentionally during metal deposition and separated by FIB milling. Based on the simulation, the Ga ions in SiO2 introduced by the ion beam was drifted by gate bias and affects the saturation drain current. Both side channel and direct channel transparent IGZO TFTs were fabricated on the glass substrate with coated ITO. Higher ion energy (30 kev) was used to etch through the substrate between drain and source and form side channels at the corner of milled trench. Lower ion energy (16 kev) was applied to stop the milling inside IGZO thin film and direct channel between drain and source was created. Annealing after FIB milling removed the residual Ga

2 ions and the devices show switch feature. Direct channel shows higher saturation drain current (~10-6 A) compared with side channel (~10-7 A) because of its shorter channel length and wider width, however, it also exhibit higher gate leakage current (>10-7 A) than side channel (<10-7 A) due to larger Ga ion implantation and diffusion region in SiO2 after annealing. Hysteresis window increase and positive VON shift were also observed due to the interface trap density increase and carrier density suppression both by Ga ions. Laser interference lithography was applied to define the IGZO active region, which gives more flexibility on TFT channel dimension and circuit modification. He-Cd laser with 325 nm wavelength was used to define 2D array of IGZO islands with period of 2.5 μm. Logic gate array was designed and fabricated by combining this 2D array of IGZO islands and FIB direct channel milling. After annealing, device shows on-off feature, but high temperature (400 C) release more free carrier and results in negative shift of VON. The row selection voltage was also introduced in the design of logic gate array to act as switch of input signals to each row separately. However, due to the long input signal sweeping time, the leakage current cannot be overlooked. The idea can be verified by AC or short pulse input signal.

3 Copyright 2015 Wencong Zhu All Rights Reserved

4 Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistor by using Focused Ion Beam by Wencong Zhu A dissertation submitted to the Graduate Faculty of North Carolina State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy Electrical Engineering Raleigh, North Carolina 2015 APPROVED BY: Dr. John Muth Committee Chair Dr.Veena Misra Dr. Robert Kolbas Dr. David Aspnes

5 DEDICATION 天生我材必有用 Everyone was born for a reason ii

6 BIOGRAPHY Wencong Zhu was born in Jinan, the capital city of Shandong Province, east China. With the purpose of seeing different world and receiving better education, he went to the first university of modern China, Tianjin University (Peiyang University) to pursue his Bachelor s degree. After graduation, the thirst for knowledge and technology drove him to continue the graduate study in U.S, at Electrical and Computer Engineering Department at North Carolina State University in Wencong joined Dr. Robert Kolbas s group in 2010 with the research on AlGaAs quantum well and received his Master s degree in Electrical Engineering in spring After deciding pursuing Ph.D. degree, he became the member of Dr. John Muth s group with the study focusing on AlGaAs LED and IGZO TFT. He graduated from North Carolina State University with his Ph.D. degree in Electrical Engineering in summer iii

7 ACKNOWLEDGMENTS Obtaining the Ph.D. degree was my biggest dream until my current life, and I want thank everyone that helped me realizing this dream during the past six years at North Carolina State University. I would like to thank Dr. Muth, who is my most important academic advisor. He has so wide range of knowledge and always inspired me when I came to him. He is also a generous person, and always willing to share ideas, facilities and resources with other people. I cannot realize my dream without his guidance. I want to thank Dr. Kolbas, who is my first graduate advisor. He is such a nice professor and respected by everyone. He can explain a complicated theory by an easily understanding way and is always willing to discuss and communicate with students. Everyone loves him after taking his classes. I would like to thank Dr. Misra. She is an expert in semiconductors and gave me a lot of very useful suggestions on my research. Besides, without the ALD tool and characterization facilities in her lab, this work would be mission impossible. I want to thank Dr. Aspnes for being my committee member. He is expert in physics, especially in the field of my research, thus his advice means a lot to my research. Discussions with him always give me a deeper insight into my research. I want to express my thanks to Dr. Escuti, and Dr. Komanduri. Dr. Escuti is a brilliant professor in Optics. This work cannot be done without using the optical facilities in his lab. D. Ravi helped me so much for the training on interference lithography and he was always there when I had trouble. iv

8 Joe provided the most important help on the training of every facility I used in cleanroom. He helped me out every time I was in trouble, especially during the last crazy busy months of my research. I will miss the time we work together. I would like to thank all the former and current members in MRC 112. They made my graduate study more interesting and my life more colorful. They are: Haojun Luo, Yan Wang, Yi Lou, Hongguo Zhang, Yifan Wang, David Luo, Xiang Ji, Jong Boem Park, Kanu, Leandra, Abhishek, Benjamin, Sushmit, I want to give special thanks to Haojun for his guidance on IGZO TFT fabrication, Yan for his help in both North Carolina and California, and Leandra for her training on laser interference lithography and PLD. At last, I want to express my deepest thank to my parents, especially my Mother. She is the best teacher I have ever seen, and set the role of mine. She gave me the best support in my toughest period of research. I want to thank my girlfriend Wei Zhang, who is my soul mate and bring me sunshine every day. v

9 TABLE OF CONTENTS LIST OF TABLES x LIST OF FIGURES xi CHAPTER 1 INTRODUCTION Overview Research Objective and Dissertation Organization 3 CHAPTER 2 LITERATURE REVIEW AND BACKGROUND Thin Film Transistor Background and History Device Structure Basic Device Operation Electronic Structure of Amorphous Oxide Semiconductor (AOS) Indium Gallium Zinc Oxide (IGZO) Modeling and Simulation of α-igzo TFT Fundamentals of IGZO TFT Contact Electrode Gate Dielectric Materials Device Stability Integrated Circuit Based on IGZO Laser Interference Lithography Basic Theory Two-Beam Interference Arrangements Two Degrees-of-Freedom Lloyd-Mirror Interferometer Multi-Beam Interference Lithography for Nano-Electronics 40 CHAPTER 3 TOOLS FOR SIMULATION, EXPERIMENT AND DEVICE CHARACTERIZATION TCAD Simulation and Modeling of α-igzo TFT TCAD Introduction Device Simulation Flow Pulsed Laser Deposition Plasma Enhanced Chemical Vapor Deposition Electron Beam Evaporation Thin Film Patterning Photolithography 53 vi

10 3.5.2 Lift-Off Process Etch Process Focused Ion Beam Experiment Setup of Laser Interference Lithography Device Fabrication Electrical Characterization of Thin Film Transistors Thin Film Transistor Operation Modes DC Current-Voltage Measurement-Output Characteristics DC Current-Voltage Measurement-Transfer Characteristics 63 CHAPTER 4 MODELING AND SIMULATION OF IGZO TFT Sample Preparation Simulation Model for α-igzo Simulation for α-igzo TFTs with Long Channel Trapped Charge Density Extracted from Output Characteristics of α-igzo TFTs with Long Channel Transfer Characteristics Simulation Result of α-igzo TFTs with Long Channel Simulation of α-igzo TFTs with Short Channel Milled by Focused Ion Beam (FIB) Conclusions 86 CHAPTER 5 SHORT CHANNEL α-igzo THIN FILM TRANSISTOR FABRICATED BY FOCUSED ION BEAM Focused Ion Beam (FIB) milling FIB Introduction The Objective of Using FIB Multi-layer Thin Film Milled by FIB Device Modification by FIB Milling Short Two-Sides-Channel α-igzo TFTs Milled by FIB Right After FIB Milling Annealing in Air At 200 ºC for 10 min Annealing in Air At 250 ºC for 10 min Annealing in Air At 300 ºC for 10 min Short One-Side-Channel α-igzo TFTs Milled by FIB Right After FIB milling Annealing in Air At 200 ºC for 10 min Annealing in Air At 250 ºC for 10 min 107 vii

11 5.3.4 Annealing in Air At 300 ºC for 10 min Discussion on Side Channel TFTs Milled by FIB Effect of Residual Ions by FIB milling Effect of Side Channel Length on TFTs with Side Channel Milled by FIB Compare Between One-Side Channel and Two-Side Channel TFTs Milled by FIB Short Direct-Channel α-igzo TFTs Milled by FIB Right After Milling After Annealing in Air At 200 ºC for 30 min After Annealing in Air At 250 ºC for 30 min After Annealing in Air At 300 ºC for 30 min Discussion Effect of Channel Dimension on Drain Current and Leakage Current Conclusions 131 CHAPTER 6 SHORT CHANNEL THIN FILM TRANSISTOR WITH TWO DIMENSIONAL ARRAYS OF α-igzo ISLANDS PATTERNED BY LASER INTERFERENCE LITHOGRAPHY Laser Interference Lithography Device Fabrication Layout Design of Logic Arrays Short Direct-Channel TFTs with Laser Interference Lithography Patterned IGZO Active Layer and Milled by FIB Right After Milling After Annealing in O 2 At 250 C for 20 min & At 300 C for 20min After Annealing in O 2 At 350 C for 20 min & 50 min After Annealing in O 2 At 400 C for 10 min Compare of Transfer Characteristics at Different Vr Conclusions 148 CHAPTER 7 CONCLUSIONS AND FUTURE WORKS Conclusions Suggestions for Future Work Different Dielectric Material with Better Quality Further Investigation on the Material Improvement on the Profile of IGZO Islands Better Control of FIB Milling 153 viii

12 7.2.5 Ultra Short Channel by Using Laser Interference Lithography and FIB milling 155 REFERENCES 156 ix

13 LIST OF TABLES Table 1.1. Optional structures that can be fabricated by using FIB milling. 6 Table 2.1. Comparison of several materials used in displays [29]. 19 x

14 LIST OF FIGURES FIG.1.1. Schematic of different milling strategies to modify the effective width of TFTs with IGZO islands patterned by laser interference lithography 7 FIG Schematics of some of the most conventional TFT structures, according to the position of the gate electrode and to the distribution of electrodes relatively to the semiconductor [22] 12 FIG The TFT structure and energy band diagram as viewed through the gate: (a) the cross-section structure of TFT, (b) at equilibrium, VGS=0, (c) accumulation mode, VGS > 0, (d) depletion mode, VGS < 0 14 FIG Schematic electronic structure of silicon and ionic oxide semiconductors. (a-c) Bandgap formation mechanisms in (a) covalent and (b,c) ionic semiconductors. (d-g) Carrier transport paths in (d) c-si, (e) α-si, (f) crystalline oxide and (g) amorphous oxide [23] 17 FIG (a) Amorphous formation and (b) electron transport properties of In2O3-Ga2O3- ZnO thin films. The values in (b) denote the electron Hall mobility (cm 2 /V s) with density (10 18 cm -3 ) in parentheses [28] 18 FIG (a) (Color) Structure of the InGaZnO4 crystal. The brown, blue and red balls represent In, Zn/Ga and O atoms, respectively. (b) Partial density-of-states (DOS) curves for InGaZnO4 crystal structures. The top of the valence band is located at zero energy and total DOS is also shown in each figure as reference. (After Orita et al., Ref [31]) 20 FIG (a) Hall mobilities of InGaO3(ZnO)m as function of electron density.c-igzo1 and c-igzo5 represent crystalline phases with m = 1 and 5, respectively. HQ and LQ denote high-quality and low-quality, respectively. (b) Potential distribution above CBM analyzed based on percolation transport model [33]. (c) Illustration to explain the percolation conduction model [34] 21 FIG (a) Proposed DOS model for α-igzo. 2. EC and EV are conduction and valence band edge energies, respectively. Solid curves within the bandgap represent the exponentially distributed band-tail states (gcba, gvbd), while the dash curve near the conduction band edge represents the Gaussian-distributed donorlike OV states (ggd). (b) and (c) Transfer characteristics (W/L=180/30 μ. ( Both experimental (circle) and simulation data (solid line: Schottky contact; +: Ohmic contact) are shown. Extracted threshold voltage (Vth), field-effect mobility (μeff), and subthreshold swing (S) are also indicated. Inset of (c): the 2D TFT structure used in simulation 23 xi

15 FIG (a) VTH and on/off ratio as a function of semiconductor thickness for different ND. Band profile of TFTs with (b) d =150 nm and (c) d = 200nm. The QFL is close to the conduction band edge when high negative voltage is applied to gate electrode for d = 200nm. 25 FIG (a) Typical response to monochromatic light of transfer characteristic of annealed α-igzo TFT. The photon flux was fixed at ~ photons (cm -2 s -1 ). The blue dashed lines correspond to illumination above the band gap (>3.1 ev) and the black solid lines correspond to subgap illumination. (b) Model to explain NBL instability. 28 FIG Temperature dependence of transfer characteristics (VDS=10V, L/W = 10/100 µ): (a) ascending sequence and (b) descending sequence. 29 FIG Temperature dependence of transfer characteristics (VDS=10V, L/W = 10/100 µ): (a) ascending sequence and (b) descending sequence. 31 FIG Schematic diagram and voltage transfer curve of the inverter with a depletion load (a) and enhancement load (b) [69]. 32 FIG Optical microscopic image of dual-gate α-igzo TFT [45] (a) and NAND, NOR gate using separate devices (b) [71]. 33 FIG (a) Two-beam interference forms s standing wave. (b) A SEM image of 1D interference pattern having a 1 μ periodicity recorded in the negative photoresist SU FIG Two commonly used two-beam IL setups. (a) A Lioyd s mirror configuration, (b) A two-beam configuration created by a beam splitter. The dotted triangle represents the prism used in liquid immersion lithography [99]. 37 FIG (a) A simulation contour map of an IL pattern formed by a double exposure first in the x-direction and then in the y-direction. (b) A SEM image of a hexagonal structure created by double exposure IL where the substrate was rotated 60 about its normal between exposures. 39 FIG Schematic of Lloyd-mirror interferometer with 2-DOF configuration, the angles x and y are varied independently. 40 FIG (a) Scanning electron microscope image of combining MBIL and photolithography techniques. Two-beam interference lithography is used to define 45nm grid lines and higher spatial frequency modulating pattern was defined by photo-lithography (Copyright 2004, Reprinted with permission of Cambridge University Press [108]). (b) A complex composite pattern is created by two exposures and modulated by photo-lithography (edited with permission from [107]). 41 xii

16 FIG Typical tool flow with device simulation using Sentaurus Device [112]. 43 FIG Schematic of the pulses laser deposition system in NCSU. 48 FIG (a) Laser interference lithography setups for p polarized light. (b) Demonstration of power adjustment by using paper. 59 FIG Process flow of IGZO TFT device fabrication. 61 FIG (a) ELR method and (b) GMLE method implemented on the ID-Vg characteristics of the same device measured at VDS = 10 mv. 65 FIG (Color online) Proposed DOS model for α-igzo. 4. EC and EV are conduction and valence band edge energies, respectively. Solid curves within the bandgap represent the exponentially distributed band-tail states (gcba), while the dash curve near the conduction band edge represents the Gaussian-distributed donorlike OV states (ggd). 74 FIG (a) Cross-section of the α-igzo TFT structure for simulation and (b) output characteristics (W/L = 100/20 µm). Both experimental (triangle) and simulation data (solid line) are shown. 75 FIG (a) Trapped charge density at IGZO/SiO2 interface and (b) constant mobility as a function of gate bias voltage, extracted from the simulated output characteristics shown in Fig. 3(b). 76 FIG (a) α-igzo TFT transfer characteristics (W/L = 100/20 µm). Both experimental (circle) and simulation data (solid line) are shown. (b) Trapped charge density at interface as a function of gate voltage for both forward and backward bias sweeping. Arrows indicate the sweeping directions. 78 FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=-4V at forward gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. 79 FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=20V at forward gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. 80 FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=15V at reverse gate bias sweeping. xiii

17 For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. 80 FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=2V at reverse gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. 81 FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=0V at reverse gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. 81 FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=-0.5V at reverse gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. 82 FIG (a) Output characteristics of short channel α-igzo TFT by FIB milling, both experimental (triangle) and simulation data (solid line) are shown. (b) The transport of Ga + induced mobile hole at positive gate bias. 85 FIG (a) Demonstration of hole transport in SiO2. (b) The location of transvers plane with equivalent positive charge distribution as a function of gate bias. 0 µm and 0.1 µm refer to the SiO2/substrate interface and SiO2/IGZO interface separately. 86 FIG (a) FEI Quanta 3D FEG dual beam system from Analytical Instrumentation Facility (AIF) of NCSU (b) Configuration of dual-beam column for ion milling [144]. 90 FIG (a) Schematic diagram illustrating some of the possible ion beam-material interactions [122]. (b) SEM images of the end-edge view of a single pixel width line scan and the trench cross-section profile fitting with a Gaussian function [145]. 90 FIG Devices with different channel dimensions: (a) and (b) shows channels with different length, and (c) presents channel with thinner thickness. 92 xiv

18 FIG The cross-section view of etched trench by FIB with ion beam energy and current of 16keV, 11pA (a) and 30keV, 30pA (b). 93 FIG (a) Plain view of the milled trench with different parameter z depth. From left to right: z=180nm, 100nm, 150nm, 120nm. The cross-section views are shown in right as (b) for z=180nm, (c) for z=100nm, (d) for z=150nm and (e) for z=120nm. The ion beam energy and current are 30keV and 10pA. 94 FIG The cross-section view of the TFT structure before modification (a) and after modification by FIB (b). 96 FIG (a) Cross-section view of deep trench milled by FIB for side channel TFTs. (b) and (c) demonstrate the current flow for two-sides channel TFTs and one-side channel TFTs separately. The void is formed because of the joint of deposited Pt on upper side wall, which stop the Pt deposition on lower side wall and the bottom of the trench. 97 FIG (a) Illustration of current flow when the device is in on state, Vgs > VT, Vds > 0,(b) Transfer characteristic (Vds = 0.1V and 1V) of α-igzo two-side channel TFT with 4um wide metal line and 100nm wide trench milled by FIB. 98 FIG Illustration of the residual Ga ions diffusion before annealing (Left) and after annealing (Right). 100 FIG (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α- IGZO two-side channel TFT with 4um wide metal line and 100nm wide trench milled by FIB and annealing at 200 ºC for 10 min. 101 FIG (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α- IGZO two-side channel TFT with 4um wide metal line and 100nm wide trench milled by FIB and annealing at 250 ºC for another 10 min. 103 FIG (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α- IGZO two-side channeltft with 4um wide metal line and 100nm wide trench milled by FIB and annealing at 300 ºC for another 10 min. 104 FIG (a) Illustration of current flow when the device is in on state, VGS > VT, VGS > 0,(b) Transfer characteristic (Vds = 0.1V and 1V) of α-igzo one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB. 105 FIG (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α- IGZO one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB and annealing at 200 ºC for another 10 min. 107 xv

19 FIG (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α- IGZO one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB and annealing at 250 ºC for another 10 min. 108 FIG (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α- IGZO one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB and annealing at 300 ºC for another 10 min. 110 FIG (a) Schematic of the FIB ion beam with zero incident angles (black solid) and non-zero incident angle (red dashed) to the sample stage. (b) shows the crosssection view of milled trench when the ion beam is tilted to right (top) and tilted to left (bottom). 112 FIG Demonstration of residual Ga ions distribution depends on the ion beam direction. 113 FIG The transfer characterization of two-side channel TFTs milled by FIB without annealing when the main current occur between drain-source (a), gate-drain (b), and gate-source (c). 114 FIG Illustration of current flow of one-side TFTs mill by FIB with excess trench length of (a) 298.4nm and (b) 708.3nm. 115 FIG Compare of the one-side channel TFTs with different effective channel length, after annealing at 250 ºC in air for 10 min. 116 FIG Compare between one-side channel and two-side channel TFTs, after annealing at 250 ºC in air for 10 min. 117 FIG (a) Shows the plain view of milled trenches with different milling depth (z parameter). The cross-section view are shown also shown in (b) for z=85nm, (c) for z=90nm and (d) for z=95nm. 119 FIG Schematic (a), SEM plain view (b) of current flow and transfer characteristic (VDS = 0.1V and 1V) of a direct-channel IGZO TFT (W/L = 4μm/200nm) right after FIB milling. 120 FIG (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of a direct channel IGZO TFT (W/L = 4μm/200nm) after annealing in air at 200 ºC for 30 min. 122 FIG (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of a direct channel IGZO TFT (W/L = 4μm/200nm) after annealing in air at 250 ºC for 30 min. 123 xvi

20 FIG (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of a direct channel IGZO TFT (W/L = 4μm/200nm) after annealing in air at 300 ºC for 30 min. 124 FIG Compare of gate leakage current for direct-channel TFTs and side-channel TFTs. (a) The schematic of cross-section view of side-channel TFT (top) and direct channel TFT (bottom) after FIB milling, (b) the transfer characteristics for devices at VDS = 0.1V and 1V without annealing. 126 FIG Transfer characteristics for direct-channel TFTs (W/L = 4μm/200nm) with thin IGZO (a) and thick IGZO (b) at VDS = 1V, after FIB milling and annealing in air at 300 ºC for 30 min. 126 FIG Simulation result of electron density distribution of IGZO TFTs. The IGZO carrier density is cm -3, VDS = 3V and VGS = 9V. 128 FIG Compare of transfer characteristics for direct channel TFT (black) and one-side channel TFT (red). The direct channel device has channel thickness of 50 nm and W/L = 4um/200nm, the one-side channel device has channel thickness of 40 nm with W/L = 100nm/600nm. 129 FIG Compare of gate leakage current for one side channel TFT (black) and direct channel TFT (red) without annealing (a) and after 300 C annealing in air for 30 min. 131 FIG Schematic of Lloyd-mirror interferometer setup. Blue lines are the light from the laser and purple lines represent the reflected light from the mirror. 134 FIG Images of 2D patterned photoresist arrays under optical microscope (a) and AFM (b). 136 FIG Images of 2D patterned IGZO arrays under optical microscope (a) and AFM (b). 137 FIG Image of color pattern after IGZO wet etching and electron beam evaporation of Titanium. 137 FIG (a) Full layout of logic gate array mask design, including ITO (red), dielectric (yellow) and contact metal (blue). Bottom: (b) layout of inverter (c) layout of NAND (d) layout of NOR. 138 FIG (a) Equivalent circuit schematic of inverter gate pixel and the corresponding SEM picture (b). 140 xvii

21 FIG (a) SEM image of the function TFT of the inverter gate pixel in the array after FIB milling. (b) The cross-section view of the milled trench. 141 FIG Transfer characteristics of the function TFT of inverter gate pixel in the logic gate array at various row selection voltages Vr. 142 FIG Transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after a annealing in O2 at 250 C for 20 min (a) and annealing in O2 at 300 C for 20min (b). 143 FIG SEM image of the intersection of input line and row selection line. 144 FIG Transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after a annealing in O2 at 350 C for 20 min (a) and for 50min (b). 145 FIG Transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after a annealing in O2 at 400 C for 10 min. 146 FIG Transfer characteristics of drain current (a) and gate leakage current (b) at vary row selection voltage Vr. 147 FIG Schematic of isotropic wet etching profile for IGZO islands with larger size (top) and smaller size (bottom). 153 FIG (a) The FIB milling stops in the metal layer. (b) The remaining metal is removed by selective etch. 154 xviii

22 1.1 Overview CHAPTER 1 INTRODUCTION Transparent electronics is an emerging science and technology field focused on producing invisible electronics circuitry and opto-electronics devices. For example, an automobile windshield could transmits visual information to the driver, such as GPS navigation, or act as the second screen of mobile device. Or imagine a glass including a transparent display displays image or video eliminating a TV or projector. Two primary technologies are necessary to make transparent electronics and they are transparent conductive oxides (TCOs) and thin-film transistors (TFTs). TCOs must include two physical properties high optical transparency and high electrical conductivity. The most common TCOs are indium oxide In2O3, tin oxide SnO2, and the alloy indium tin oxide. They are usually used as electrodes and other passive electrical applications. The thin-film transistor (TFT) is another technology underlying transparent electronics, since it is the bridge between passive electrical and active electronic applications. The first ZnO-based TFT was announce in 1968 (Boesen and Jacobs) and more significant results were published around However, as ZnO exhibit high carrier density and low characteristic uniformity, people began to find substitutes. Hosono et al. [1, 2] predicted that amorphous oxides composed of heavy metal cations with an electronic configuration (n-1) d 10 ns 0 (n ( 4) are promising candidate for semiconductors. These ns orbitals have larger radii, so that there is a large overlap between the adjacent orbitals, which leads to insensitiveness to the distorted metal-oxygen-metal chemical bonds. Based on above mentioned criteria, α-igzo were successfully fabricated. High mobility of 7 cm 2 /V s and high on/off ratio of more than five orders of magnitude were achieved even at room 1

23 temperature process. Ooctahedrical bonding of the indium leads to high conductivity. Zink provides chemical stability and incorporating Ga ions is crucial in α-igzo for suppressing excessive carrier generation via oxygen vacancy. The large radius of the Ga also help the films to be amorphous rather than poly crystalline. The appearance of α-igzo also created significant worldwide interest in high-end LCD and AMOLED technology, both in industry and academia, because of its potential for high mobility, excellent uniformity in the device parameters, and good scalability to a large substrate size. Amorphous silicon (α-si) TFTs, which are widely used a switching device for displays, have the advantages of uniformity and low fabrication cost. Their lower mobility (<1 cm 2 /V s), however, may be not sufficient to drive large-are AMOLED displays. The magnitude of electron mobility of α-igzo is one or two orders higher (>10 cm 2 /V s) than α-si. Besides, the good transparency to visible light makes α-igzo more suitable in display applications, thus it has been wildly used in next generation displays. Transparent electronic device formed on flexible substrate is another emerging technology where silicon-based electronics cannot provide a solution for large area applications. Examples of active flexible applications include paper displays and wearable computers. So far, mainly flexible devices based on hydrogenated amorphous silicon (α- Si:H) and organic semiconductors have been investigated. However, the performance of these devices has been insufficient. Fabricating high-performance devices is challenging owing to trade-off between processing temperature and device performance. However, α- IGZO can be processed at room temperature or below 200 C and the lower process temperature enable new approaches on a wider variety of substrates. TFTs fabricated on 2

24 polyethylene terephthalate sheets exhibit saturation mobility of 6-9 cm 2 /V s, and device characteristics are stable during repetitive bending of the TFT sheet [3]. In addition to the application in display and flexible electronic devices, other application for oxide TFTs have also been demonstrated. Some oxide semiconductors are sensitive to specific gases, light or humidity, which make them suitable for sensors for multiple applications [4, 5]. TOSs based TFTs have also been applied in solar cell [6], three dimensional integrated circuits and memory elements [7, 8]. 1.2 Research Objective and Dissertation Organization Though the transparent amorphous oxide semiconductor (AOS) have attracted attention as an active layer for next generation TFTs, a strong understanding of AOS physics, material and device processing issues, and especially the stability and reliability of AOS TFTs is needs before any applications can be commercialized. Understanding the mechanism of bias-induced threshold voltage shift is important to make α-igzo based AOS TFTs more reliable and affordable. However, very limited work has been reported on how the trapped charge density changes with varying bias voltage and subgap density-ofstates (DOSs). This dissertation combines the model of subgap density-of-states and interface or bulk trapped charge density to simulate the electrical characteristics of both long channel and short channel α-igzo. This is provided to gain better understanding of the device stability. The second objective of this dissertation is to fabricate submicron α-igzo based TFTs using a new method, focused ion beam (FIB) milling. This is a quick, mask free approach that can be used to fabricate simple circuits. Proper milling strategies will be explored to create TFTs with desired channel dimensions. 3

25 One challenge in investigating small devices is to make small features. Electron beam is very time intensive lithography. For small samples, stepper is not suitable. Thus the third goal is to process the α-igzo active layer for TFTs by using laser interference lithography to define the two dimensional active layer patterns for logic gate arrays. Patterning of the active layer is critical for fabricating short channel TFTs and compared with photolithography, laser interference lithography is potentially inexpensive. The structure of this thesis is organized by the following. Chapter 2 gives the brief review of literature related to amorphous oxide semiconductors, including development history of AOSs based TFTs, physical properties of α-igzo and current AOS based devices and circuits. Description of thin film transistor device physics and laser interference lithography will be discussed to provide background knowledge for both simulation and experimental work presented in this dissertation. Chapter 3 provides the description of technology computer aided design (TCAD) tools for simulation and experimental facilities used in process flow to make AOS TFTs, including thin film deposition, laser interference lithography and photolithography, reactive ion etching (RIE), focused ion beam, followed by a discussion on the electrical TFT characterization methodology and figures-of-merit. Chapter 4 discuss the simulation results for both long channel α-igzo TFTs and short channel device milled by focused ion beam (FIB) based on subgap density-of-states model, and compare it with the experimental results. A changing trend of trapped charge in both dielectric and at IGZO/SiO2 interface along with gate bias was extracted from the fitting of simulation to experiment result. It also simulates the moving mechanism of implanted ions from FIB milling. 4

26 Chapter 5 introduces the FIB technology used to modify device structure. It also presents the electrical characterizations of side-channel TFTs milled by FIB at different annealing temperature. Devices with different channel widths are demonstrated. The effects of beam quality and annealing temperature on the leakage current are also discussed. FIB milling provides a more flexible method to define TFTs with different structures. Table 1.1 shows the optional TFT structure that can be fabricated by using FIB milling. Structure (a) and (b) show that only side channel exist if IGZO pattern is wider than metal line and the FIB milling removes all the IGZO between drain and source. Structure (c) and (d) demonstrate that if IGZO pattern is narrower than metal line but FIB milling stops inside IGZO, only direct channel exist, and the channel thickness depends on the milling time. Structure (e) and (f) show that if IGZO is wider than metal line on one side and FIB milling stops in IGZO, both direct channel and one-side channel are created. Structure (g) and (h) presents that if IGZO is wider than metal line on both sides and FIB milling stops in IGZO, both direct channel and two-sides channel are created. In this work, structure (a) (b) (c) and (d) are fabricated and discussed. Chapter 6 presents the laser interference lithography which explores ways to replaces the conventional photolithography or electron beam photolithography to define the α-igzo active pattern as a step towards making a circuit using the focused ion beam method. The process flow of the inverter gate pixel is presented with device electrical characteristics demonstrated. 5

27 Table 1.1. Optional structures that can be fabricated by using FIB milling The 2D array of IGZO islands patterned by laser interference lithography gives more flexibility to define the channel width by FIB milling. Strategies of channel milling are demonstrated in Figure 1.1. The metal covers five IGZO islands in vertical direction, if the milling path is along the dashed line as shown in Figure 1.1 (a) and (b), only three IGZO islands are included to form the channel. Assume the width of one IGZO island is W, the effective overall channel width can be 1W,2W,3W,4W and 5W based on the milling path, which provide high diversity in W/L ratio for TFTs. The second strategy are demonstrated in Figure 1.1 (c) and (d). The original milling cut five IGZO islands in a column as shown by dashed line, followed by a square milling which remove the center island and its surround metal, and the result channel length is 4W. This is good method for the post modification. 6

28 Chapter 7 summarizes the major achievements presented in this dissertation and discusses the suggestions for future work. FIG.1.1. Schematic of different milling strategies to modify the effective width of TFTs with IGZO islands patterned by laser interference lithography. 7

29 CHAPTER 2 LITERATURE REVIEW AND BACKGROUND This chapter reviews the fundamentals of α-igzo devices. Basic device structure and operation of TFTs are introduced, followed by a discussion of amorphous oxide semiconductors. The potential for α-igzo TFTs integrated circuit is also explored. Since device stability is important, the subgap density-of-states model is discussed. The final part of this chapter presents the basic of laser interference lithography, which is used to facilitate the patterning of α-igzo active layer without conventional photolithography or electron beam lithography. 2.1 Thin Film Transistor Background and History The TFT was invented in 1925 and patented in 1930 by J.E. Lilienfeld [9-11] and O. Heil [12]. However, the first TFT was produced after one more decade by Weimer at the RCA Laboratories in 1962 [13-15] when semiconductor and the vacuum techniques necessary for the thin film deposition were developed. These initial n-type TFTs used a top-gate staggered structure with microcrystalline CdS deposited by evaporation as the channel layer. Thermally evaporated SiO was used as the gate dielectric and gold was applied for gate electrode and drain and source contacts. With the channel length of 5 to 50 μ was used as the gate field-effect mobilities on the order of 1.1 cm 2 /Vs and drain current on/off ratio of The early TFT were also made of CdSe with high field effect mobility, µeff, e.g., > 40 cm 2 /Vs, and the CdSe TFT LCD was first demonstrated in 1973 [16]. 8

30 However, due to difficulties in controlling the compound semiconductor thin film material properties and device reliability over large area, this technology was never mass produced. These reliability issue was resolved when the first functional TFT with hydrogenated amorphous silicon (α-si:h) as the channel layer was made in 1979 [17]. The simple fabrication process made it suitable device for mass production, and it is still the most dominant TFT technology currently. However, α-si the mobility is too low for high-speed or large-current applications, such as the driving circuit of the display or the driving pixel in the organic light emitting diode (OLED) displays. Α Si:H is a photoconductor at visible wavelengths, the TFT has large leakage current under light exposure. Amorphous and crystalline metal oxide TFTs (oxide TFTs) have attracted tremendous attention recently due to the high mobilities. The oxide semiconductor TFT dates back to the mid-1960s [18, 19] and only poor electrical performances were obtained from TFT device based on SnO2 [20], until reports on ZnO TFTs by Hoffman et al, Carcia et al. and Masuda et al appeared in Hoffman and Carcia reported fully transparent devices with performance comparable and even better in some aspects than the α-si: H and organic TFTs. The single-crystal ZnO shows large Hall mobility as high as 200 cm 2 /Vs. The later work from Carcia et al. even demonstrated the availability of ZnO by using r.f. magnetron sputtering. However, the channel of ZnO TFTs is polycrystalline if deposited at room temperature, and, therefore, the long-term stability and uniformity suffer from grain-boundary problems, which is also the common issue for polycrystalline silicon (p-si). Another critical issue of ZnO and other oxide semiconductor is their high concentration of mobile electrons 9

31 (typically >> cm -3 ) which make the control of threshold voltage and off-current difficult. To solve these problems, Nomura et al. suggested in 2003 to use a complex InGaO3(ZnO)5 (or IGZO) single-crystalline semiconductor layer in a TFT [21]. Though a very high temperature of 1400 C was needed, it showed high mobility of 80 cm 2 /V s and high on/off ratio of 10 6, and made the high-performance oxide semiconductor-based TFT possible. In the following year, they improved the work by depositing amorphous IGZO as channel layer through PLD at near-room temperature. Though the mobility of 9 cm 2 /V s and on/ off ratio of 10 3 were far from the single-crystalline TFTs, the amorphous TFT is an impressive achievement because its low sensitivity to crystal structure disorder and better uniformity than crystalline oxide semiconductor over large areas Device Structure Figure 2.1 illustrates typical device structures used for TFTs. Based on the stacking order of the gate electrodes, channel layer and source/drain electrodes, the TFT structures and be classified into top/bottom gate and top/bottom contact. The top-gate structure is employed when it is difficult to form a bottom electrode. This structure has other advantages. For example, it only require two patterning mask steps at minimum, and the top gate electrode and insulator layer can also act as passivation layer that protect the channel layer from water/oxygen absorption and desorption due to atmospheric exposure. Bottom-gate structures are common in laboratory research because commercially available oxide/substrate wafer can be used as the insulator and bottom gate electrode. Furthermore, usually insulator layer is deposited at high temperature; depositing insulator layer first will not affect the semiconductor channel layer. But the disadvantage of this structure is also 10

32 apparent. First, the top-channel is exposed to the atmosphere and causes the instability in device characteristics. Second, the overlap between bottom gate electrodes and source/drain electrodes are very large, and the charge and discharge process takes long time due to the large parasitic capacitance and lower the device working frequency. Based on the relative location between source/drain contact and semiconductor/insulator interface, the structure can be classified into co-planar structures and staggered structures. In the coplanar structure, the source/drain contacts are on the same level with semiconductor/insulator interface where conducting channel forms. This structure benefits the lower resistance because the source/drain electrodes directly contact with the induced conducting channel. For stagger structures, source/drain contacts and semiconductor/insulator interface lay on the opposite sides of semiconductor film. For this structure, current from electrodes needs to go through the resistive film vertically to reach the induced channel. The staggered structure also provides a large contact area for charge injection. 11

33 FIG Schematics of some of the most conventional TFT structures, according to the position of the gate electrode and to the distribution of electrodes relatively to the semiconductor [22] Basic Device Operation TFTs are three terminal field-effect devices, whose working principle relies on the conducting channel modulation by a gate electrode with the modulated current flowing in the channel between source and drain contacts. TFTs work similarly to other field-effect device such as metal oxide semiconductor field-effect transistor (MOSFETs). In MOSFETS, a doped silicon wafer acts as both the substrate and the active semiconductor. An inversion region is formed close to the dielectric/semiconductor interface, i.e., a n-type conductive layer is created in a p-type silicon substrate. TFTs can use an insulating substrate, normally glass, and the conductance of the semiconductor is achieved by an accumulation layer. In this section, a TFT with n-type semiconductor is used to explain the device operation principle under n channel accumulation mode. 12

34 Figure 2.2 shows the cross-section view of the TFT structure and the energy band diagram of the device at different gate biases. Some assumptions are made before the discussion. In this example, the semiconductor is slightly n type. A similar discussion is also available for p type TFTs. There is no charge trapped in dielectric and semiconductor or at dielectric/semiconductor interface. The semiconductor and gate electrode have the same work function, which guarantee that no accumulation or depletion is appeared at 0 gate bias. Figure 2.2 (b) shows the energy band diagram at equilibrium, where no external voltage is applied on the gate electrode. As the work function of semiconductor and gate electrode are equal, Fermi level of semiconductor is aligned with gate electrode work function, the energy band is not bent. When a positive gate bias is applied, the external electric field attracts mobile electrons inside the semiconductor to accumulate at the dielectric/semiconductor interface, which acts as the conducting channel layer. This can also be explained by the band diagram of Figure 2.2 (c), where a positive gate voltage lower the gate electrode energy band relative to semiconductor, which bends semiconductor the conduction band downward more close to the Fermi level. The smaller space between conduction band minimum and Fermi level at the interface region demonstrates that more electrons are accumulated above conduction band. This corresponds to the on state of the device. On the other hand, when a negative gate bias is applied on the gate electrode, electric field pushes the mobile electrons away from the dielectric/semiconductor interface and forms a thin layer of depletion region. From the view of band diagram, negative external electric field by gate bias higher the gate electrode work function relative to the 13

35 semiconductor energy band, which bends the semiconductor conduction band upward away from the Fermi level. This larger space between conduction band minimum and Fermi level in semiconductor at the interface region means less mobile electrons exist, leaving only ionized donor and positive space charges. The width of the depletion region increases along with the rising magnitude of the negative gate bias, and the entire semiconductor layer can be fully depleted. In this case, no conduction channel layer exist between drain and source contacts and the device is in off state. Enhancement mode transistor is always desired in the circuit design, which is always in off state with zero gate bias. To make the TFTs in enhancement mode, a relatively low carrier concentration and thin channel are necessary, as a very negative gate voltage is needed to fully depleted the channel and turn off the device if the carrier concentration is high, or the channel is too thick. (a) (b) (c) (d) FIG The TFT structure and energy band diagram as viewed through the gate: (a) the crosssection structure of TFT, (b) at equilibrium, V GS=0, (c) accumulation mode, V GS > 0, (d) depletion mode, V GS < 0. 14

36 The operation of enhancement mode TFT can be separated into two different modes, depending on the voltages at the terminals. When the gate bias is high enough to establish the accumulation layer and turn on the device, a positive voltage between drain and source (VDS>0) creates current flow. When the drain voltage is small compared with gate voltage, the channel charge density is fairly uniform from the source to the drain, and the drain current increases linearly with respect to VDS at a given VGS, so this is the so called linear region. This is the TFT operates like a resistor, and the resistance depends on the channel charge density, which is a function of the gate bias (VGS). In the linear region (VDS<VGS- Vth), the current from drain to source is modeled as below: WW II DDDD = μμ FFFF CC oooo (VV LL GGGG VV tth )VV DDDD VV 2 DDDD 2 (2.1) Where μfe is the charge-carrier effective mobility, W is the gate width, L is the gate length and Cox is the gate oxide capacitance per unit area. When VDS is very small, the second term in the parenthesis can be neglected, and the drain current is linearly proportional to VDS at a given gate voltage VGS. As VDS increases, the accumulation-layer charge density at the drain end of the channel is reduced; therefore, drain current does not increase linearly with VDS. When VDS reaches VGS-Vth, the channel is pinched off at the drain end, and drain current ID saturates. Further increase in drain voltage does not result in higher drain current, and the device is operating in saturation region. In the saturation region (VDS>VGS-Vth), ID is described by II DDDD = μμ ssssss CC oooo WW 2LL (VV GGGG VV tth ) 2 (2.2) For saturation mode, μμ ssssss represents the average of the carrier mobility including both the accumulation region and pinch off region. The two equations above are only available 15

37 for ideal TFTs, in real cases, μsat and μsat always depend on VGS because of other factors such as interface traps or Coulomb scattering. 2.2 Electronic Structure of Amorphous Oxide Semiconductor (AOS) Amorphous semiconductors are preferred over crystalline or polycrystalline semiconductors as active layers mainly because the low processing temperature and uniformity of the device characteristics. However, the carrier mobility of α-si:h is limited to ~1 cm 2 /V s, which is lower by two or three orders of magnitude than that of singlecrystalline Si (~200cm 2 /V s for carrier concentration ~10 19 cm -3 ). In silicon, the conduction band minimum (CBM) and valence band maximum (VBM) are made of the anti-boding (sp 3 σ*) and bonding (sp 3 σ) states of Si sp 3 hybridized orbitals, and the band gap is formed by the splitting of these two energy levels (Figure 2.3 (a)). The sp 3 orbitals have strong spatial directivity, thus in amorphous silicon, even small fluctuation in the chemical bounds results in high-density tail localized states in the forbidden band, which trap carriers (Figure 2.3 (e)). The carrier transport controlled by hoping between localized tail-states and band conduction is not achieved, which cause the low mobility in α-si. By contrast, amorphous oxide semiconductors have strong ionicity and the electrons transfer from the s orbitals of metal atoms to 2p orbitals of oxygen atoms (Figure 2.3 (b)). The Madelung potential formed by these ions raises the energy levels in cations and lower the levels in anions and creates the VBM by unoccupied s orbitals in metal cations and CBM by fully occupied 2p orbitals in oxygen anions (Figure 2.3 (c)). The unoccupied s orbital metal cations are spherically extended and can easily overlap with another s orbital from the neighboring metal cations (Figure 2.3 (f)). The spherical orbital is not direction sensitive and the electron transport is not effected by the local structure disorder. 16

38 FIG Schematic electronic structure of silicon and ionic oxide semiconductors. (a-c) Bandgap formation mechanisms in (a) covalent and (b,c) ionic semiconductors. (d-g) Carrier transport paths in (d) c-si, (e) α-si, (f) crystalline oxide and (g) amorphous oxide [23]. 2.3 Indium Gallium Zinc Oxide (IGZO) As discussed in section 2.2, amorphous oxide semiconductor is the ideal candidate for active layer with high mobility and excellent large-area uniformity. However, Figure 2.4(a) shows that for binary oxide materials, such as pure ZnO and In2O3, only crystalline films can be formed even when deposited at room temperature. One of the principles of forming amorphous materials is mixing multi-components with different crystal structures. For example, In2O3 and ZnO have bixbyite and wurtzite structures, respectively, this allow In- 17

39 Zn-Oxide (ZO) to have an amorphous phase. Oregon State University and Hewlett-Packard have reported the fabrication of a-zn-sn-o (a-zto) TFTs [24] and Zn-In-O (a-zio) TFTs [25] with very high mobility up to 55 cm 2 /V s. Even though a-izo meet the requirement of excellent uniformity and large mobility, one crucial issues with this material is that it exhibits a high carrier concentration of >10 17 cm -3, which can lead to large off-current and small on-off ratios [26, 27]. The high carrier density origin from the oxygen vacancy in semiconductors, thus incorporating ions with high ionic potential to form strong chemical bond with oxygen ions and suppress the formation of oxygen vacancies should be the solution. Nomura et al. inserted Ga into IZO and demonstrated that the carrier concentration of α-igzo can be lowered below <10 17 cm - 3 while contain high electron mobility (~10 cm 2 /V s). Figure 2.4(b) shows that α -IZO (bottom of the pyramid) has higher electron mobilities than α-igzo (top of the pyramid). Thus, incorporating certain portion of Ga 3+ is critical to reduce the carrier concentration. Besides, Ga also helps keep the film in amorphous states due to its large atom radius. (a) (b) FIG (a) Amorphous formation and (b) electron transport properties of In 2O 3-Ga 2O 3-ZnO thin films. The values in (b) denote the electron Hall mobility (cm 2 /V s) with density (10 18 cm -3 ) in parentheses [28]. 18

40 Table 2.1 summarizes the current TFT technologies, and shows that α-igzo is the only candidate that can achieve the balance between high mobility, low carrier concentration and large area uniformity. This implies a good choice to replace α-si for future generation displays. Table 2.1. Comparison of several materials used in displays [29]. Figure 2.5 (a) shows the crystal structure of InGaZnO4 and Figure 2.5 (b) shows the calculated density-of-states (DOS) distribution of InGaZnO4. As the VBM is located at zero energy level, the valence band is mainly formed by Zn-3d and O-2p orbitals and the conduction band (peak at lower energy level above 0) contains the s orbital of In, Ga and Zn ions. The location of In-5s orbital energy is lower than the other two ions, thus the CBM origins from the In ions. Nomura et al. subsequently confirmed this conclusion by calculating α-igzo electronic structure through pseudopotential and plane wave method at the local-density approximation (LDA) level [30]. 19

41 (a) (b) FIG (a) (Color) Structure of the InGaZnO 4 crystal. The brown, blue and red balls represent In, Zn/Ga and O atoms, respectively. (b) Partial density-of-states (DOS) curves for InGaZnO 4 crystal structures. The top of the valence band is located at zero energy and total DOS is also shown in each figure as reference. (After Orita et al., Ref [31]) IGZO also exhibits unusual carrier transport properties as shown in Figure 2.6 (a) compared with other crystalline semiconductors: The maximum Hall mobility is similar for crystalline IGZO and α-igzo a and its electron mobility increase with increasing freeelectron density. The first property is explained earlier that as the CBM is formed by s orbital of metal cations which are insensitive to the structure disorder, thus the amorphous phase of IGZO will not affect the overlap of orbitals between neighboring metal cations. Second property is explained by a percolation conduction model [32] as shown in Figure 2.6. It assumes that carrier transport is controlled by distributed potential barrier above CBM with the average height of Ecenter and the energy distribution of ΔE. These values are 20

42 summarized in Figure 2.6 (b), showing that Ecenter are mev and ΔE are 5-20 mev. As illustrated in Figure 2.6(c), electrons take shorter transport path at high temperature even if these paths have high potential barrier (path (i) in Figure 2.6 (c)). They tend to take longer path (ii) with lower barrier at lower temperatures because the kinetic energy is not sufficient to pass though the higher barriers. (a) (b) (c) FIG (a) Hall mobilities of InGaO 3(ZnO) m as function of electron density.c-igzo1 and c- IGZO5 represent crystalline phases with m = 1 and 5, respectively. HQ and LQ denote high-quality and low-quality, respectively. (b) Potential distribution above CBM analyzed based on percolation transport model [33]. (c) Illustration to explain the percolation conduction model [34]. 2.4 Modeling and Simulation of α-igzo TFT Although the fundamental transport properties and electronic structures of α-igzo has been studied, the subgap density of states (DOSs) also plays important role in amorphous semiconductor. Recently, published papers have proposed technology computer-aided design (TCAD) device simulators to reproduce the measured current-voltage characteristics by modeling subgap density of states with proper fitting parameters [35-37]. 21

43 The subgap Density of states-based Amorphous Oxide TFT Simulator (DeAOTS) is proposed [36] based on previous work on the α Si:H TFT model [38-42]. The model contains two components: the acceptorlike conduction band-tail states (gcba) and the acceptorlike deep-gap states (gda). Such tail states is formed by the structural disorder within an amorphous material which can induce electron scattering and localize the wave function [43, 44]. In α-igzo, this band-tail states origins from the disorder of metal ion s- orbitals, while the ionized oxygen p-orbitals behaves as the valence band-tail states (gvbd). The deep states in α-igzo is formed by the oxygen vacancy (OV). It has been pointed out that OV can act like a donor and locates close to the conduction band minimum (CBM) if post-thermal annealing or propr film growth process is applied. It also has a Gaussian distributed states ggd. The three types of subgap states, conduction band-tail states (gcba), the valence band-tail states (gvbd) and OV donor-like deep states (ggd) are given by the following expressions [45]: gg CBa = gg ta exp[(ee EE CC )/EE aa ], (2.3) gg VBa = gg td exp[(ee VV EE)/EE dd ], (2.4) gg Gd = gg d exp[ (EE λ) 2 /σσ 2 ], (2.5) Where EC and EV are conduction and valence band edge energies, gta and gtd are densities of acceptor- and donorlike states at E=EC and E=EV, respectively, Ea and Ed are characteristic slope of conduction and valence band-tail states, respectively, and gd, λ and σσ are the peak value, the mean energy, and the standard deviation of states, respectively. Figure 2.7 (a) shows the proposed density of states (DOS) model for α-igzo. By fitting the parameters from experiment, simulated result shows good consistency with experiment result as shown in Figure 2.7 (b) (c). Reports [46] also indicate that the location of donorlike 22

44 states is important. If the location of donorlike states is much higher than the intrinsic Fermi-level, then all donorlike states are ionized and induced electrons by gate voltage need to fulfill the ionized donorlike states before entering the subthreshold region to fill the band-tail state. Thus wider or higher donorlike states distribution will shift the threshold voltage. While for band-tail states, higher DOS results in lower current but no change to the threshold voltage. This suggests that both the energy locations of OV states and DOSs of band-tail states and donorlike states should be properly controlled to achieve a high performance α-igzo TFT. FIG (a) Proposed DOS model for α-igzo. 2. E C and E V are conduction and valence band edge energies, respectively. Solid curves within the bandgap represent the exponentially distributed band-tail states (g CBa, g VBd), while the dash curve near the conduction band edge represents the Gaussian-distributed donorlike OV states (g Gd). (b) and (c) Transfer characteristics (W/L=180/30 μ. ( Both experimental (circle) and simulation data (solid line: Schottky contact; +: Ohmic contact) are shown. Extracted threshold voltage (V th), field-effect mobility (μ eff), and subthreshold swing (S) are also indicated. Inset of (c): the 2D TFT structure used in simulation. 23

45 Based on this model, Jeong and Hong [47] examined the Debye length and active layer thickness-dependent performance variations of α-igzo TFT. Figure 2.8(a) shows the threshold voltage Vth and on/off ration as function of semiconductor thickness for different free carrier density ND. For the depletion mode TFT (ND = cm -3 ), Vth is shifting to positive direction slightly with increasing thickness as more ionized donorlike states (electron trap) need to be filled by induced electrons before free electrons can form a conducting layer. For enhancement mode TFT (ND > cm -3 ), intrinsic free carrier density is high, which makes increase the off current and lower the on/off ratio. Besides, larger negative gate voltage is needed to deplete the free electrons from the active layer, which shift the Vth to negative direction. Figure 2.8(b) and (c) shows the compare of band profile of TFT between active layers with thickness d=150 nm and d = 200 nm. When free carrier density is high, to deplete the electrons through the whole semiconductor, Fermi level needs to be pull down away from the conduction band. However, due to the existence of donorlike states, Fermi level is pinned near the envelope of donorlike deep states. 24

46 FIG (a) V TH and on/off ratio as a function of semiconductor thickness for different N D. Band profile of TFTs with (b) d =150 nm and (c) d = 200nm. The QFL is close to the conduction band edge when high negative voltage is applied to gate electrode for d = 200nm. In fact, this threshold thickness dth is closely related to Debye length ld because ld determines the maximum potential transfer length through the semiconductor layer when bias is applied. Since the Debye length is a function of both free carrier density ND and the average amount of donorlike deep sates NS, qualitative calculation is performed to relate dth to ND and NS: dd TH ll DD = εε ss qq 2 NN SS + NN DD kkkk (2.6) All simulated results indicate that the active layer thinner than dth is essential for highperformance α-igzo TFTs. To achieve that goal, intrinsic free carrier density as well as donorlike deep states should be carefully optimized. 25

47 2.5 Fundamentals of IGZO TFT For this section, we overview the fundamental issues in IGZO TFT performance and fabrication process Contact Electrode In order to reduce the response time of the circuit, the resistance of source/drain electrodes should be minimized. Y. Shimura et al. measured and compared the contact resistance between IGZO and various metallic electrodes, including Ag, Au, In, Pt, Ti, ITO, and IZO [48]. All the materials except Au and Pt exhibited a linear relation of currentvoltage characteristics, while Au and Pt resulted in Schottky contacts. Among these materials, Ti and ITO are the best electrodes. The contact resistance also strongly depends on the carrier density of the channel surface, therefore, treatments such as Ar plasma treatment [49] have been employed to improve the contacts. Multilayer electrodes structures such as Ti/Au and Ti/AL/Ti are also used for electrodes, Au layer protects the bottom reactive contacting metal while Ti layer improves the adhesion of the whole contact and reduces the resistivity Gate Dielectric Materials The effects of gate dielectric in contact with the semiconductor are also important. Silicon oxide and silicon nitride have been most widely used as gate dielectric for both oxide semiconductor TFTs and conventional Si-based transistors. Α-IGZO TFTs with SiOx gate dielectric shows better threshold voltage stability compared with SiNx due to the higher hydrogen content in SiNx films providing more charge trap sites, which would produce a high shallow hydrogen-related states. Besides, the valence offset between the 26

48 SiNx and IGZO film can be estimated as ~ 0.15 ev, which is much smaller than (~2.80 ev) that between the SiO2 and IGZO film [50, 51]. Therefore, the photocreated hole carriers can be injected easily into the SiNx gate dielectric due to its low valence band offset value, which would be partly responsible for the inferior stability of device. Optimization of gate dielectric materials will be helpful in reducing the charge trap concentration. Due to limited battery capacity, low power consumption is the key issues in terms of mobile device display application. High-k gate dielectric is an effective approach to reduce power consumption by lower the driving voltage needed to create the accumulation channel layer in IGZO. Various high-k materials have been studied for TFT applications such as Al2O3 by Lim [52], Y2O3 by Yabuta[53], BaSrTiO by Kim[54] and Ta2O5 by Zhang [55]. However, by systematic studies, it was suggested that a Coulomb scattering mechanism by phonon scattering from the large polarization of high-k gate dielectric can limit the channel mobility [56]. Also, for the application of the high-k gate dielectric, further investigation on high leakage current, low band gap, interfacial reaction and interface traps have to be performed Device Stability Long-term stability is the most critical issue of TFTs for mass production. Though α- IGZO thin film can be deposited at room temperature, annealing is necessary to improve the uniformity and stability. Electrical conductivity increase with annealing temperature up to ~300 C and then starts decreasing [57]. Constant bias stress test also indicated that annealed α-igzo TFTs are much more stable with Vth shit (ΔVth) less than 1V. Most of the instability of bottom-gate α-igzo TFT comes from the adsorption/desorption of oxygen and water molecules at back-channel surface and can be 27

49 resolved by covering the TFT with another passivation layers. More recently, illumination stability and negative bias-light illumination (NBL) stability have become more important. The typical transfer characteristics under monochromatic illumination in Figure 2.9 (a) [58] shows that α-igzo TFTs respond to photo energy above 2.3 ev, which is lower than the band gap (3.1ev). It is attributed to the excitation of electrons from deep subgap states to the conduction band as shown in Figure 2.9 (b). Sony reported the use of a dc-sputtered AlOx passivation layer suppressed the photo-response to a cold cathode fluorescent lamp [59]. The temperature instability of IZO TFTs was also studied independently to evaluate the density of state (DOS) distribution of the IGZO semiconductor itself [60, 61] or to understand the limitation of the practical application [62]. Figure 2.10 [63] shows the temperature dependence of the threshold voltage shift of α-igzo TFTs with SiOx film deposited by PECVD as a gate insulator, the transfer curve shift to lower (more negative) turn-on voltage with increasing temperature is observed. FIG (a) Typical response to monochromatic light of transfer characteristic of annealed α-igzo. 2 TFT. The photon flux was fixed at ~ photons (cm -2 s -1 ). The blue dashed lines correspond to illumination above the band gap (>3.1 ev) and the black solid lines correspond to subgap illumination. (b) Model to explain NBL instability. 28

50 FIG Temperature dependence of transfer characteristics (V DS=10V, L/W = 10/100 µ): (a) ascending sequence and (b) descending sequence. The lower threshold voltage observed for the increased temperature may be associated with the generation of point defects, peculiar to oxide semiconductors. Thermally excited oxygen atoms that can leave their original sites induce vacancies (point defects) with remaining free electrons at the sites. Lower threshold voltage can be attributed to these free electrons generated along with the oxygen vacancies. A lower trap density gives rise to less threshold voltage operating temperature dependence because an equilibrium Fermi level position is releases from pinning close to conduction band minimum. The mobility is also found to increase slightly with increasing temperature, which can be attributed to enhanced carrier detrapping combing with percolation theory. 29

51 2.6 Integrated Circuit Based on IGZO The high mobility and large-area uniformity of α-igzo makes it as the perfect material for the new-generation active-matrix backplane technology, especially in highperformance LCD and OLED displays which play important role in electronic device market. Another important feature of α-igzo is its low processing temperature, which meets the recent emerging need for flexible display. Besides display backplane, gate driver should also be integrated on the flexible substrate. The large carrier mobility of α-igzo also enable the implantation of more sophisticated glass-based devices known as systemon-glass (SOG) or system-on-panel (SOP) devices. In these devices, electronics circuits such as pixel drivers and other peripheral circuits are integrated with TFT arrays on the same glass substrate. However, most of the research is still on display applications or discrete devices [64-66]. Few reposts have been published on logic gates, DRAM, SRAM or other sophisticated integrated circuits other than the driving circuits of display. One critical issue that degrades the α-igzo based integrates circuit performance is the difficulty in making p-type α-igzo TFTs. The possible reason is that large hole effective mass and the high DOS of hole-trap in bandgap. To make the basic elements in integrated circuit, most current researches are using n-type as the load to replace p-type TFT in inverters. Hwang et al. proposed two inverters for mobile display application using only n- channel α-igzo TFTs [67]. One inverter includes cross-coupled structure causing positive feedback to overcome the limitation of circuits designed with deletion mode n-channel oxide TFTs. The other inverter includes the cross-coupled structure which can sue the bootstrapping effect to improve operating frequency and voltage. The inverter operates at 30

52 the frequency of 20 khz when the VDD is 15V and could be applied in driving circuit for flat panel displays. Report on α-igzo TFTs and load inverters with a short channel length (2 μm) were represented at 2013 [68]. The TFT shows mobility of >5 cm 2 /V s with Vth value of V, and no degradation such as a negative shift of Vth or degradation of the subthereshold slope by the short-channel effect, were observed as illustrated in Figure 2.11 (a). The characteristics of load inverters using the same IGZO TFTs show maximum voltage gain of >4 and a RC delay time of 0.53 μs at 10 khz. (a) (b) FIG Temperature dependence of transfer characteristics (V DS=10V, L/W = 10/100 µ): (a) accending sequence and (b) descending sequence. Lee et al. reported a high performance α-igzo TFT inverter using enhancement mode driver and the depletion mode load [56]. The α-igzo layer was deposited by RF magnetron sputtering and the threshold voltage was controlled by adjusting the deposition time to make enhancement mode TFT or depletion mode TFT. For staggered structure, the distance 31

53 between source/drain mental contacts and accumulation channel increases with the thicker α-igzo film, thus TFT with thicker thin film exhibits lower mobility and can be depletion mode with negative threshold voltage. The proposed inverter showed much improved switching characteristics including higher voltage gain, wider swing range, and higher noise margins compared to the conventional inverter with an enhancement load as shown in Figure FIG Schematic diagram and voltage transfer curve of the inverter with a depletion load (a) and enhancement load (b) [69]. The dual-gate (DG) α-igzo TFTs for NOR and NOT logic operation using passivation dielectric were proposed [70]. The passivation dielectric separates both top-gate and bottom-gate from the α-igzo. The active layer as shown in Figure 2.13 (a). By applying a positive voltage to the top gate of a TFT that is serially connected to the next adjacent TFT, an inverter with voltage gain of ~9 and desirable transition voltage of ~2.5 V under 5V VDD was achieved. A NOR logic gate was also available by the independent control of 32

54 the dual gates. Luo demonstrated the α-igzo based NAND and NOR logic gates with separate devices as shown in Figure 2.13(b). TFTs with 5-, 10-, 20-jacent TFT, an inverter with voltage gain of ~9 and desirable transition Vth of 0.2 V, subthreshold slope less than 190 mv/dec and on/off ratio larger than The NOR and NAND logic gates exhibit sharp transfer characteristics and satisfactory functionality between 1 and 20V with operating frequency reaching 5 khz. FIG Optical microscopic image of dual-gate α-igzo. 2 [45] (a) and NAND, NOR gate using separate devices [71] (b). To testify the quality of the TFTs with certain fabrication process in real circuits, the dynamic characteristics of the TFTs are important, and propagation delay of a ring oscillator (RO) is a widely accepted benchmark of how fast the field-effect transistors (FETs) can operate. The first integrated circuit based on oxide-semiconductor channel TFTs that outperformed α-si:h TFTs and organic TFTs in operation frequency was demonstrated in 2007 [72]. A five-state ring oscillator composed of α-igzo TFTs with channel lengths of 10μT can operate at 410 khz when the external supply voltage is 18V. 33

55 Suresh et al. [73] improved the performance by demonstrating a five-stage ring oscillator working at frequencies as high as 2.1MHz with a supply voltage of 25V. The IGZO channel was pulsed laser deposited at room temperature. Memory is an important element of integrated circuit for system-on-glass (SOG) or system-on-panel (SOP). A traditional 1-bit SRAM composed of 6 α-igzo TFTs fabricated on flexible polymide foil was demonstrated [74]. The circuit continues working up to operation frequencies of 10 khz with a supply voltage of 5V. The result for the first time shows the circuit performance under tensile mechanical strain, and the output signal was almost unchanged even under the bending with a radius of 5mm. Emerging nonvolatile memories such as phase-change random access memory (PRAM) and resistive random access memory (RRAM) have been developed recent years and have advantages of low-voltage and high-speed data writing and reading. However, the performance is limited by small on/off current ratio of approximately 10 4 or less. The oxide semiconductor can solve this problem because of its extremely low leakage current. Inoue et al. [75] demonstrated the operation of nonvolatile oxide semiconductor random access memory (NOSRAM) using α-igzo. The NOSRAM single cell fabricated with the 0.8- μm process technology shows an on/off ratio of 10 7 and endurance over write cycles. A 1-Mb NOSRAM was also achieved with write operation at 150 ns/ page with supply voltage of 4.5 V or less. 2.7 Laser Interference Lithography Though photolithography is widely used for micron-scale devices and integrated circuit (IC), and the combination of short wavelength light sources [76, 77] and innovations such as immersion lithography [78-82] and phase shift masks [77, 83] have pushed the feature 34

56 size into the nanometer scale, it also includes very expensive masks and lens systems. A much simpler methodology, laser interference lithography (LIL), which is based on the interference of two or more coherent laser beams, can produce periodic patterns over large areas [84-93] with feature dimensions approaching 20 nm [94]. In this section, the basic theory of LIL and the concepts of fabricating on dimensional (1D) and two-dimensional (2D) periodic structures are presented Basic Theory Interference is the result of space superposition of two or more coherent beams. The intensity distribution of the electric field varied between maximum which exceed the sum of the individual intensities of the beams, and minimum which may be zero. The intensity pattern is determined by the differences of optical path in all involving coherent beams and can be recorded in photoresist which will be developed to define the nanostructure of the layer under the photoresist. Typically, one laser beam with an output in the visible wavelength or the UV is divided into multiple beams using optical elements such as beam splitters or prisms. A 1D periodic intensity pattern can be formed by overlapping two coherent plane waves as shown in Figure The period, d, of the interference pattern is determined by the wavelength, λ, of the laser used, the index of refraction, n, of the photoresist, and the angle, θo at which the two beams interfere [95]: dd = λλ 2nn ssssss(θθ) (2.7) 35

57 (a) (b) FIG (a) Two-beam interference forms s standing wave. (b) A SEM image of 1D interference pattern having a 1 μm periodicity recorded in the negative photoresist SU-8. Figure 2.14 (b) shows a SEM image of 1D structure with a ~1 μi periodicity formed by interfering two coherent beams with wavelength of 355 nm at an incident angle of ~14. To further reduce the period, shorter wavelength and large angle between two interfering beams should be used. The fringe contrast of the pattern, V, is defined as [96]: VV = II mmmmmm II mmmmmm II mmmmmm +II mmmmmm (2.8) Where Imax and Imin are the maximum and minimum intensities in the interference pattern, respectively Two-Beam Interference Arrangements Two experimental arrangements widely used for two-beam interference. The first is Lioyd s mirror interferometer as shown in Figure 2.15 (a) [94]. The angle between the sample to be patterned and the mirror is set to be 90, and the bottom incident beam reflected by the mirror coherence with the top incident beam at the wafer which is covered 36

58 with photoresist. This setup has been used successfully with sources having a high transverse coherence such as a single-mode TEM Ar-ion laser [97]. This optical system is easily builds up and to tune the incident angle by just rotating the Lloyd s mirror. However, the substrate areas that can be illuminated at very small or large incident angle are small. It is expensive to employ large size mirror because the exacting smoothness and flatness tolerances of the mirrors are difficult to guarantee over large areas. This problem can be resolved by the second arrangement as shown in Figure 2.15 (b). The laser from the source is split into two beams using a beam splitter and recombine them on to the substrate through lens and pinholes which are used to optimize the beam quality. However error can accumulate when both beam travel long distance after beam splitter and encounter different optics, vibrations, mirror imperfections, spurious scattering and a variety of other deleterious effects. This issue can be overcome using a fringe-locking system [86] and Spallas et al. [98] has demonstrated the effectiveness of this arrangement to fabricate uniform array over a cm glass substrate. The obvious disadvantage is that this arrangement requires more optical elements and is more complicated. FIG Two commonly used two-beam IL setups. (a) A Lioyd s mirror configuration, (b) A two-beam configuration created by a beam splitter. The dotted triangle represents the prism used in liquid immersion lithography [99]. 37

59 Simple 2D periodic pattern can be formed by first defining 1D gating and then rotating the sample by specific angle and performing a second exposure to create 2D gating with desired shape [85, 100]. Defining a 2D array of squares can be obtained by doing the first exposure with the periodicity along x-direction and rotate the sample by 90 and continue the second exposure with the periodicity along y-direction. Figure 2.16 (a) is a contour simulation for the 2D array of squares. The regions with highest exposure intensity are in red and regions with lowest exposure intensity are in blue region, and the color between red and blue indicates a moderately exposed region [85]. To define the pattern we want, the region with color close to red should be exposed with an intensity over a threshold value and can be removed by developer later and region with color close to blue should be less exposed and remain after developing to be the square mesas. To achieve this goal, the two exposure times and developing time need to be set carefully because nonlinear sigmoidal intensity response of typical photoresist [101, 102]. Structures other than square pattern can be achieved by rotating a different angle after 1 st exposure. Figure 2.16 (b) shows the 2D hexagonal structure with a rotation about 60 between two exposures [103]. Simulation or experiment are necessary to find the optimum exposure time as the intensity distribution and intensity response of photoresist are sensitive to even a tiny angle change. 38

60 FIG (a) A simulation contour map of an IL pattern formed by a double exposure first in the x-direction and then in the y-direction. (b) A SEM image of a hexagonal structure created by double exposure IL where the substrate was rotated 60 about its normal between exposures Two Degrees-of-Freedom Lloyd-Mirror Interferometer To keep most of the advantage of the traditional Lloyd-mirror interferometer, such as stability and simplicity while obtain larger pattern coverage area, a tunable Lloyd-mirror interferometer with two degree of freedom was developed as shown in Figure 2.17 [104]. Compared with traditional Lloyd-mirror with a constant angle between mirror and substrate, the angle between the sample and incident light s phase front and the angle between the mirror and the incident phase front can be adjusted. For this case, the 1D pattern periodicity is given by the following equation: PP 2 DDDDDD = λλ 2cccccccc sin (xx+yy) (2.9) We will use this 2-DOF Lloyd-mirror interferometer to define the 2D periodic nanostructure of α-igzo active layers. 39

61 FIG Schematic of Lloyd-mirror interferometer with 2-DOF configuration, the angles x and y are varied independently Multi-Beam Interference Lithography for Nano-Electronics Current integrated circuits combine very regular layouts with underlying grid patterns which defines the smallest feature size. Multi-beam interference lithography (MBIL) can be sued to define this underlying periodic or quasi-periodic grid-based structure. MBIL is applied first to define the period pattern containing the minimum feature size of the device, then a second lower spatial-frequency trim exposure may be used to define the non-periodic structure with much larger dimension using a conventional technique such as photolithography. This is a simple, fast, low cost and mass-production available method to eliminate the diffraction limitation of using normal photo-lithography alone. Figure 2.18 (a) illustrates the use of two-beam interference to form vertical fingers, followed by a second traditional low-pith photo-lithography exposure [105, 106]. Figure 2.18 (b) demonstrates a multi-step procedure to create more complex composite patterns [106, 107]. 40

62 FIG (a) Scanning electron microscope image of combining MBIL and photo-lithography techniques. Two-beam interference lithography is used to define 45nm grid lines and higher spatial frequency modulating pattern was defined by photo-lithography (Copyright 2004, Reprinted with permission of Cambridge University Press [108]). (b) A complex composite pattern is created by two exposure and modulated by photo-lithography (edited with permission from [107]). By using this technique, a high-throughput, all-optical lithography method that addresses the requirements of the 32 nm node was demonstrated [109]. Since interference lithography can generate dense but regular pitch patterns, a key challenge to this hybrid lithography is the conversion of existing designs to regular-linewidth, regular-pitch layouts. Greenway et al. [110] proposed a one-dimensional regular pitch SRAM bitcell layouts which are amenable to this hybrid lithography. The fabricated 6T bitcell with 32nm gate length shows electrical characteristics that are comparable to those of existing bitcell layouts. Triple-gate metal-oxide-semiconductor field effect transistors fabricated with interference lithography was also illustrated [111]. In this work, a 350 nm grating exposure is made by laser interference lithography over the whole sample surface, followed by a contact lithography carried out to erase unwanted parts of the grating. The electrical characteristics of the triple-gate MOSFETs acre comparable to results achieved with e- beam lithography defined devices. 41

63 CHAPTER 3 TOOLS FOR SIMULATION, EXPERIMENT AND DEVICE CHARACTERIZATION This chapter introduces the important facilities and tools used for both device fabrication process and device simulation. 3.1 TCAD Simulation and Modeling of α-igzo TFT TCAD Introduction Technology CAD (TCAD) is a branch of electronic design automation that models the semiconductor fabrication and semiconductor device operation. It simulated the fabrication operation and reliability of semiconductor devices by using physical models, thereby allowing the exploration and optimization of new semiconductor devices. TCAD reduces the number of engineering wafers, saving time and money and provides engineers with important insights on the behavior of semiconductor devices which can lead to new device concepts. The suite of CAD tools in this work is Sentaurus TCAD by Synopsys, which work seamlessly and can be combined into complete simulation flows in 2-D and 3-D. It supports silicon and compound semiconductor technologies, covering a broad range of semiconductor applications. It also allows the customized material library which facilitates the prediction and optimization of device made with novel material. The tools used in this work include Sentaurus Structure Editor, Sentaurus Device, Sentaurus Visual, Sentaurus Inspect and Sentaurus Workbench. The details will be discussed in the following sections. 42

64 3.1.2 Device Simulation Flow In a typical device simulation flow, the device structure is created and remeshed by Sentaurus Structure Editor. The resulting file contained all the device configuration information and is sent to Sentaurus Device to simulate the electrical characteristic of the device. Finally, Sentaurus Visual is used to visualize the output from the simulation in 2D and 3D, and Inspect is used to plot the electrical characteristics. The tool flow is demonstrated in Figure 3.1. FIG. 3.1 Typical tool flow with device simulation using Sentaurus Device [112] Sentaurus Structure Editor is a 2-D/3-D device editor which builds and edits device structure using geometric operations. The graphical user interface (GUI) facilitate the visualization of device structure during interactive operation, and it features a commandline window in which script commands corresponding to the GUI operations are displayed. 43

65 The script files use a LISP-like programming language called Scheme, which can be incorporated into Sentaurus Workbench. Sentaurus Device simulates the electrical, thermal, and optical characteristics of semiconductor devices in 2-D and 3-D. It incorporates an extensive set of physical models and material parameters, and supports DC, AC, transient and harmonic balance analysis. Sentaurus Device optional modules allow for flexibility in configuring application-specific solutions, it also has extensive set of models and parameters to support compound semiconductor device development, including spatially varying mole fractions, bulk and surface trapping, etc. To simulate the effect of trapped charge in gate dielectric and at dielectric/semiconductor interface on α-igzo TFT electrical characteristics, traps and fixed charge is included in the physical model of Sentaurus Device. Three types of trap distribution is available: fixed charge traps are always completely occupied; acceptor traps are uncharged when unoccupied and they carry the charge of one electron when fully occupied; donor traps are uncharged when unoccupied and they carry the charge of one hole when fully occupied. In bulk α-igzo, an acceptor trap with exponential energetic distribution is used to represent the tail state below the conduction band minimum, and a donor trap with Gaussian distribution located in the bandgap very close to the conduction band minimum. At the dielectric/igzo interface, an acceptor trap with uniform energetic distribution is used to simulate the electro trap caused by the interface defects. The quasi-stationary ramp is used to ramp a device from one solution to another through modification of its boundary conditions (such as contact voltage) or parameter values. The simulation continues by iterating between the modification of the boundary 44

66 conditions or parameter values, and re-solving the device. For the simulation of α-igzo TFT in this work, drain voltage is ramped with fixed gate voltage to simulate output characteristics and gate voltage is ramped with fixed drain voltage to simulate transfer characteristics. At each step of the gate voltage ramp, the semiconductor is regarded as stationary, which means all physical variables are not changing with time. Poisson s equation is used to relate the variations of electrostatic potential to the electrostatic charges. It can be expressed by εε ϕ + PP = qq(pp nn + NN DD NN AA ) ρρ trap (3.1) Where εε is the electrical permittivity, PP is the ferroelectric polarization, q is the elementary electronic charge, n and p are the electron and hole densities, ND is the concentration of ionized donors, NA is the concentration of ionized acceptors, ρρ trap is the charge density contributed by traps and fixed charges. For the α-igzo used in this work, the relative permittivity εε rr is set to be 9.1. The transport equations using the drift-diffusion model that can be expressed by JJ nn = qqμμ nn nnnn + qqdd nn nn (3.2) JJ pp = qqμμ pp pppp + qqdd pp pp (3.3) Where μμ nn and μμ pp are the electron and hole mobility, DD nn and DD pp are electron and hole diffusivity. The first term on the right hand side represents the drift current and the second term is diffusion current. The μμ pp of α-igzo used in this work is fixed at cm 2 /Vs, while μμ nn is modified to fit the experiment result because its value depends on the trapped 45

67 charge density and varies as a function of gate voltage. The bandgap of 3.0 ev for α-igzo is used for the simulation. After the device simulation, Sentaurus Visual provides users with interactive 1-D, 2-D and 3-D visualization and date exploration environment. It also supports TCL scripting, enabling the postprocessing of output data to generate new curve and extracted parameters. To get the output characteristics (ID-VD) and transfer characteristics (ID-VG) of the TFT, Inspect is used to display and analyze the curves. An Inspect curve is a sequence of points defined by an array of x-coordinates and y-coordinates. An array of coordinates that can be mapped to one of the axes is referred to as a dataset, which usually represents a physical quantity, such as voltage, current, or time. For output characteristics and transfer characteristics, y-coordinate is drain current, and x-coordinates are drain voltage and gate voltage separately. 3.2 Pulsed Laser Deposition The technique of PLD has been used to deposit high quality films of materials for more than decade. It is an extremely simple technique, which uses pulses of laser energy to remove material from the surface of target, and the material is collected on an appropriately placed substrate upon which it condenses and the thin film grows. Figure 3.2 shows the typical schematic of PLD system for thin film deposition. The full PLD process can be described by five stages [113]: (1) Light absorption in the solid. The target absorbs the high energy from the laser light, and atoms as well as ions and electrons are ejected from the solid. For a chemical compound or homogenous multicomponent target the energy absorption is usually similar for all the components due to the high energy. The removal of many layers in the ablation 46

68 process supplies the following stages with a stoichiometric composition of the ejected atoms. (2) Plume expansion. The vaporized materials, containing neutrals, ions, electrons etc., is known as a laser-produced plasma plume and expands rapidly away from the target surface. The material expands parallel to the normal vector of the target surface towards the substrate due to the Coulomb repulsion and recoil from the target surface. The spatial distribution of the plume is dependent on the background pressure inside the PLD chamber. (3) Film growth. The deposition of ejected target material on the substrate can be described by the following sequence: the arriving particles adsorb on the substrate surface and diffuse some distance before they react with each other and the surface and start to nucleate. However, the growth of a film is a very complicated process, chamber pressure, pulsed laser energy and substrate temperature my subsequently modify film composition and film properties. The technique of PLD was found to have significant benefits over other film deposition method: The capability for stoichiometric transfer of material can reproduce the exact chemical composition of a complex material to the deposited film. As the energy source is external laser, laser-target interaction is completely decoupled from other process parameters, thus deposition can occur in both inert and reactive background gases. The atoms and ions in the plasma plume have kinetic energy that may exceed thermal energy by more than two orders of magnitude, which increase the sticking and nucleation rate as well as the surface mobility. 47

69 The particles arriving at the substrate surface can be controlled precisely with the number of pulses, thus the modification of thin film thickness can be achieved by change the number of laser pulses. FIG. 3.2 Schematic of the pulses laser deposition system in NCSU In spite of theses significant advantages, PLD has been confined to research environment due to the following reasons: 1. The plasma plume created during the laser ablation process is highly forward directed, thus the deposition rate is not uniform across the substrate surface. The small deposition area on the substrate cannot meet the requirement of large area coverage for many industrial applications. 2. The ablated material 48

70 contains macroscopic globules of molten material, and the arrival of theses particulates at the substrate deteriorate the properties of thin films. The schematic of the PLD system from NEOCERA Inc. used in this work shown in Figure 3.2 contains the following components: (1) The laser is used as the energy source to ablate the target and create the plasma plume. In this work, a lambda-physic Compex 201 KrF excimer laser with wavelength of 248 nm is used as the energy source. Laser power is typically between 150 and 300 mj per 20 ns pulse, with the rate of 10 Hz during deposition, and the power density at the target surface is estimated to be ~ 3 J/cm 2. The number and rate of pulses can be controlled by the computer software. (2) The vacuum chamber contains the target holders and substrate holders. To obtain better quality uniform for thin film, the target holder and substrate holder are rotating and spinning during deposition and controlled by computer. (3) Pumping system and gas inlet is used to maintain the high vacuum and provide the background gas for deposition. A mechanical pump is used for rough pumping, followed by a turbo pump to reach lower pressure. The chamber pressure is kept around 10-7 Torr and for deposition process, the chamber is only vented and pumped back when target replacement is needed. Substrate is first placed in the loading dock which is connected to the main chamber, and transferred to the vacuum chamber after loading dock is pumped down to low pressure. The chamber background gases can be oxygen or argon and the gas flows are regulated by a MKS mass flow controller. For α-igzo deposition, oxygen is used as the background gases, the partial pressure was controlled using a gate valve. 49

71 (4) Optical system contains the lens, apertures and reflection mirrors which are sued to guide the output laser and focus it on the surface of target. Perfect alignment is needed to achieve laser beam with high enough power for the ablation. The IGZO targets prepared in this work is obtained by mixing high purity In2O3, Ga2O3 and ZnO powers in alcohol. The powers are weighted to give the required chemical quantity composition of I1G1Z5O (In:Ga:Zn=1:1:5). After stirring, the solution was left to dry and grounded to powder using a mortar and pestle. The powder was calcinated at 1000 C for 2 hours. Next the powder was grounded again and pressed to a 1inch ceramic disk with 5000 psi. The disk is sintered at 1400 C for hours in air. For a typical deposition, the target is mounted on the holder carousel, the substrate is placed in loading dock first and transferred into the main chamber with a base pressure of ~ Torr. Before the deposition, the target is pre-cleaned with 500 pulses at 5 Hz followed by another 500 pulses at 10 Hz while the substrate is covered with a shutter. During deposition, the laser pulses are operating at 10 Hz with 160 mj for each pulse, the number of pulses is varied to obtain the desired thin film thickness. The oxygen gas flow is maintained at 20 sccm and the partial pressure is controlled using a gate valve at 25 mtorr. The deposition process was carried out at room temperature without extra heating on the substrate. 3.3 Plasma Enhanced Chemical Vapor Deposition Chemical vapor deposition (CVD) is a chemical process used to produce high quality solid materials. The process is widely used in industry to produce thin films. During the chemical vapor deposition process, the precursor is introduced into a process chamber 50

72 through vapor source and reacted at a certain temperature and pressure. The desired thin film is deposited on to a substrate inside the process chamber. The thickness and composition of the deposited materials can be controlled by the vapor concentration, temperature, and pressure. Plasma enhanced chemical vapor deposition (PECVD) is an excellent alternative for depositing variety of thin films at lower temperature compared with CVD. PECVD uses electrical energy to generate a glow discharge (plasma) in which the energy is transferred into a gas mixture and transform it into reactive excited species such as ions, molecules. These reactive fragments interact with substrate and the deposition process occurs. Since the formation of reactive species occurs by collision in the gas phase, the substrate can be maintained at a low temperature. Besides, PECVD also shows better conformal step coverage on the substrate surface. The main disadvantage of PECVD is limited capacity because the plasma generation requires wafers to lie flat on the bottom stage. In this work, an Oxford Plasmalab 80 Plus PECVD system is utilized to deposit SiO2 for use as a gate dielectric. The substrate was heated to 300 C and the precursor gases include He, N2O and SiH4 (2%)/He (98%) mixed gas. The chemical reaction occurs in the chamber is SSSSSS 4 + NN 2 OO SSSSSS 2 (+HH 2 + OO 2 ) (3.4) 3.4 Electron Beam Evaporation The electron beam evaporation (e-beam evaporation) is a kind of physical vapor deposition (PVD), which is commonly used for the deposition of metals because they can be performed at lower process risk and cheaper than CVD. The electron beam evaporation process typically involves the electron beam evaporation gun, a system controller, power 51

73 supply, crucibles for the evaporation material, materials for evaporation and substrate to be coated. During deposition, a tungsten filament is heated inside the electron beam gun, which located outside the evaporation zone to avoid becoming contaminated by evaporant. The filament begins to emit electrons when becomes hot enough, and these electrons is guided and accelerated toward the material to be evaporated by means of magnetic or electric fields. When the electron beam strikes the target surface, the kinetic energy is transferred to target by the impact into thermal energy (heat), and the target material is vaporized. The resulting vapor can be used to coat surface. A clear advantage of this process is it permits direct transfer of energy to source during heating and very efficient in depositing pure evaporated material to substrate. Electron beam only heats the source material, which avoid the contamination from the crucible. Bu using multiple crucible carousel, several different materials can be deposited without breaking the vacuum. The substrate h older is usually high on top of the crucibles, which leads to a small incident angle. This makes lift off process very easy. Ad for disadvantages, it is harder to improve the step coverage and could cause x-ray damages by the electron beam evaporation. In this work, Edwards AUTO 306 Magnetron Sputtering System is uses as the electron beam evaporation process for the drain and source metal deposition. The chamber pressure is kept to 10-5 to 10-4 Torr and requires liquid nitrogen to prevent oil vapors from contaminating the chamber due to the use of diffusion pump. The voltage for the electron beam acceleration is 5 kv and the metal slugs used for target were purchased from commercial vendor. 52

74 3.5 Thin Film Patterning Photolithography Photolithography is the process of transferring geometric shapes on a mask to the surface of a substrate wafer. It tends to be the technical limiter for further advance in feature size reduction of micro structure in device fabrication. Typically, the photolithography process includes the following steps: (1) Substrate preparation. It is intended to improve the adhesion of the photoresist to the substrate. Substrate cleaning is applied to remove contamination on the surface of substrate, either organic or inorganic particulates. Then dehydration bake is used to remove the water. If the top surface of the substrate is hydrophilic, addition of adhesion promoter is necessary to improve the surface adhesion to photoresist. In this work, the glass substrate was first cleaned in acetone to remove the organic particulates, followed by rinse in methanol to remove the remaining acetone. After blowing the substrate dry with nitrogen gun, the substrate was baked at 115 C for 5 minimums for dehydration. If the SiO2 thin film exist on the surface, the substrates was coated with hexamethyl disilizane (HMDS) before photoresist coating. (2) Photoresist coating. Photoresist is a light-sensitive material used to form a patterned coating on the surface; it generally consists of inactive resin, photoactive compound (PAC), and solvent, which is used to adjust viscosity. Depends on the types of PAC, photoresist can be divided into positive photoresist or negative photoresist. For positive photoresist, unexposed region is removed while for negative photoresist, exposed region is removed. Substrate is held on a spinner chuck by vacuum and resist is coated to uniform thickness by spin coating. The resist thickness is set by viscosity and spinner rotational speed. After 53

75 spinning, soft bake is needed to evaporate the solvent and to densify the resist. In this work, AZ5214E positive photoresist was used, it can also works in image reversal mode for liftoff process. A Laurell spinner was used for coating, and after spinning at 4700 round/min for 50s, the typical thickness of resist is ~1.4 μm. (3) Alignment and exposure. Photomask is placed between the light source and substrate to transfer the patterns on mask to substrate by only allowing the incident light pass through the mask via transparent light-field. PAC is converted to a carboxylic acid on exposure to UV light I the range of nm and can be removed by the aqueous base developer. Each pattern being printed on the substrate is aligned to the previously formed patterns by using alignment marks. In this work, photomask with 4 4 Chrome on quartz glass was purchased from commercial vendor. Karl Suss MJB3 aligner was used, and mercury lamp at 365 nm (I-line) was applied as the UV light source. The exposure power is ~3mW/cm 2. When AZ5214E was used as positive photoresist, the sample was developed after exposure for 90 sec. When working at image reversal mode, another reversal bake was needed after first short exposure, than a flood exposure (without photomask) was applied before developing. (4) Development. Once exposed, the photoresist must be developed. Aqueous bases are used as developers as it can remove the carboxylic acid which is created from PAC after exposure. In this work, the sample was loaded in a small plastic basket and agitated gently while rinsing in the MF310 developer. After development, the sample was rinsed in DI water and flowed dry by nitrogen gun. 54

76 3.5.2 Lift-Off Process Lift-off is a simple and easy way to pattern deposited films which are difficult to dry etch. A pattern is defined on a substrate using photoresist and standard photolithography. A thin film is blanket-deposited all over the substrate, covering both the photoresist and areas in which the photoresist has been cleared. During the lift off, the photoresist under the film is removed with solvent, taking the film with it, and leaving only the film which was deposited directly on the substrate. In this work, AZ5214E was used for the patterning, PLD of IGZO and electron beam evaporation of drain and source metals were applied for thin film deposition. AZ5214E is positive resist which can be used for lift-off process under image reversal mode. Like negative photoresist, AZ5214E provides pronounced undercut which helps to prevent the resist sidewalls from being coated and makes the subsequent lift-off easier. As it is positive photoresist, it does not swell during development as negative photoresist did Etch Process Another way to pattern the deposited film is etching. It is used to remove material from areas identified by the photolithography process. After developing, substrate areas without photoresist covered are removed by the etching. In general, there are two types of etching process: Wet etching where the material is dissolved when immersed in a chemical solution; Dry etching where the material is sputtered or dissolved using reactive ions or a vapor phased etchant. Wet etching is a simple technology, it only requires a container with a liquid solution that will dissolve the material but will not dissolve the mask or at least etches the mask much slower than the material to be patterned. The problem is wet etching is isotropic process which will cause undercutting of the mask layer by the same distance 55

77 as the etch depth. In this work, dry etching was applied which etches almost straight down without undercutting and provides much higher resolution. Reactive ion etching (RIE) is a high resolution mechanism for etching materials. Samples are first masked by one of many patterning processes. They are then placed into a vacuum chamber, Gases are introduced into the chamber and then activated by plasma. A negative DC bias induced by the free electron at the substrate accelerates ions in the plasma perpendicular to the sample surface. This provides a directional physical motivating force to the etch. The plasma source can be either capacitively coupled plasma (CCP) or inductively coupled plasma (ICP). A typical CCP system consists two electrodes, one is grounded, the other one is connected to single radio-frequency (RF) power supply, and the electric field is generated between the two electrodes. For ICP system, the plasma is generated with an RF powered magnetic field, a time-varying electric current is passed through the coil and creates a time-varying magnetic field, which in turn induces azimuthal electric field. In this work, for ITO etching, Plasmatherm batchtop RIE tool was used with BCl3 as the etching gas. Plasmalab 80 Plus ICP system was used to etch the SiO2 film and the etching gases were Ar and CHF Focused Ion Beam Focused ion beam (FIB) system have been produced primarily for large semiconductor manufacturers. FIB system operate in a similar way to a scanning electron microscope (SEM) except, rather than a beam of electrons, FIB system use a finely focused beam of gallium ions that can be operated at low beam currents for imaging or high beam currents for site specific sputtering or milling. FIB system may be stand-alone single beam 56

78 instruments or alternatively, FIB columns can be incorporated into other analytical instruments such as an SEM, TEM, or secondary ion mass spectrometry (SIMS). The most common system is FIB/SEM dual platform instrument as it allows sample preparation, imaging, and analysis to be accomplished in one tool. The ion beam and the electron beam complement each other in charge reduction, protective depositions, and imaging information. Besides, the electron beam can be sued to monitor the ion beam milling to endpoint precisely on the feature of interest. The FIB system used in this work is FEI Quanta 3D FEG DualBeam instrument. The accelerating voltage for electron and ions is 0.5~ 30kV and the SEM resolution can reach 1.2 nm at 30kV, FIB resolution is 7 nm at 30kV. Low current of 10 pa was used for imaging while higher current was used for metal contact milling. More detail about the application of FIB on α-igzo TFT fabrication will be presented in Chapter Experiment Setup of Laser Interference Lithography In this work, a Kimmon He-Cd laser with wavelength of 325 nm was used as the laser source for the laser interference lithography experiment setup. The output power of the laser beam is fixed at 300 mw and the beam is vertically polarized. All the lenses, mirrors and exposure setups were made on optical table. In this work, the p-polarized setups was used for the exposure, which needs a vertical supporting post and two horizontal posts holding the reflecting mirror and the sample stage. A plastic goniometer was sued to adjust the angle of mirror and stage. The stage is made from anodized aluminum that diffuses the incident light so that there is no specular reflection, which will form the vertical standing wave inside the photoresist and degrade the quality of photoresist. As the stage is oblique, in order to hold the sample on the stage, a hard paper with light diffusion coating was stuck 57

79 to the stage by using double sides tape and acts as a stopper. The paper should be thick enough to stop the sample from sliding, but can t be too thick to block part of the incident light and results in smaller exposure area. The normal aluminum mirror was used to reflect the light and both the stage and the mirror can be rotated to adjust the angle. Figure 3.3 (a) illustrate the exposure setup. A Newport 1815-C power meter with 883-UV detector was used in Dr. Escuti s lab to measure the power of the incident light at the mirror and the stage. The laser beam is spreaded so that it can cover both the stage and the mirror. The light directly on the stage interfere with the light reflected from the aluminum mirror and form the pattern on the sample. As the high exposure contrast is needed so that photoresist exists periodically after developing, the powers of the vertical components of the lights directly on stage and reflected from mirror should be identical. To achieve this, power meter was used or a more direct way can be performed just using eyes. A white paper was placed on the sample stage to assist the power adjustment. Light directly on the stage, along with the light reflected from the mirror form a region with higher intensity on the paper. When one light source is blocked, the remaining intensity indicates the power of the other light source. When the incident light is blocked from touching the stage, the remaining less bright region indicates the power of light reflected from the mirror. The intensity of this region should be identical to the intensity of the area where only direct light from the laser is projected on. Figure 3.3 (b) shows the experimental process of adjusting power using paper. 58

80 (a) (b) FIG (a) Laser interference lithography setups for p ploarized light. (b) Demonstratation of pwer adjustment by using paper. 3.8 Device Fabrication The substrate used in this study is polished float glass coated with ITO and purchased from vendor. The nominal ITO coating thickness is 1200 Å ~ 1600 Å. The sheet resistance RS is 8~12 Ω/sq, and the nominal transmittance is >83%. The five-level mask was purchased from vendor. The mask is made by quartz glass, which shows high transmittance (~90%) at the wavelength of 365nm (I-line of mercury lamp) which is used for the photolithography exposure. The pattern is defined by Chrome at the bottom of the glass, thus contact printing is used for the lithography to minimize the diffraction effect and obtain higher resolution. Two layers of masks are used to define the drain and source contact metal. The first layer is for the electron beam evaporation of metal and subsequent 59

81 lift-off process. The second layer is used to etch away the connecting metals between individual device patterns so each device can operate separately. All the IGZO thin film transistors in this study are fabricated using a staggered bottom gate configuration. The coated ITO acts as the bottom gate. First, ITO gate was patterned by photolithography and followed by BCl3 reactive ion etching (RIE) for 40mins at 100W forward power to make sure the dry etch remove all the undesired ITO. A 100nm SiO2 dielectric layer was grown by plasma-enhanced chemical vapor deposition (PECVD) at 300 C. A 40nm thick amorphous IGZO channel layer was formed by pulsed laser deposition (PLD) at room temperature with oxygen partial pressure of 25 mtorr. The IGZO was patterned by two ways: the IGZO deposition was right after SiO2 deposition and followed by photolithography and wet etch with diluted acetic acid, or the IGZO thin film is patterned by a lift-off process. The samples were annealed by either furnace or rapid thermal annealing (RTA). Molybdenum or Titanium was deposited as source and drain contact by electron beam evaporator after photolithography and followed by lift-off. All the metal patterns from individual devices are connected with each by routing metal lines to the edge of the sample intentionally. Before loading the sample into the SEM chamber, the edge of the sample was covered by silver paste, which provide a direct conducting path between the top metal and sample stage, and charging effect was minimized for the SEM picturing. Focused ion beam (FIB) was used to cut a trench at specified region to separate drain and source and channel was formed. SEM was used to locate the milling region and take pictures of cross-section. After FIB milling, the final step is to do the photolithography with the 5 th mask layer and etch away the connections between individual devices by using 60

82 strong acid or BCl3 RIE, thus each device can operate separately. The process flow is demonstrated in Figure 3.4. FIG Process flow of IGZO TFT device fabrication. 3.9 Electrical Characterization of Thin Film Transistors Thin Film Transistor Operation Modes Because both MOSFET and TFTs are field-effect transistors, the simplified algebraic model usually used for MOSFET can be applied for TFT characterization. The drain current equation of field-effect transistor for both the linear and saturation region are mentioned in Chapter 2 and shown below: WW II DDDD = μμ FFFF CC oooo (VV LL GGGG VV tth )VV DDDD VV 2 DDDD for VV 2 DDDD VV GGGG VV TT (3.5) II DDDD = μμ ssssss CC oooo WW 2LL (VV GGGG VV tth ) 2 for VV DDDD > VV GGGG VV TT (3.6) 61

83 However, modern TFTs characteristics are more complex than the algebraic model presented here, and more accurate equation are usually used for better assessment of TFTs [114]: WW II DDDD = μμ FFFF (VV GGGG )CC oooo (VV LL GGGG VV oooo )VV DDDD VV 2 DDDD for VV 2 DDDD VV GGGG VV oooo (3.7) II DDDD = μμ ssssss (VV GGGG )CC oooo WW 2LL (VV GGGG VV oooo ) 2 for VV DDDD VV GGGG VV oooo (3.8) We can notice that the mobility for both linear region and saturation region are modified as field effect mobility, which is always dependent on the VGS for thin film transistor technology. Second, threshold voltage VT is replaced by turn on voltage Von, since VT is an ambiguous definition and it can be extracted in different methods. More details about the mobility, threshold voltage VT and turn on voltage Von will be discussed in the following sections DC Current-Voltage Measurement-Output Characteristics IDS-VDS curve or output characteristics are common characterization to test the electrical performance and quality of fabricated thin film transistor. The curves are obtained by sweeping the VDS at different fixed gate voltage VGS and measuring the drain current IDS. From the curves, the device performances at cutoff, linear and saturation operation regions can be observed. For example, the slope of IDS curve at saturation region indicates how well the channel is depleted for that VGS and gives the clue to the output resistance of the working TFTs. The slope of the curve at linear region provides the information about contact resistance on the other hand. At saturation region, the drain current should increase quadratically with rising gate voltage VGS if mobility is not changing with VGS. The significant deviations from this rule would indicate that the mobility is gate voltage dependent. 62

84 3.9.3 DC Current-Voltage Measurement-Transfer Characteristics An IDS-VGS curve or transfer characteristic is another important characterization to evaluate the switching speed of TFTs. The curve is obtained by sweeping the gate voltage VGS from negative to positive while keeping the drain voltage VDS constant. Several important device parameters such as threshold voltage, turn-on voltage, subthreshold swing, current on/off ratio and field effect mobility can be extracted from these curves. It also provides critical information about the trapped charge at interface or bulk and the quality of the IGZO/dielectric interface. The parameter extractions will be presented in the following sub-sections Subthreshold Voltage Swing and Drain Current on/off Ratio Subthreshold voltage swing S is also called slope factor, which can be extracted from the transfer characteristics and smaller S indicates that the transistor turns on faster from off status. It is defined to be the maximum inverse slope of the log (ID) vs. VGS characteristics in the subthreshold region: S = log(ii 1 DD) VV GGGG max (3.9) It is related to the bulk subgap density of states (DOS) which acts as the electron trap and the trap density at the interface. By definition [115,116], the subthreshold voltage swing is CC 1+ iiii+ccdd CCoooo SS = SS oo 1+ CC DD CCoooo (3.10) and 63

85 CC SS oo = kk BBTT ln10 1+ DD CCoooo (3.11) qq 1 2 aa 2 CC DD CCoooo 2 is the subthreshold swing with no interface traps. kb is the Boltzman s constant, T is the absolute temperature, q is the electric charge, a is a constant, Cox is the oxide trap capacitance, CD is the depletion layer capacitance which include the DOS traps, and Cit is the interface trap capacitance. Drain current on/off ratio is another important criteria that measure the switching performance of TFT. It is the ratio of highest measured drain current at the on status (Ion) over minimum drain current at the off status (Ioff). The off current should be minimized when the device is off in order to reduce the gate leakage current and the leakage power consumption, thus higher on/off ratio is preferred Threshold Voltage and Turn-On Voltage The threshold voltage (VT) is a fundamental parameter for MOSFET modeling and characterization. It is defined as the gate voltage value at which the strong inversion layer is formed in the channel. For TFTs, threshold voltage represents the gate voltage at which the accumulation takes place in the TFT channel. The method to extract this parameter from the electrical characteristics in MOSFET can also be applied to TFTs. However, it is an ambiguous parameter as there exists numerous methods to extract the value of threshold voltage. Most of the procedures available to determine VT are based on the measurement of the transfer characteristics (IDS-VGS) of a single transistor. Most of these ID-Vg methods use the strong inversion region. Extraction is mostly done at low drain voltages so that the device operates in the linear region. Extrapolation in the liner region method (ELR) is perhaps the most popular threshold-voltage extraction method. It consists of finding the 64

86 gate-voltage axis intercept (i.e, ID=0) of the linear extrapolation of the IDS-VGS curve at its maximum first derivative (slope) point. As illustrated in Figure 3.5 (a) [117], the presented device shows the threshold voltage of 0.51 V. Another commonly used method the transconductance extrapolation method in the linear region (GMLE) which suggests that the threshold voltage corresponds to the gate voltage axis intercept of the linear extrapolation of the gm-vg characteristics at its maximum first derivative (slope) point. Figure 3.5 (b) [117] presents the application of this method to the same device and shows the VT of only 0.44 V. Besides, VT extraction with the device operating in saturation is also frequently carried out [118, 119]. It is obvious that different methods extract different VT for the same device. Besides, amorphous and polycrystalline thin film transistors (TFTs) introduce the additional difficulty in the VT extraction that the saturation drain current is usually modeled by a power law with an exponent which can differ from 2 [120]. Thus extracting the VT using traditional methods will generally produce values of VT that are unacceptable or at least not very accurate. (a) (b) FIG. 3.5 (a) ELR method and (b) GMLE method implemented on the I D-V g characteristics of the same device measured at V DS = 10 mv. 65

87 To eliminate the confusion of threshold voltage definition, another parameter, the turnon voltage, VON, has been used to evaluate the switching behavior of TFTs. VON can be extracted from the transfer characteristics with the drain current shown in logarithmic scale. It is defined as the gate voltage at which abrupt increase in drain current happens, this corresponds to the condition that applied gate voltage is large enough to accumulate considerable number of mobile carrier presented in the channel. It is much easier to extract from the transfer characteristics and is more commonly used for the bias stress test to analyze the turn-on voltage shift Mobility Extraction Channel mobility is obviously the most important electrical parameter to evaluate TFT performance. It characterize how quickly the carrier can move through the channel between drain and source of the TFT, when puled by the voltage VDS. It defines the drain current level of the single device and determines the driving ability in large scale circuit. Large carrier mobility is preferred as higher current leads to higher operation speed and lower supplying voltage, which can save more power. It also determines other important parameters of TFT such as drain current on/off ratio and subthreshold voltage swing. Similar to VTH extraction, the mobility is also a subjective parameter in terms of its definition. First, it is an estimation of average carrier mobility all over the channel and it is not accurate enough when many complicated mechanisms are considered for the conduction, such as different scatterings, interface traps, carrier ionization, and nonuniform carrier distribution caused by the field effect. Second, there exist variety of methods to extract the channel mobility, and each of them gives different result because different model and approximation is applied. 66

88 Therefore, the following sections will introduce five types of channel mobilities and the applicable conditions for each one. The most commonly encountered technique for determining the channel mobility used from MOSFET drain current equations are effective mobility, μeff, field-effect mobility, μfe, which are both extracted from linear region, and the saturation mobility, μsat, which is extracted from the saturation region. Mobility extraction methodologies based on idealized MOSFET and TFT models are not, in general, appropriate for devices that deviate significantly from these models. To avoid ambiguity often present in mobility values of TFT reported in literature, Hoffman introduced two new mobility metrics, average mobility, μμ aaaaaa, and incremental mobility, μμ iiiiii, so as to produce result that are both physically meaningful and quantitatively representative of nonideal TFT device performance [121] μμ eeeeee, μμ FFFF, and μμ ssssss At the triode region of TFT operation, the drain current equation is given by Eq. (3.5). In the linear region where VDS is very small, it can be expressed as, II DDDD μμμμ oooo WW LL [(VV GGGG VV tth )VV DDDD ] (3.12) Differentiating Eq. (3.12) with respect to VDS and VGS yields the channel conductance, gd, and the transconductance, gm, respectively, gg dd = II DD VV DDDD = μμcc oooo WW LL (VV GGGG VV tth ) (3.13) gg mm = II DD VV GGGG = μμcc oooo WW LL VV DDDD (3.14) The effective mobility, μμ eeeeee and the field effect mobility, μμ FFFF, can be extracted separately, 67

89 μμ eeeeee = gg dd WW CC oooo LL (VV GGGG VV tth ) (3.15) μμ FFFF = gg mm CC oooo WW LL VV DDDD (3.16) It is obvious from Eq.(3.15) that μμ eeeeee is dependent on VGS and Vth. Both thermal broadening and trapping tend to obscure the accurate measurements of Vth and, therefore, μμ eeeeee.the discrepancy between the effective and field-effect mobility is associated with the neglect of the gate voltage dependence in the derivation ofμμ FFFF. The experimentally measured field-effect mobility is usually smaller than the effective mobility, therefore, if μμ FFFF is used for device modeling, the current and device switching speeds are going to be underestimated. In saturation region where VDS > VGS, the drain current is given by Eq.(3.6). Very rarely, the saturation mobility μμ ssssss is used from Eq.(3.6) with device in saturation region. μμ ssssss is extracted by taking the square root of Eq.(3.6) and differentiating with respect of VGS, and given by, μμ ssssss = dd II DD ddvv GGGG 1 WW CC oooo 2LL 2 (3.17) Again, due to the neglect of the gate-voltage dependence in the definition for the saturation mobility, the experimental result for μμ ssssss are always smaller compared to the ones obtained for μμ eeeeee. 68

90 μμ aaaaaa and μμ iiiiii Average mobility μμ aaaaaa is based on applying VDS without unnecessarily sacrificing measurement precision. The use of a small VDS enables the assumption that the channel charge density is substantially uniform across the length of the channel, corresponding to drift-dominated current flow. The channel conductance can be expressed as, GG CCCC (VV GGGG ) = lim VV DDDD 0 II DD VV DDDD VV GGGG = μμ aaaaaa (VV GGGG ) WW LL QQ iiiiii(vv GGGG ) (3.18) where Qind is the cumulative charge per unit area induced in the channel by the applied gate voltage in excess of Von and μμ aaaaaa is the average mobility. Qind includes contributions from one or more of the following: free electrons, midgap bulk states, and interface states. It is most accurately achieved by measuring the channel capacitance CCH as a function of VGS, however, the channel capacitance is likely to be quite complex due to the diverse composition of induced channel charge and the probable range of carrier mobility. To make the Qind the extraction more straightforward, the induced charge is assumed to exist exactly at the channel/gate insulator interface, the charge induced by the gate voltage in excess of Von is given by, QQ iiiiii (VV GGGG ) = CC oooo [VV GGGG VV oooo ] (3.19) and μμ aaaaaa can be derived by combining Eq.(3.18) and Eq.(3.19), μμ aaaaaa (VV GGGG ) = GG CCCC (VV GGSS ) WW LL CC iiiiii (VV GGGG VV oooo ) (3.20) This expression is nearly identical to commonly used effective mobility μμ eeeeee. The primary difference is the use of Von instead of VT, which we have discussed already. 69

91 The second measured quantity of potential use in evaluating channel mobility. First, the differential channel conductance can be obtained as, GG CCCC (VV GGGG ) = ΔGG CCCC (3.21) ΔVV GGGG The incremental channel charge QQ iiiiii induced by an incremental increase in gate voltage VV GGGG can be defined as, QQ iiiiii (VV GGGG ) = CC iiiiii VV GGGG (3.22) Using these quantities, an expression can be written for the differential channel conductance, GG CCCC (VV GGGG ) = μμ iiiiii (VV GGGG ) WW LL QQ iiiiii(vv GGGG ) (3.23) Equation (3.21), (3.22), (3.23) can now be combined to yield an expression for μμ iiiiii μμ iiiiii (VV GGGG ) = GG CCCC (VV GGGG ) WW LL CC iiiiii (3.24) Average mobility μμ aaaaaa is more reflective of the conventional intentions of mobility extraction and more accurately represents device performance, μμ iiiiii provides more valuable insights into channel carrier transport as it probes the mobility of carriers as they are incrementally added to the channel charge reservoir. 70

92 CHAPTER 4 MODELING AND SIMULATION OF IGZO TFT Though α-igzo also exhibits superior electrical characteristics compared to hydrogenated amorphous silicon[122], which is the present-day dominant TFT technology for large-area applications[123], like other TFTs, the characteristic variations of α-igzo, such as the change of threshold voltage (Vth), occur even at short timing bias stress, and those variations limit the application of α-igzo TFTs. In order to make α-igzo TFTs more reliable and affordable, understanding the mechanism of bias-induced threshold voltage shift is important. In previous works[124], the bias-induced instability and the consequent Vth shift of α-igzo TFT has been attributed to the negative charge trapping at the semiconductor/dielectric interface. Positive Vth shift without the change in subthreshold slope (SS) and a curve fitting for a stress time-evolution of Vth shift with the logarithmic or stretched-exponential time dependence are regarded as firm evidence for this point of view [125, 126]. However, very limited work has been reported on how the trapped charge changes with varying bias voltage and other factors that may influence the trapped charge density. We combined the model of subgap density-of-state and interface or bulk trapped charge density to simulate the electrical characteristics of both normal long channel TFT and short channel TFT etched by focused ion beam (FIB). 4.1 Sample Preparation All α-igzo TFTs used in this chapter were fabricated by Luo [127]. The conventional devices with long channel were fabricated on a heavily doped p + -type silicon substrate with 100nm of thermally grown SiO2, the silicon substrate was used as the bottom gate. About 71

93 40nm of IGZO was deposited by PLD as a channel layer (In: Ga: Zn = 1: 1: 5 atom ratio) with oxygen partial pressure of 25mT at room temperature. A 120nm Ti contact layer was formed by lift off after E-beam evaporation. For devices with short channel, FIB milling was used to define drain and source, and the detail will be presented in section Simulation Model for α-igzo The simulation includes the subgap density-of-states (DOSs) [ ], which plays important role in amorphous semiconductor TFTs. Unlike crystal semiconductor, the random disorders in structure of amorphous semiconductor can capture and scatter electrons, which lead to localized wave function. Such phenomenon can be approximately presented as localized tail states within the band gap, near the conduction band edges [ ]. In α-igzo, the conduction band-tail states (gcba) originate from the disorder of metal ion s-bands, which reduce the overlap of electron orbitals between adjacent metal ions. Because the hole mobility of α-igzo is much lower than electron mobility, hole current is neglected in this simulation work. For simplicity, the deep-gap states were not considered either because of its low state concentration [134]. The conduction band-tail states of α- IGZO are represented as a function of energy (E) by the following expressions: gcba = gtaexp[(e-ec)/ea] (1) where EC is conduction band edge energies, gta is density of acceptor-like states at E=EC and Ea is characteristic slopes of conduction band-tail states. The gta is mainly determined by oxygen partial pressure during α-igzo deposition, which define the density of oxygen vacancy. Lower oxygen pressure induces more oxygen vacancies (OV) and disorder into 72

94 the structure, which results in higher conduction band-tail states. For the 25mTorr oxygen partial pressure used during IGZO deposition in this work, gta= cm -3 ev -1 is used, which is close to the value of gta = cm -3 ev -1 for IGZO films deposited by PLD at 39mTorr (5.2Pa)[135]. A much higher gta ( cm -3 ev -1 ) was used when much lower oxygen partial pressure 3.75mTorr (0.5 Pa) was applied [131]. The carrier density of the IGZO thin film used in simulation is cm -3, which is close to the value obtained at 25mTorr oxygen partial pressure during PLD process demonstrated by Suresh [136]. Besides active carriers, a Gaussian distributed donorlike state also contribute extra conducting carrier due to band bending caused by the gate bias stress[137], ggd = gdexp[-(e-(e 2 /- 2 ] (2) where gd, ere g-lso contribute extra conducting carrier due to band bending caused by the gate bias ucting trated by ail states. For the 25mTorr oxygen partial pressure used during IGZO deposition in this work, gcalized wave function. Sstate [138]. When gate is positive biased, all donor state is neutral because the Fermi level is above donor states in the conducting channel near IGZO/SiO2 interface. However, when negative gate bias is applied, the energy band of IGZO is bending upward at IGZO/SiO2 interface, which moves the Fermi level towards the donor states. The positively charge donor states provide additional carriers for the conduction of α-igzo TFT. Kamiya et al. reported that the donor states of α-igzo are~0.11 ev below the conduction band minimum [139], and λ and m is used in 73

95 this simulation cm -3 ev -1 and 0.03eV are applied for gd and 0.03eV are applied for g4.8 10evel towards the donor state and 0 DOS model is illustrated in Figure 4.1. FIG (Color online) Proposed DOS model for α-igzo. 4. E C and E V are conduction and valence band edge energies, respectively. Solid curves within the bandgap represent the exponentially distributed band-tail states (g CBa), while the dash curve near the conduction band edge represents the Gaussian-distributed donorlike OV states (g Gd). 4.3 Simulation for α-igzo TFTs with Long Channel The TCAD in this work used for device simulation is Synopsys Sentaurus Workbench. The long channel TFTs structure is illustrated in Figure 4.2(a). The thicknesses for each layer are same as the device fabricated and mentioned before. Figure 4.2(a) is the crosssection view of the TFTs and the width of the device is 100 µm. 74

96 (a) (b) FIG (a) Cross-section of the α-igzo TFT structure for simulation and (b) output characteristics (W/L = 100/20 µm). Both experimental (triangle) and simulation data (solid line) are shown Trapped Charge Density Extracted from Output Characteristics of α-igzo TFTs with Long Channel In previous reports, carrier trapping at channel/dielectric interface was identified as a main mechanism for the shift in Vth [125, 136, 137]. Applying a gate bias stress to TFT was found to induce a parallel threshold voltage shift. Trapped electrons result in a positive shift of Vth, and a negative shift of saturation region because the trapped non-conducting electrons make the pinch-off happens at lower drain voltage. In order to fit the measured output result, proper parameter for subgap density-of-states as mentioned before and different trapped electron density for varying gate bias were included, and Figure 4.2(b) shows the measured output [drain current (IDS) versus drain-source voltage (VDS)] characteristics of α-igzo TFTs compared with the model obtained from TCAD simulation. The trapped electron density at IGZO/SiO2 interface extracted form simulation at varying 75

97 gate voltage (3V-15V) is shown in Figure 4.3(a). The trapped charge density increase with the rising gate voltage because higher gate voltage induce more electrons accumulated and trapped at the interface. The trapped charge density keeps on increasing until all the trap states are occupied. For each Id-Vd measurement with fixed gate voltage, the constant mobility is applied for the whole α-igzo thin film. However, the extracted mobility from the Id-Vd curve as seen in Figure 4.3(b) shows a decreasing constant mobility with increasing gate voltage. The possible reason is that higher trapped electron density leads to more mobility degradation due to Coulomb scattering. The conducting channel is close to the IGZO/SiO2 interface and trapped electrons reduce the mobility of passing electrons by Coulomb forces. (a) (b) FIG (a) Trapped charge density at IGZO/SiO 2 interface and (b) constant mobility as a function of gate bias voltage, extracted from the simulated output characteristics shown in Fig. 3(b). 76

98 4.3.2 Transfer Characteristics Simulation Result of α-igzo TFTs with Long Channel To investigate how the interface trapped electron shift the threshold voltage, the transfer characteristics with both forward gate bias sweeping (-5V to 20V) and backward gate bias sweeping (20V to -0.5V) are measured. The TCAD simulation applies different trapped electron densities and constant mobilities for every 1V step of gate bias sweeping. For the forward gate bias sweeping, the interface trapped electron density and corresponding mobility are based on the result from the output characteristics of Figure 4.3. The output characteristics only includes curves at five different gate voltages, and linear prediction of mobilities was applied at every point based on the results at five given gate voltages. For the backward gate bias sweeping, the varying of interface trapped electron density with decreasing gate bias is extracted from the measurement result. Figure 4.4(a) shows the compare of measurement and simulated results. The subthreshold swing (SS) obtained from the measurement is 200mV/decades, the current on/off ratio is over and a 1V positive shift of threshold voltage is observed after round gate bias sweeping. It also shows that the subthreshold slope does not change during forward and backward bias sweeping. This indicates that no additional defect states at the interface after the device was stressed [125]. During the gate bias sweeping, the equilibrium exists between electron trapping and de-trapping processes. As the Fermi energy is more close to the conduction band than to the center of electron trap state, the relaxation time of electron de-trapping process is longer than that of electron trapping process, this can be verified from Figure 4.4(b) that at the beginning of backward gate bias sweeping (20V to 15V), the density of 77

99 induced mobile electron at interface drops, however the trapped charged density still increase. The arrow in the figure indicates the direction of gate bias changing. (a) (b) FIG (a) α-igzo TFT transfer characteristics (W/L = 100/20 µm). Both experimental (circle) and simulation data (solid line) are shown. (b) Trapped charge density at interface as a function of gate voltage for both forward and backward bias sweeping. Arrows indicate the sweeping directions. We also notice that below 15V during the backward gate bias sweeping, trapped charge first drops and then increase again. The possible reason is that the trapped electron density at interface is controlled by two factors: induced electron density by gate bias and activated electrons from donor state near the conduction band minimum. The two processes compete with each other and the dominating one determines whether the overall trapped charge density rises or drops. From 15V to 2V during backward gate bias sweeping, the density of induced electron at conduction band is reducing while trapped charge density is still much higher than equilibrium, the electron de-trapping from the trap is dominating the process. From 2V to 0V, the bump in trapped charge density curve indicates that when the Fermi level decreases close to the donor state due to the falling induced electron density, 78

100 donor state ionization initiates and more electrons are contributed to the conduction band, and then be captured by the trap again. In this case, the donor ionization is dominating the dynamic process. This can be verified from Figure 4.8(a) and (b). The gap between electron quasi Fermi energy and conduction band minimum EC-Efermi at Vgs=2V is 0.251eV, which is less than half of the gap of 0.55eV at Vgs=0V. The center of donor state locates at 0.1eV below the conduction band, which means when Vgs=0V, the Fermi level is 0.45eV below the donor state and more electrons are ionized. When the gate bias falls below 0V, electrons are pushed away from the interface, and Figure 4.10 (b) shows that the curve of ionized donor density-of-state is very close to the donor trap density-of-state, which means at Vgs=-0.5V, almost all the donor states have been ionized and further decreasing the gate voltage toward negative direction cannot compensate the loss of trapped electron anymore. That is why the trapped electron density drops again when negative gate voltage is applied. (a) (b) FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO 2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at V gs=-4v at forward gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. 79

101 (a) (b) FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO 2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at V gs=20v at forward gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. (a) (b) FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO 2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at V gs=15v at reverse gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. 80

102 (a) (b) FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO 2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at V gs=2v at reverse gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. (a) (b) FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO 2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at V gs=0v at reverse gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. 81

103 (a) (b) FIG (a) Band diagram of α-igzo TFT at the IGZO/SiO 2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at V gs=-0.5v at reverse gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. 4.4 Simulation of α-igzo TFTs with Short Channel Milled by Focused Ion Beam (FIB) Sample Preparation of TFTs with Short Channel Milled by FIB To fabricate short channel TFTs, UV lithography or electron beam lithography are the most commonly used photolithography techniques, which require expensive and complicated optical facilities. Etching by using Focused Ion Beam is a much simpler way to get short channel. The device with short channel fabricated by Luo [127] used the same process steps, except that the drain and source Ti contacts were connected as one piece before FIB etching. An FEI Quanta 3D FEG with live SEM imaging and FIB milling dual beam system was used in this work. Focused Ga+ ion beam milled a narrow gap between the source and drain to define the channel length. The acceleration voltage of 30KeV and 82

104 beam current of 30pA were applied during the milling. The IGZO active layer underneath the Ti contact is 10µm 4µm and wider than the Ti contact width which is 4 µm. The depths and width of the milled trench can be controlled with careful beam adjustment. In this work, the beam etched away both the IGZO and SiO2, and the actual gap (channel length) of TFTs is 80nm. There is still IGZO side channel on each lateral sides. As the FIB milling introduces Ga ion into the SiO2 dielectric, the trapped holes in SiO2 are included in the simulation, combing with the subgap density-of-states model to simulate the device characteristics and compare the simulation result with experiment data. The details are discussed in the following section Simulation Model and Result for α-igzo TFTs with Short Channel Milled by FIB The output characteristics from both measured data and simulation of the short channel α-igzo TFT milled by FIG in this work are compared in Figure 4.11(a). As the Ga + ion beam was milling the device through into the p-si substrate and a positive stress was applied on gate voltage during the measurement of output characteristics, several different mechanics might occur in this process as shown in Figure 4.11(b): 1 indicates that fast incident Ga + ions generate a large number of electron-hole pairs in both SiO2 and p-si substrate. After this ion is stopped, it can capture an excited free electron and become neutral. Only mobile holes are left in valence band and the substrate and SiO2 show electropositivity [142]. The generated hole near the SiO2/substrate gain so large energy from Ga + that it can tunnel into the SiO2 film surpass the hole barrier as shown by process 2. This process can be either Fowler Nordheim tunneling or trap-assisted tunneling (TAT).The mobile holes generated by Ga + irritation or Fowler Nordheim tunneling were 83

105 pushed away from the SiO2/substrate interface by positive gate bias, which is indicated by 3. The rest holes in shallow traps of SiO2 by TAT might also move towards the SiO2/IGZO interface through hopping conduction 4, but with a much lower speed, depending on the trap density in SiO2. More and more holes, both mobile or trapped, are moving towards the SiO2/IGZO interface by positive gate bias, and some of them will be trapped by deep hole trap centers at the interface as shown in 5, the other mobile hole either stay SiO2 or escape into IGZO thin film. Process 3 is of great importance for device electrical characterization because it effects the density of accumulated electrons in IGZO channel. The electrons in channel region is induced by two components: the free charge at the SiO2/substrate (gate) interface, and the holes inside SiO2 or at SiO2/IGZO interface. Holes in SiO2 tend to move toward to or be trapped in the location closer to IGZO at higher gate positive bias, which means the thickness of equivalent capacitor formed by Ga + induced holes is reduced, and more electrons in IGZO are induced, even though the total number of holes in SiO2 almost remains unchanged. To approve this, the sample was annealed in air at 350 C for 30 min after fabrication and FIB milling, to remove the Ga + ions residual are on the surface of the gap surface, which results in high leakage current. The annealing also reduced the electron trap density at SiO2/IGZO interface. However, the annealing temperature is not high enough to dramatically remove the hole trap in SiO2. Hoe trapping is reduced by short anneals in an O2 ambient at 1000 C with optimal time of 100s [143]. That means the dominating trapped charge is the hole trapped at SiO2/IGZO interface on the SiO2 side, rather then the electron trap at SiO2/IGZO on the IGZO side. 84

106 (a) (b) FIG (a) Output characteristics of short channel α-igzo TFT by FIB milling, both experimental (triangle) and simulation data (solid line) are shown. (b) The transport of Ga + induced mobile hole at positive gate bias. To simulate the hole moving inside SiO2 while increasing the gate bias, we simplify the complex hole distribution and make a positive charge density with 2D Gaussian distribution which only exits at a transverse plane in the SiO2 as shown in Figure 4.12(a). The variance along the length (σx) and along the width (σy) to be half of the gap length (40nm) and half of the gap width (2.5 µm) separately, and the peak area density is cm -2. As the electron trap density is small compared with hole density in SiO2, we assume the value to be cm -2 and does not change with gate bias. To fit the output characteristics of this short channel TFT at varying gate biases, the location of the transverse plane of trapped hole is adjusting along the vertical direction. The extracted location curve is shown in Figure 4.12(b), the location of 0 µm and 0.1 µm refer to the SiO2/substrate interface and SiO2/IGZO interface separately. At gate voltage (Vgs) = 0V, most holes locate near SiO2/substrate interface because the tunneling process. As gate bias increases, the center of holes are moving to the SiO2/IGZO interface. This explains that 85

107 compared with normal IGZO TFTs without FIB milling, this short channel TFT shows larger linear region from output characteristics measurement, because the pinch-off is hard to achieve due to the exist of trapped hole in dielectric. We also notice that the extracted mobility is only ~4 cm 2 /V s, the possible reason is the damage to IGZO structure during FIB milling. (a) (b) FIG (a) Demonstration of hole transport in SiO 2. (b) The location of transvers plane with equivalent positive charge distribution as a function of gate bias. 0 µm and 0.1 µm refer to the SiO 2/substrate interface and SiO 2/IGZO interface separately. 4.5 Conclusions In this chapter, the simulations for both long channel α-igzo TFTs and short channel device milled by FIB were applied and compared with the experimental results. The sample was fabricated with p-type silicon substrate, thermally grown SiO2, IGZO thin film by PLD and Ti contact by electron beam evaporation. To obtain a good fit with the measured results, the subgap density-of-states, including both the exponentially distributed band-tail states 86

108 (gcba) and the Gaussian-distributed donorlike OV states (ggd) are necessary for the simulation model. Based on this, the changing tendency for density of trapped charge at IGZO/SiO2 interface and IGZO mobility were extracted, and it indicates that the trapping, de-trapping of the interface states and donor state ionization all contribute to the variation of trapped charge density during the dul-sweep of gate bias. For short channel TFTs milled by FIB, besides the interface trapped charge, the Ga ions implanted and diffused into the SiO2 dielectric after annealing also affect the mobile electron density at interface. Many mechanisms happen inside the SiO2, and these trapped positive ions cause the device to be pinched off at lower drain voltage with fixed gate bias. Furthermore, the milling also damaged the IGZO, and the mobility of shot channel device is much lower compared with that of normal channel IGZO TFTs. 87

109 CHAPTER 5 SHORT CHANNEL α-igzo THIN FILM TRANSISTOR FABRICATED BY FOCUSED ION BEAM To fabricate device with short channel length (<1 μm), the conventional way is using electron beam lithography, which is slow and very expensive. In this chapter, a new method to fabricate α-igzo TFT with short channel using focused ion beam (FIB) was proposed. It is photoresist free, fast and can be processed under room temperature, which is beneficial to fabricate small flexible electronics or transparent electronics. In the following session, the basic principle and milling result of FIB will be given in section 5.1. TFTs with one-side-channel and two-sides-channel by FIB and their characterizations are presented in section 5.2 and section 5.3 respectively. Section 5.4 demonstrate the direct-channel TFTs by more refined control of milling ion beam and its better performance compared with side-channel TFTs. 5.1 Focused Ion Beam (FIB) milling FIB Introduction The focused ion beam (FIB) microscope has been widely used in fundamental materials studies and device process technology over the last several years because it offers both high-resolution imaging and flexible micromachining in a single platform. It is similar to scanning electron microscope (SEM), except that the beam that is rastered over the sample surface is ion beam rather than electron beam. Secondary electrons are generated by the interaction of the accelerated ion with the sample surface and can be gathered to obtain high-resolution images. In most commercially available systems, Ga ions are used as the ion source and it is the liquid-metal ion source (LMIS). Ga has the advantages over other LMIS because of its combination of low melting temperature, low volatility, and low vapor 88

110 pressure. It is sued to locally remove or mill away materials. In conjunction with the gasinjection capabilities on the systems, which enable ion-beam-activated deposition, a variety of device fabrication and modification process are possible. The basic FIB instrument consists of a vacuum system and chamber, a liquid metal ions source, an ion column, a sample stage, detectors, gas delivery system. To get nondestructive imaging of the sample during ion beam milling, SEM is integrated to make a dual-beam system. It allows sample preparation, imaging, and analysis to be accomplished in one tool. An FEI Quanta 3D FEG dual beam system from Analytical Instrumentation Facility (AIF) of NCSU is used in this study, as shown in Figure 5.1 (a). The typical dualbeam configuration is vertical electron column with a tilted ion column. When used in ion milling mode, the sample stage is tilted to 52 degree for milling normal to the sample surface, and SEM column is used to observe the cross-section of the milled structure. The ability to mill the material depends critically on the nature of the ion beam-solid interactions. When the ion beam strikes the sample surface, many species are generated, including sputtered atoms and molecules, secondary electrons and secondary ions. Sputtering occurs as the result of a series of elastic collisions where momentum of accelerated ions is transferred to the target atoms within a collision cascade region, and causes the material milling. This process is demonstrated in Figure 5.2 (a). Secondary electrons and ions are used to image the sample. The profile of milled trench is not perfect rectangle shape. The ion beam after focus by lens exhibit a Gaussian distribution, as indicated by Figure 5.2 (b). The shape depends on the ion beam energy, current and scanning strategies. 89

111 (a) (b) FIG (a) FEI Quanta 3D FEG dual beam system from Analytical Instrumentation Facility (AIF) of NCSU (b) Configuration of dual-beam column for ion milling [144]. (a) (b) FIG (a) Schematic diagram illustrating some of the possible ion beam-material interactions [122]. (b) SEM images of the end-edge view of a single pixel width line scan and the trench crosssection profile fitting with a Gaussian function [145]. 90

112 The side effect of the ion beam milling is that the Ga ions can be implanted deep into the thin film under the material to be etched, and diffused further when the sample is annealed. This will make the implanted layer conductive and results in undesired effect. Details about this side effect will be given in the following sections The Objective of Using FIB As presented at the beginning of this chapter, the advantage of using FIB to fabricated small feature structures is photoresist free, fast and can be processed under room temperature. In addition, another important benefit is that the quantity of material removed by ion beam can be controlled, which gives great flexibility to modify the length, width and thickness of the thin film transistor channels. This is demonstrated in Figure 5.3. The channel is formed by removing the metal layer and exposing the IGZO channel active layer and Figure 5.3 (a) and (b) shows channels with different length, which is controlled by the ion beam scanning distance. Figure 5.3 (c) shows the TFTs with thinner channel thickness, which can be achieved by longer ion beam milling time to remove more IGZO. The deposition crate thin film with almost uniform thickness all over the sample, while the FIB milling provides a convenient method to modify the effective channel thickness. This facilitates the circuit design, which always requires different W/L ratios, β ratios and threshold voltages for transistors and logic gates to fulfill the desired performance and functions. Combing with Pt deposition, other e modifications such as circuit re-routing or contact repair are also available. 91

113 (a) (b) (c) FIG.5.3. Devices with different channel dimensions: (a) and (b) shows channels with different length, and (c) presents channel with thinner thickness Multi-layer Thin Film Milled by FIB In this study, FIB was used to mill the material and modify the device structure. Good control of the ion beam is necessary, because the device we fabricated has multiple layers and the milling rate for different materials varies a lot. Besides, the dimension of milled trench is also critical as it determines the performance of the device. For a typical FIB, the milling profiles depend on the following major parameters: 1) Beam energy. Ga ions with higher energy mill the material faster, but results in deep damage to the surrounding layers. It is determined by the acceleration voltage. 2) Beam current. Higher beam current leads to larger milling spot size. Trench with smaller dimensions requires low beam current, but longer milling time. 92

114 3) Dwell time. It is the period of time the beam stays at a particular position. It is recommended to use longer dwell times for small structure, but too long dwell time will reduce the number of cycles passed through one location, which enhance the redeposition of sputtered materials. 4) Overlap. It is defined as the area overlapped when the beam moves from on position to the next and is calculated in terms of percentage of area. Large overlap will guarantee the continuous etching for clean milling, but increase the process time. In this study, the milling conditions of dwell time of 1 μs and overlap of 50% were used for simple ion milling. Different beam energy and current were examined to compare the profile of milled trench as shown in Figure 5.4. (a) (b) FIG.5.4. The cross-section view of etched trench by FIB with ion beam energy and current of 16keV, 11pA (a) and 30keV, 30pA (b). 93

115 The layers from top to bottom are 180 nm Titanium, 100nm α-igzo, 100nm SiO2, 130nm ITO, and the substrate is glass. The filling material is Platinum, which was deposited to prevent the re-sputtering in the trench during cross-section cutting. It is obvious that the ion beam with lower energy (16keV) and lower current (11pA) exhibit more vertical side wall of the trench, which is preferred in this study. Low current created smaller milling spot size and more uniform milling rate, and lower energy result in minor damage and implantation to the underlying thin film layers. However, if the ion beam energy and current is too small, it takes much longer time to remove desired volume of material. The depth of milled trench is determined by the milling time, which is represented by the parameter of z depth in the FIB controlling software. It sets the desired milling depth with silicon as the benchmark. For other materials to be milled, adjustment is needed to obtain the right milling depth. FIG.5.5. (a) Plain view of the milled trench with different parameter z depth. From left to right: z=180nm, 100nm, 150nm, 120nm. The cross-section views are shown in right as (b) for z=180nm, (c) for z=100nm, (d) for z=150nm and (e) for z=120nm. The ion beam energy and current are 30keV and 10pA. 94

116 Figure 5.5 shows that millings with different z depth parameters will result in the etching stopped at different thin film layers. The deepest milling (z=180nm) reveals the first layer of ITO as shown in Figure 5.5 (b), and the shallow milling (z=100nm) did not even etch through the first Ti layer (Figure 5.5 (c)). For z=150nm and z=120nm, the milling stopped at SiO2 layer and IGZO layer separately. The optimum z depth parameter is necessary to obtain the desired milling depth. For the rest of this study, ion beam with 16keV and 11pA are applied to achieve both good control of milling profile and reasonable milling time Device Modification by FIB Milling The substrate used for device fabrication in this study is 1.1 mm polished float glass with 120nm~160nm coating ITO. The sheet resistance RS is 8~12 Ω/sq. The ITO was patterned by BCl3 RIE to form gate. A 100nm SiO2 was deposited by PECVD as dielectric layer. 40nm or 100nm of IGZO was deposited by pulsed laser deposition (PLD) for active layer (In: Ga: Zn = 1:1:5). The deposition was applied in room temperature with oxygen partial pressure of 25mTorr. Either lift-off or wet etching by diluted acetic acid (acetic acid: DI water = 1:4 w.t.) were used to pattern the IGZO active layer. A 150nm Ti layer was deposited by E-beam evaporation and patterned by conventional photolithography. The source/drain terminals were intentionally connected before FIB milling and the patterned was designed that each single device were connected the surrounding metal routing line, which extended to the edge of the sample. Because the substrate is non-conductive and the charging effect will cause abnormal contrast, image deformation and shift. To resolve this issue, before loading the sample to FIB, the conductive silver paste was glued to the edge of the sample, which was covered by Ti metal. Thus there was direct connection between 95

117 conducting sample stage and every devices on the sample, which provide the path for the release of build-up electrons and reduce charging effect. An FEI Quanta 3D FEG SEM-FIM dual system was used for the next step to modify the device. Ga ion beam was used to mill a narrow trench and separate the source and drain terminals. Different milling depth was performed to give two types of channel: ion beam with 30 kev energy and 30 pa current was sued to etch deep to the substrate and form side channel device, while ion beam with 16 kev energy and 11pA current was used to make the milling stopped inside the thicker (100nm) IGZO and develop direct channel device. Figure 5.6 demonstrates the process of using ion beam to modify the device structure. After the FIB milling, the final step is to remove the routing metal lines by photolithography and wet etch (HF: H2O2: H2O = 1:1:20 vol.). Thus the devices were separated from each other and ready for the test. Depends on the width and depth of the milling trench, the device can be divided into side channel TFTs and direct channel TFTs. (a) (b) FIG The cross-section view of the TFT structure before modification (a) and after modification by FIB (b). 96

118 5.2 Short Two-Sides-Channel α-igzo TFTs Milled by FIB If the IGZO active pattern is wider than the Ti metal lines one side or on both sides, higher ion energy and current can be applied to remove the IGZO, SiO2 and ITO layers between the drain and source and form a trench deep to the substrate. The side channel still exists on each side. Figure 5.7 (a) shows the SEM cross-section view of the milled trench. The Pt filling was used to provide better resolution of the boundary of the milled trench. Figure 5.7 (b) illustrates how the device works. If the IGZO is wider than Ti metal line, than two-sides channel was created; if the IGZO is only wider than metal line on one side, one-side channel TFTs were fabricated. For side channel TFTs, the IGZO thin film is 40nm thick. This deep milling does not require precise control of etch depth, so higher ion beam energy (30 kev) and current (30 pa) was applied to make the process faster. (a) (b) FIG.5.7. (a) Cross-section view of deep trench milled by FIB for side channel TFTs. (b) and (c) demonstrate the current flow for two-sides channel TFTs and one-side channel TFTs separately. The void is formed because of the joint of deposited Pt on upper side wall, which stop the Pt deposition on lower side wall and the bottom of the trench. 97

119 5.2.1 Right After FIB Milling Figure 5.8 (a) shows plain view of the trench of two-side channel TFT milled by FIB. The nominal width of the trench is 100nm and the width of the Ti metal line is 4μm. The cross-section view has been demonstrated in Figure 5.7 (a), the milling has removed Ti, IGZO, SiO2 and ITO between drain and source, so ideally there was no direct current between drain and source, only side channel is conductive. (a) (b) FIG.5.8. (a) Illustration of current flow when the device is in on state, Vgs > V T, Vds > 0,(b) Transfer characteristic (Vds = 0.1V and 1V) of α-igzo two-side channel TFT with 4um wide metal line and 100nm wide trench milled by FIB. Figure 5.8 (b) shows the transfer characteristic of a 4μm 100nm (4μm is the width of metal line, 100 nm is the nominal width of milled trench) TFT right after FIB milling without annealing. The maximum drain current at VDS = 1V is A, and the maximum leakage current is A. Von is ~0V and the subthreshold swing is estimated to be 2.36V/decade. The gate leakage current is very high, even higher than the 98

120 drain current at VDS = 1V. The high leakage is the result of residual Ga ions left after ion beam milling. The residual ions include both the ions left at the surface of the trench and implanted dose into the thin film. The ions at trench surface provide direct conduction between gate and drain or source, while the ions implanted into the SiO2 make the dielectric layer more conductive and results in gate leakage current through SiO2. It is obvious from Figure 5.8 (b) that when the gate voltage and drain voltage are both positive, the gate current increase much faster than drain current when gate voltage is increasing. The reason is that the source voltage is biased at 0V, when gate and drain voltage are both positive, drain current and leakage current from gate are competing to provide current to source. When the gate voltage is high enough, the leakage current dominate the process, leave reduced effective polarization inside the dielectric. Thus the increasing of accumulated electron density at IGZO/SiO2 is slowed along with rising gate voltage and at VGS = 10V, the gate current is comparable to drain current. When the gate voltage is negative, the gate leakage current is negative, which means the leakage current is from drain to gate Annealing in Air At 200 ºC for 10 min The purpose of annealing is to recover the damage of thin film created by FIB milling, and oxidize the residual Ga ions left at the trench surface, which will reduce part of the leakage current. However, annealing also enhance the diffusion of implanted Ga ions inside the SiO2. The ions will leave the location close to the trench edge, diffuse further to where the side channel is formed, thus make the gate leakage through the gate dielectric higher, and degrade the device performance. This process can be demonstrated in Figure

121 (a) (b) FIG Illustration of the residual Ga ions diffusion before annealing (Left) and after annealing (Right). After annealing this device in air at 200 ºC for 10 min, the device performance was improved. Figure 5.10 (a) shows the transfer characteristics of the same two-side short channel IGZO TFT with 4μm wide metal line and 100 nm wide milled trench, at drain voltage of 0.1V and 1V. The maximum drain current at VDS = 1V is A, and the maximum leakage current is A. Von is still around 0V and the subthreshold swing is reduced from 2.36V/decade to 1.12V/decade. 100

122 (a) (b) FIG (a) Transfer characteristic (V DS = 0.1V and 1V), (b) output characteristics of α-igzo two-side channel TFT with 4um wide metal line and 100nm wide trench milled by FIB and annealing at 200 ºC for 10 min. Figure 5.10 (b) shows the output characteristics of this device after 10 min annealing in air at 200 ºC under various gate voltages ranging from VGS = -6V~10V. The TFT shows the n-type enhancement mode performance, the device is in cut-off region when the gate voltage is negative and the maximum drain current increased exponentially. Small maximum drain voltage (3V) is applied as to avoid the device shorting due to the short channel and residual Ga ions at surface. The device exhibit linear mode because for most curve the gate voltage is much larger than maximum drain voltage (3V). The drain current is A with drain voltage of 3V and gate voltage of 10V. We also notice that at negative gate voltage, the drain leakage current was reduced from A to A. When the gate is negatively biased, the drain leakage current originates from the conduction between drain and gate due to residual Ga ions both on the trench surface and diffused inside the dielectric layer. Annealing only oxidize the surface 101

123 Ga ions, but drive more ions inside SiO2 and cause more leakage current through dielectric. Thus the drain leakage reduction is the result of oxidation of residual Ga ions on the trench surface. We need to remove more surface residual ions while reduce the further diffusion of ions in the dielectric. So annealing in higher temperature for short time is necessary Annealing in Air At 250 ºC for 10 min This device was annealed in air at 250 ºC for another 10 min. Figure 5.11 (a) shows the transfer characteristics at drain voltage of 0.1V and 1V. The maximum drain current at VDS = 1V is increased to A, and the maximum leakage current is reduced to A. Von is still around 0V and the subthreshold swing is increased from 1.12V/decade to 1.23V/decade. The on-off current ratio is about 10 3 for both VDS = 0.1V and VDS = 1V. The larger hysteresis window of the dual-sweep of gate voltage indicates a positive threshold voltage. The voltage shift is increased from 2V of devices annealing in air at 200 ºC for 10 min, to 2.5 V. The possible reason is explained in the previous chapter that, annealing in higher temperature diffuse more residual Ga ions into the dielectric, and they drifted vertically by external electric field from gate voltage. When the gate voltage is positive biased, the Ga positive ions were drifted towards the IGZO/SiO2 interface, and acted as electron trap. Thus the total density of electron trap at interface was increased if under positive gate bias and most of residual Ga ions were diffused to the location of channel by annealing. When gate voltage was under reverse sweep, more electrons were trapped at interface and results in positive threshold voltage. 102

124 (a) (b) FIG (a) Transfer characteristic (V DS = 0.1V and 1V), (b) output characteristics of α-igzo two-side channel TFT with 4um wide metal line and 100nm wide trench milled by FIB and annealing at 250 ºC for another 10 min. Figure 5.11 (b) shows the output characteristics of this device under various gate voltages ranging from VGS = -6V~10V. The drain current is increased from A to A with drain voltage of 3V and gate voltage of 10V. We also noticed the drain leakage current at negative gate voltage is further reduced. For un-annealed device, the drain leakage current is ~ A at VDS=1V, for device annealed in air at 200 ºC for 10 min, the drain leakage current is reduced by one order of magnitude to ~ A. When annealed in air at 200 ºC for another 10 min, drain leakage current is ~ A. The drain leakage current reduction rate is lower, which means most of the surface residual Ga ions have been oxidized, and the leakage current is mainly due to diffused ions in the dielectric. 103

125 5.2.4 Annealing in Air At 300 ºC for 10 min This device was annealed in air at 300 ºC for another 10 min. Figure 5.12 (a) shows the transfer characteristics at drain voltage of 0.1V and 1V. The maximum drain current at VDS = 1V is increased to A, and the maximum leakage current is further decreased to A. Von shifted in positive direction to 4V and the subthreshold swing is decreased to 1.10V/decade. The possible reasons for positive shift of threshold voltage is that the implanted Ga ions in the IGZO and at IGZO/SiO2 interface are oxidized ant incorporated into the IGZO, make the IGZO film less conductive because Ga ions combined with the oxygen and reduce the density of oxygen vacancy. This is confirmed by the fact that the hysteresis window is also reduced to 2V for the dual-sweep, as less Ga ions left at the IGZO/SiO2 interface. (a) (b) FIG (a) Transfer characteristic (V DS = 0.1V and 1V), (b) output characteristics of α-igzo two-side channel TFT with 4um wide metal line and 100nm wide trench milled by FIB and annealing at 300 ºC for another 10 min. 104

126 Figure 5.12 (b) shows the output characteristics of this device under various gate voltages ranging from VGS = -6V~10V. It is clear that the device entered into saturation mode at lower drain voltage even under high gate voltage (VGS = 10V), this is because Von is increased from 0V to 4V, and the condition for saturation mode VDS > VGS Von is easily satisfied. 5.3 Short One-Side-Channel α-igzo TFTs Milled by FIB Right After FIB milling Figure 5.13 (a) shows plain view of the trench of one-side channel TFT milled by FIB. The nominal width of the trench is 100nm and the width of the Ti metal line is 8μm. The cross-section view has been demonstrated in Figure 5.13 (a), the milling has removed Ti, IGZO, SiO2 and ITO between drain and source, and IGZO is wider than metal line only on one side and only one side channel was created. (a) (b) FIG (a) Illustration of current flow when the device is in on state, V GS > V T, V GS > 0,(b) Transfer characteristic (Vds = 0.1V and 1V) of α-igzo one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB. 105

127 Figure 5.13 (b) shows the transfer characteristic of a 4μm 100nm (4μm is the width of metal line, 100 nm is the nominal width of milled trench) TFT right after FIB milling without annealing. The maximum drain current at VDS = 1V is A, and the maximum gate leakage current is A. which is even much higher than the drain current. This indicates that Von is ~-0.5V and the subthreshold swing is estimated to be 0.51V/decade. The gate leakage current is even much higher than the drain current at VDS = 1V and VGS = 10V, which means the direct conduction exists between gate and source because of the residual Ga ion at trench surface. Another proof verify that most of the residual ions stayed at the surface is that when gate voltage is below VON, IDS-VGS curve shows resistor feature, indicates that residual ions also left between gate and drain. Besides, the drain leakage current at negative gate voltage at VDS = 1V is also higher than that of VDS = 0.1V, and the only way the leakage current can happen between drain and source is surface residual Ga ions. Given all that, before the annealing, the Ga residual ions cover all the surface of the milled trench, and leakage current can occur between any two terminals of gate, drain and source, depends on their voltages Annealing in Air At 200 ºC for 10 min After annealing this device in air at 200 ºC for 10 min, the device performance was improved. Figure 5.14 (a) shows the transfer characteristics of the same one-side short channel IGZO TFT at drain voltage of 0.1V and 1V. The maximum drain current at VDS = 1V is improved to A, which is the result of reduction of direct leakage to gate, the polarization of dielectric is enhanced and more mobile electrons are accumulated at IGZO/SiO2 interface to form the inversion layer. The maximum leakage current is reduced to A, Von positively shifts to 0V and the subthreshold swing is 0.79 V/decade. 106

128 At negative gate bias, the IDS-VGS curve shows almost no resistor feature, and the main drain leakage current at this moment is the result of residual ions between drain and source. Figure 5.14 (b) shows the output characteristics of this device after 10 min annealing in air at 200 ºC under various gate voltages ranging from VGS = -6V~10V. The curve with VGS above 4V stays in the linear region because small drain voltage (3V) is applied and VDS<VGS-VON. (a) (b) FIG (a) Transfer characteristic (V DS = 0.1V and 1V), (b) output characteristics of α-igzo one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB and annealing at 200 ºC for another 10 min Annealing in Air At 250 ºC for 10 min This device was then annealed in air at 250 ºC for another 10 min. Figure 5.15 (a) shows the transfer characteristics at drain voltage of 0.1V and 1V. The maximum drain current at VDS = 1V is further increased to A, and the maximum leakage current is reduced 107

129 to A. Von is 0V and the subthreshold swing 0.92 V/decade. Compare with the device without annealing and annealed in air at 200 ºC, this one shows a much lower drain leakage current and larger on-off ratio for VDS=0.1V, even though the drain leakage current at VDS=1V is still high. We can conclude that at 250 ºC, the residual ions connecting drain and source is further reduced, and the drain-source conduction acts like a Schottky junction. The larger hysteresis window of the dual-sweep of gate voltage also occurs for one-side channel TFTs at the same annealing temperature and time, is the result of more electron trap at IGZO/SiO2 interface formed by Ga ions as mentioned before. For VDS = 0.1V, VON is increased from -0.1V to 1.5V, which means the oxidation of Ga ions inside IGZO reduce the mobile electron density. (a) (b) FIG (a) Transfer characteristic (V DS = 0.1V and 1V), (b) output characteristics of α-igzo one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB and annealing at 250 ºC for another 10 min. 108

130 Figure 5.15 (b) shows the output characteristics of this device after 10 min annealing in air at 250 ºC under various gate voltages ranging from VGS = -6V~10V. The curve with VGS below 6V all enters the saturation region because of the positive shift of VON. In conclusion, this step of annealing is critical as it is obvious that the annealing oxidize most of the surface residual ions, and more Ga ions diffused into the IGZO or SiO2 thin film. Some of them act as electron trap to increase the hysteresis window, and the ones left in IGZO were incorporated into IGZO and reduce the carrier density Annealing in Air At 300 ºC for 10 min This same device was annealed in air at 300 ºC for another 10 min. Figure 5.16 (a) shows the transfer characteristics at drain voltage of 0.1V and 1V. The maximum leakage current is reduced to A. Von is 2V and the subthreshold swing 0.91 V/decade. Compare with the device without annealing and annealed in air at lower temperatures, the drain leakage current for VDS = 1V and VDS = 0.1V are in the same level and below A. This indicates that the direct conduction between drain and source were almost eliminated by annealing, and VDS has no effect on the drain leakage current. However, the gate leakage current is still very high at positive gate bias, and the date shows that it originate from the source-gate leakage. 109

131 (a) (b) FIG (a) Transfer characteristic (V DS = 0.1V and 1V), (b) output characteristics of α-igzo one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB and annealing at 300 ºC for another 10 min. Figure 5.16 (b) shows the output characteristics of this device after 10 min annealing in air at 300 ºC under various gate voltages ranging from VGS = -6V~10V. The curve with VGS below 8V all enters the saturation region because of more positive shift of VON. 5.4 Discussion on Side Channel TFTs Milled by FIB In this session, the effect of the ion beam variation and milling strategy on the device performance will be discussed. The one-side channel device and two-side channel device will also be compared to verify the impact of effective channel width Effect of Residual Ions by FIB milling As mentioned in last section, the residual ions induced by FIB milling include the ions left at the milled trench surface and the ones implanted into the SiO2. Before annealing, the most of ions stayed at the surface, and covered the whole surface of the trench, thus the leakage current exists between gate, drain and source, and the direction of the current depends on their bias voltages. 110

132 Annealing helps to oxidize the surface ions and reduce the direct leakage current, but will also drive the ions diffuse into all the tin films that are exposed to the residual ions, and annealing in higher temperature and longer time will make the diffusion deeper. The Ga ions in IGZO layer will combine with oxygen and reduce the free carrier density. The Ga ions left inside the SiO2 layer will make the dielectric conductive and result in high gate leakage. However, the residual ions are not uniformly distributed on the trench surface. Ideally, the ion beam should be vertical to the device surface, because before milling on one location, the sample stage is adjusted to find the eucentric location by SEM, and after rotating the stage by 52 degree, the ion beam is vertical to the sample. After moving the sample to focus on another location, the stage may not shit in the same plane, which leads to a non-zero incident angle of ion beam to the surface, unless we do the eucentric adjustment for each location, which takes long time. It is demonstrated in Figure 5.17 (a). The red dashed line represents the sample stage without eucentric adjustment. When the incident angle of ion beam is zero, most of residual ions left at the bottom of the trench, and the gate leakage current is minimized. If the ion beam is tilted, the side wall of the trench facing the beam is subjected to more milling and ion implantation, thus gathers more residual ions. This is also demonstrated in Figure 5.17 (b). The profile of milled trench indicates the non-vertical direction of ion beam. 111

133 (a) (b) FIG (a) Schematic of the FIB ion beam with zero incident angles (black solid) and non-zero incident angle (red dashed) to the sample stage. (b) shows the cross-section view of milled trench when the ion beam is tilted to right (top) and tilted to left (bottom). So three situations occur depends on the direction of the ion beam: 1) Beam is vertical to the surface, and most of the residual ions are at the bottom of the trench. As the milling etched through all the thin film and stopped at substrate, the gate leakage is minimized. This is indicated in position 1 of Figure ) If beam is facing the drain side, most of the residual ions stayed at the side wall close to the drain, so the leakage current between gate-drain is high, as shown by position 2 of Figure

134 3) When the beam is facing the source side, most of the residual ions stayed at the side wall close to the source, so the leakage current between gate-drain is high, as shown by position 3 of Figure FIG Demonstration of residual Ga ions distribution depends on the ion beam direction. The device characterization before annealing in Figure 5.19 also proves this assumption. Figure 5.19 (a) shows that the gate current is very small, the drain current and source current have the same amplitude and opposite sign when the device is on. This is the ideal situation, where the gate leakage current to drain or source is minimized. Figure 5.19 (b) indicates that the drain current and gate current always shows current with same amplitude 113

135 but opposite direction, and are both zero at VGS = 1V, which is also the drain gate bias. This means the main leakage current occurs between drain and gate due to more residual ions left at the side wall of trench at the drain side. Figure 5.19 (c) shows that at positive gate bias, the source current is negative and the amplitude equals the sum of amplitude for gate current and drain current. Drain current also appears because of VDS = 1V. This represents that the source-gate leakage is the dominating conduction as a result of more residual ions left at the side wall of trench at the source side. (a) (b) (c) FIG The transfer characterization of two-side channel TFTs milled by FIB without annealing when the main current occur between drain-source (a), gate-drain (b), and gate-source (c) Effect of Side Channel Length on TFTs with Side Channel Milled by FIB As mentioned earlier, the FIB milling removed all the thin films between drain and source terminals, only side channel exist. Thus the channel length is not determined by the width, but the length of the trench. The trench needs to be longer than the metal line in order to separate the drain and source, and the length of trench beyond the metal line determine the effective channel length. When the device is on, the majority of the electrons 114

136 prefer to flow from the source to drain along the corner of the trench, and minor electrons will spread out away from the trench to avoid current crowding. (a) (b) FIG Illustration of current flow of one-side TFTs mill by FIB with excess trench length of (a) 298.4nm and (b) 708.3nms Figure 5.20 shows the SEM pictures of two one-side channel TFTs with 250 ºC annealing in air for 10 min after milling. The etching created shorter channel for the left one and longer channel for the right one. Figure 5.21 shows the compare of transfer characteristic for these two devices at VDS = 1V. They show the similar level of gate leakage current at VGS = 10V so the effect of gate leakage on the drain current is minimized. It is clear that the TFT with shorter channel exhibit larger drain current. Besides, it also shows lower VON, because shorter channel was milled with shorter time and smaller 115

137 amount of ions left at the trench, and fewer Ga ions are diffused into IGZO to reduce the carrier density after annealing. FIG Compare of the one-side channel TFTs with different effective channel length, after annealing at 250 ºC in air for 10 min Compare Between One-Side Channel and Two-Side Channel TFTs Milled by FIB Two TFTs with one-side channel and two-side channels with annealing with 250 ºC annealing in air for 10 min after milling are compared, and the transfer characteristics are 116

138 shown if Figure The excess trench lengths beyond metal line are ~300nm for both TFTs, on each side of the channel. Two device also exhibit same gate current level so the leakage effect are eliminated. Results shows that the device with two-side channel reached higher drain voltage and has rapid current increase compared with one-side channel device. This is because two-side channel TFTs has wider effective channel width, and the less current crowding effect. FIG Compare between one-side channel and two-side channel TFTs, after annealing at 250 ºC in air for 10 min. 117

139 5.5 Short Direct-Channel α-igzo TFTs Milled by FIB The advantage of side-channel α-igzo TFT is that no photolithography and mask with small critical dimension are necessary to fabricate short channel TFTs. No precise control of milling time is needed to form side channel. However, as the ion beam removed all the thin films between drain and source, only side channel exist, and the effective channel width is limited by the space between the trench corner and the edge of the IGZO pattern. Besides, current crowding effect around the trench corner will also limit the drain current. In order to obtain wider channel width by using the same IGZO pattern and metal line, direct channel between drain and source is necessary. To get direct channel, the milling should remove the metal film and stop at the IGZO layer. Milling time, in other words, parameter z, needs to be adjusted to achieve this goal, as the IGZO is amorphous semiconductor and can be etched away rapidly by ion beam. The right trench in Figure 5.23 (a) shows that at z=85nm, the bottom of the trench is smooth and shows darker color, the corresponding cross-section view of Figure 5.23 (b) show that a very thin layer of Ti metal still left on top of IGZO. The middle trench in Figure 5.23 (a) shows a rougher bottom, and some ridge patterns exit in the trench. Besides, at right and left sides of the trench, clear borderline shows up, indicating the different etching rate in Ti and IGZO. This is confirmed from Figure 5.23 (c) that, the ion beam etches IGZO faster than Ti, and the ion beam has etched into IGZO at the very center part of the trench. This also explains the ridge pattern, which might be the residual Ti metal at the edge of the trench. The left trench in Figure 5.23 (a) shows that the metals are completely separated by milling and a smooth bottom appears at the center of the trench. Figure 5.23 (d) proves that the milling stopped inside the IGZO. However, the ion beam etched faster on the left side. 118

140 The reason has been given in the last section that the incident angle of ion beam is not absolute zero. FIG (a) Shows the plain view of milled trenches with different milling depth (z parameter). The cross-section view are shown also shown in (b) for z=85nm, (c) for z=90nm and (d) for z=95nm. 119

141 5.5.1 Right After Milling The device for direct channel milling used the similar process flow of side channel device, except that the IGZO was deposited with larger thickness of 100nm, in order to guarantee that the milling can been controlled to stop at IGZO. Figure 5.24 (a) shows the schematic of the direct channel TFT milled by FIB. The IGZO is narrower than the metal line, and current can only flow through direct channel, as indicated by red arrow. Figure 5.24 (b) shows the plain view of the device by SEM. The nominal etch gap width was set to 200nm, which is wider than 100nm of side channel milling. This is because the ion beam energy received by sample is not absolute constant during milling, and larger gap was to make sure the residual metals from the drain and source side, which is the result of ion beam with lower energy, are not connected and leads to leakage current. The dimension of the IGZO pattern is 4μm 4μm, so the width and length of the channel are 4μm and 200 nm separately. FIG.5.24 Schematic (a), SEM plain view (b) of current flow and transfer characteristic (V DS = 0.1V and 1V) of a direct-channel IGZO TFT (W/L = 4μm/200nm) right after FIB milling. 120

142 Figure 5.24 (c) shows the transfer characteristics (VDS = 0.1V and 1V) of this directchannel IGZO TFT (W/L = 4μm/200nm) right after FIB milling. Even though the drain current increase a little (from A at VGS = -5 V to A at VGS = 10V, with VDS = 1V), it does not show typical on-off feature of TFTs. Besides, drain current at VDS = 1V is much larger than drain current at VDS = 0.1V. All these indicate that without annealing, the residual Ga ions left on the side wall of trench and bottom IGZO surface shorted the drain and source, even though the IGZO channel became more conductive with increasing gate bias, the dominating conduction current went through the residual ions, and the device acts like a resistor. Unlike the side-channel TFTs, the gate leakage current before annealing stays below A and does not change a lot with increasing gate voltage. The reason is that for directchannel TFTs, the milling stopped at the IGZO, the SiO2 and ITO thin film under the IGZO layer were not etched by ion beam. Without annealing, the residual ions only left at the surface of the trench, no direct current flow exit between gate and source (drain) under bias After Annealing in Air At 200 ºC for 30 min The device was fist annealed in air at 200 ºC for 30 min, and the transfer characteristics and output characteristics are shown in Figure 5.25 (a) and (b) separately. The device performance was improved as the on-off TFT feature appears. The VON is beyond the gate voltage sweep limit and should be below -5V. The maximum drain current at VDS = 1V is A, the on-off ratios are 10 and 10 2 for VDS=1 and VDS=0.1 separately. The strong dependence of drain current on drain voltage at negative gate voltages indicates that residual Ga ion still stays at the trench surface, and current between drain and source originate from both leakage current by residual ions and channel current through IGZO. 121

143 The low gate leakage current (<10-10 A) and no increasing with rising gate bias demonstrates that after 200 ºC annealing for 30 min, no leakage appears between gate and drain (source). The annealing oxidized part of the surface residual Ga ions, and did not diffuse implanted ions further into SiO2 too much. (a) (b) FIG (a) Transfer characteristic (V DS = 0.1V and 1V), (b) output characteristics of a direct channel IGZO TFT (W/L = 4μm/200nm) after annealing in air at 200 ºC for 30 min. Figure 5.25 (b) shows the output characteristics of the device after annealing. The device acts like a resistor and the curves do not show cut-off region, because the VON is very negative, and the device was always in on state After Annealing in Air At 250 ºC for 30 min The same device was annealed in air at 250 ºC for another 30 min, the maximum drain current with VDS = 1V was increased from A to A. The lowest drain leakage is reduced below 10-8 A, and the on-off current ratio is about 10 3 for both VDS=0.1V and VDS=1V. The drain current is increased because the IGZO was partially recovered from 122

144 the Ga ion milling by further annealing, and current flow exists through both IGZO channel and surface residual Ga ions. The gate leakage current increased with the rising gate voltage and reached to 10-8 A. This is because the implanted Ga ions diffused deeper into the SiO2 and make the dielectric layer more conductive. At high gate bias, leakage current occurs between gate and source. (a) (b) FIG (a) Transfer characteristic (V DS = 0.1V and 1V), (b) output characteristics of a direct channel IGZO TFT (W/L = 4μm/200nm) after annealing in air at 250 ºC for 30 min. Figure 5.26 (b) shows the output characteristics of this device under various gate voltages. Compare with the result after the 200 ºC annealing, drain current under low gate bias (VGS < -2V) are in the cut-off mode. The drain current curves show a slow increase when VDS < 1V, and increase rapidly with VDS above 1V. The possible reason is the coexits of IGZO channel current and surface residual ion leakage current. The detail will be discussed later in this chapter. 123

145 5.5.4 After Annealing in Air At 300 ºC for 30 min The device was then annealed in air at 300 ºC for another 30 min and the results are shown in Figure The maximum drain current at VDS = 1V was dropped from A to A, because the annealing removed most of the surface residual ions, and the current flow through the ions was eliminated. The device shows clear on-off feature, and the leakage drain currents at negative gate bias are below 10-9 A, and the minimum drain leakage for VDS = 0.1V and VDS = 1V stays at the same level, which is another evidence that the most of the surface ions are oxidized. The on-off current ratio is improved to almost 10 5 for VDS = 1V and the subthreshold swing is estimated to be 0.29V/decade. However, the gate leakage is very high, and reached the same level of drain current. This indicates that after long time annealing (90 min), the induced Ga ions were diffused through the whole SiO2 layer. The VON is positively shifted to -1V when VDS = 1V, as more Ga ions were incorporated to IGZO, oxidized with oxygen and decrease the density of mobile electrons. (a) (b) FIG (a) Transfer characteristic (V DS = 0.1V and 1V), (b) output characteristics of a direct channel IGZO TFT (W/L = 4μm/200nm) after annealing in air at 300 ºC for 30 min. 124

146 Figure 5.27 (b) shows the output characteristics of this device under various gate voltages. Compare with the result after the 250 ºC annealing, the drain voltage where the drain current begins to increase rapidly moved from 1V to 0.5V. When VGS < 6V, the drain current start to saturate as a result of the positive shift of VON Discussion Compare the transfer characteristics for side channel TFTs and direct channel ones, it is obvious that the side channel one shows much higher gate leakage current when both devices are not annealed, and the gate current increase exponentially with rising gate bias, as shown in Figure 5.28 (b). The reason is illustrated in Figure 5.28 (a). For side channel TFTs, the Ga ions covers the whole surface of the trench milled by the ion beam, thus a direct leakage conduction exist between Darin(source) and gate through the ions. The twoside channel TFTs in Figure 5.28 (b) shows the lowest gate leakage current ( A at VDS = 1V and VGS = 10V) in all milled side channel TFTs, which means the ion beam strike the sample surface almost vertically, but the leakage is still two order of magnitudes higher than that of direct channel TFTs ( A VDS = 1V and VGS = 10V). Another factor needs to be investigated is the channel thickness of direct channel TFTs after FIB milling. Figure 5.29 shows the compare of transfer characteristics for devices with different channel thickness. The two devices locate next to each other so the variation of ion beam quality during sample moving is minimized. They both have 200 nm channel length and are annealed in air at 300 ºC for 30 min. The difference of milling depth parameter z is 4 nm, according to the fact that 100 nm IGZO was transferred to 10 nm in z parameter, and 4 nm difference should give a 40 nm difference in real channel thickness. 125

147 (a) (b) FIG Compare of gate leakage current for direct-channel TFTs and side-channel TFTs. (a) The schematic of cross-section view of side-channel TFT (top) and direct channel TFT (bottom) after FIB milling, (b) the transfer characteristics for devices at V DS = 0.1V and 1V without annealing. (a) (b) FIG Transfer characteristics for direct-channel TFTs (W/L = 4μm/200nm) with thin IGZO (a) and thick IGZO (b) at VDS = 1V, after FIB milling and annealing in air at 300 ºC for 30 min 126

148 Figure 5.29 shows that the device with thicker channel exhibits much lowers gate leakage. This is because to create thicker channel, less milling time and ion implantation was introduced into the IGZO and SiO2 thin film, thus after annealing, less ions are diffused into SiO2, which leads to lower gate leakage. Device with thicker channel also shows higher maximum drain current ( A) than device with thinner IGZO ( A). Besides, thicker channel results in more negative VON of -2V, compared with thinner channel of -1V, as less milling time introduce less Ga ions into IGZO, and more oxygen vacancies stays without suppressed by Ga. 5.6 Effect of Channel Dimension on Drain Current and Leakage Current For the direct channel IGZO TFTs, the channel length is defined by the width of the milled trench, which is 200 nm in this research. As the IGZO active pattern is narrower than the metal line, the channel width is determined by the IGZO pattern size. For side channel IGZO TFTs, the dimension of the channel is complicated. Because the channel was created at the corner of the trench, most of the electrons are crowded at the edge of the trench, transported between drain and source with the minimum moving distance. This is confirmed by the TCAD simulation result of Figure 5.30, which shows that the highest electron density appears at the trench edge. The zoomed picture shows that the highest electron density exists within 100 nm from the edge of trench, which can be considered as the effective channel width. 127

149 . FIG Simulation result of electron density distribution of IGZO TFTs. The IGZO carrier density is cm -3, V DS = 3V and V GS = 9V. Channel dimension and drain current are compared between direct channel TFT and side channel TFT. For direct channel device, the remaining IGZO thickness is about 50 nm (Figure 5.23 (d)), which is regarded as the channel thickness. Milled trench width is 200nm, which is the channel length, and dimension of IGZO pattern (4 μm) represents the channel width. For side channel device one-side channel TFTs shown in Figure 5.20 (a) was used. The channel thickness is 40 nm, and the effective channel length is ~800 nm (300 nm trench extension * nm trench width). Electron diffusion length of 100 nm as shown in Figure 5.30 is used as the channel width. The compare of transfer characteristics are shown in Figure 31. Both devices are annealed in 300 ºC in air for 10 min after milling. 128

150 FIG Compare of transfer characteristics for direct channel TFT (black) and one-side channel TFT (red). The direct channel device has channel thickness of 50 nm and W/L = 4um/200nm, the one-side channel device has channel thickness of 40 nm with W/L = 100nm/600nm. To normalize the result, the product of T(channel thickness) * W/L is compared. For direct channel TFT, T*W/L = 1000 nm, while for one-side channel TFT, T*W/L = 5 nm. The maximum drain currents at VDS = 10V for direct channel TFT and one-side channel TFT are A and separately. The T*W/L ratio of direct channel TFT is two orders of magnitude higher than that of one-side channel TFT, but the maximum drain current is only one order of magnitude higher. This indicates that for direct channel TFTs, the channel is right under the milled trench and compared with one-side channel, the 129

151 channel IGZO is more affected by the Ga ion implantation, which results in lower carrier mobility. Another important factor that limits the drain current level is the gate leakage current. Side channel TFTs and direct channel TFTs show different channel structure because of the different milling strategy. Direct channel has milling stopped inside IGZO, which means the most of the Ga ions are left at the trench surface without annealing. For side channel TFTs, milling etched through into the substrate, so the residual Ga ion both on trench surface and inside dielectric results in higher gate leakage current, even without annealing. This can be verified in Figure 5.32 (a), which shows the compare the gate leakage current of direct channel TFT and one-side channel TFT without annealing. While after annealing, the surface residual Ga ions at trench surface of direct channel TFT were diffused into dielectric. For one-side channel TFTs, the gate leakage through surface Ga ion was reduced, however diffused Ga ion in dielectric due to annealing result in additional gate leakage current. Because direct channel TFTs suffers larger ion diffused area in dielectric, it shows higher gate leakage current after annealing as shown in Figure 5.32 (b). Assume that for direct channel TFT, most of the diffused Ga ions in dielectric locate right below channel, so the diffusion region share the same dimension with the channel (W = 4 μm, L = 200 nm). For side channel TFTs, device in Figure 5.20 (a) was used which has L = 800 nm (300nm trench extension* nm trench width), and the diffusion region width is the lateral extension of Ga ions into the dielectric. Assume the gate leakage current density is the same for direct channel TFT and side channel TFT, according to the maximum gate leakage current level for one-side channel TFT ( A) and direct 130

152 channel TFT ( A), the approximate of Ga ion lateral diffusion length into dielectric for side channel TFT should be 150 nm. (a) FIG Compare of gate leakage current for one side channel TFT (black) and direct channel TFT (red) without annealing (a) and after 300 C annealing in air for 30 min. (b) 5.7 Conclusions In summary, IGZO TFTs milled by focused ion beam are demonstrated in this chapter. The fast milling with higher ion energy and current can be used to fabricate side channel TFTs with n-type enhancement mode accumulation characteristics. To create direct channel TFTs, the milling needs to be stopped inside IGZO thin film and a lower ion energy and current was applied. For side channel TFTs, annealing is necessary to remove the surface residual Ga ions and reduce gate leakage current. However, higher annealing temperature and longer annealing time will also make Ga ions diffuse further into SiO2 layer and increase the gate leakage through dielectric. The Ga ion in IGZO also increases the VON by suppressing the 131

153 oxygen vacancies. For direct channel TFTs, the leakage through surface residual ions are eliminated as the milling did not touch the ITO gate film. However, the annealing also drives more ions into SiO2 and increase leakage current. Though thicker IGZO channel with less milling time shows much lower leakage, it also exhibit more negative VON. 132

154 CHAPTER 6 SHORT CHANNEL THIN FILM TRANSISTOR WITH TWO DIMENSIONAL ARRAYS OF α-igzo ISLANDS PATTERNED BY LASER INTERFERENCE LITHOGRAPHY We plan to fabricate different logic gates, including multiple inverters, NAND gates and NOR gates, and integrated them into one big array module. The inputs and outputs of these single gates can be connected to fulfill some simple logic functions. We will also use laser interference lithography to define IGZO active region with smaller feature size, and make logic gates based on these small IGZO channel and arrange logic gates into arrays. 6.1 Laser Interference Lithography In this work, the sample dimension is 15 mm 15 mm, Lloyd-mirror interferometer was applied to cover larger area and obtain more functional α IGZO active islands. A Kimmon He-Cd laser with wavelength of 325 nm was used as the laser source, and the laser was p-polarized. Though submicron structure can be achieved by using such short wavelength, the feature size of α-igzo island obtained in this work is about 1 s usedrger IGZO patterned is necessary to provide enough space for drain(source) current injection area after 200nm wide trench milling by FIB. The mirror angle (x) and substrate stage angle (y) shown in the following picture were both set to be 80, and the 1D pattern periodicity based on equation 2.9 is 2.74 μm. 133

155 FIG.6.1. Schematic of Lloyd-mirror interferometer setup. Blue lines are the light from the laser and purple lines represent the reflected light from the mirror. To get good interference pattern, the intensities of direct incident light and reflected light from the mirror should be identical, thus lenses are necessary to make the Gaussian shape of the laser more divergent and the laser gives more uniform intensity distribution over longer vertical distance. AZ5214E photo resist was used for the traditional lithography with thickness of 1.4 μz after 50 sec spinning at speed of 5700 round/min. However, the light intensity after diverge is much smaller compared with traditional lithography, and to fully expose the thick photoresist, much longer exposure time is required. Besides, the reflected wave from the thin films under the photoresist will form standing wave with incident wave, and deteriorates the exposure profile in vertical direction. To reduce the exposure time and the effect of vertical standing wave, thinner photoresist was applied by diluting it with solvent (AZ5214E: PGMEA = 1:1), and the thickness was decreased to ~250nm. 134

156 6.2 Device Fabrication The great benefit of using laser interference to pattern the IGZO active layer is saving one layer of mask design and achieving small feature without using more complicated and expensive electron beam lithography system. First, traditional lithography and BCl3 reactive ion etching (RIE) were applied on the substrate to pattern the top ITO layer and form the bottom gates. Then the 100nm SiO2 was deposited by PECVD at 300 C, followed by another deposition of 100nm IGZO thin film by PLD. The SiO2 layer was not patterned at this moment because to reduce the internal reflection and diffraction during the laser interference, it is necessary to keep the surfaces of the layers under the photoresist as smooth as possible. The IGZO patterns we need always locate on top of the SiO2, so the SiO2 etching will not affect the IGZO pattern we want to keep. As the photoresist film is not thick enough (250nm) compared with the IGZO film to be deposited, lift-off process is not suitable. Thus the IGZO was deposited first, followed by subsequent etching. After the spinning of photoresist on top of IGZO, the sample was exposed to 325nm He-Cd laser, then rotated the sample for 90 and took another exposure with the same duration. Thus the two exposures created two 1D arrays of pattern in orthogonal, and form the 2D square arrays of photoresist islands after developing. The overlap region of two exposures which shows 2D square array of patterns is 12mm 12mm, which covers most part of the sample surface. The measured diameter of the photoresist feature is ~1.25 As the photoresistis 2.5 μm in both directions. The images of the sample surface after photoresist patterning under optical microscope and Atomic Force Microscope (AFM) were shown in Figure 6.2. We observed from the AFM picture that the height of the peaks is about 250nm and the flat 135

157 exist between two neighboring peaks, which means the photoresist layer was fully exposed and developed. (a) (b) FIG.6.2. Images of 2D patterned photoresist arrays under optical microscope (a) and AFM (b). The next step is to pattern the IGZO by wet etching. In order to protect the SiO2 layer, diluted weak acid (acetic acid: DI water = 1:4 wt.) was applied. After etching and photoresist stripping, the images of the patterned IGZO 2D arrays under optical microscope and Atomic Force Microscope (AFM) were shown in Figure 6.3. The IGZO island is 100nm thick and shows sidewalls with large slope because of the isotropic wet etching. After IGZO patterning, about 250 nm Titanium was deposited by electron beam evaporation with drain and source intentionally connected, followed by FIB milling to separate drain and source. Figure 6.4 shows the color patterns of the sample surface because of the interference effect( the 2D array patterns act as diffraction grating The final step is using wet etch (HF: H2O2: DI water = 1:1:20) to remove the connecting metal lines, 136

158 which were used during FIB to reduce the charging effect, and separated the individual devices from each other. (a) (b) FIG.6.3. Images of 2D patterned IGZO arrays under optical microscope (a) and AFM (b) FIG.6.4. Image of color pattern after IGZO wet etching and electron beam evaporation of Titanium 137

159 6.3 Layout Design of Logic Arrays To make reliable arrays of logic gates, we need to follow some design rules. First, all components, including TFTs, routing connecting lines and contact pads, need to be aligned in row or column, so they can be tracked easily to be combined to lager circuit element. Besides, routing line of gate, drain, source, ground and power supply need to be separated by dielectric if necessary, to avoid short or malfunction of the devices. Furthermore, to make each single gate works dependently, matrix floor plan with row selecting and column selecting should be incorporated. Thus by giving the signal to specific row and column selecting contact, we can active the gate we need while leave the rest idle. (a) (b) (c) (d) FIG (a) Full layout of logic gate array mask design, including ITO (red), dielectric (yellow) and contact metal (blue). Bottom: (b) layout of inverter (c) layout of NAND (d) layout of NOR. 138

160 Figure 6.5 shows the logic gate array layout of mask design. It include 4 rows and 6 columns. The left, middle and right 4 2 logic gates are inverters, NANDs and NORs separately. The row selection electrodes locate at the left, inputs electrodes are on the top and ground (GND), supply (VDD) electrodes are on the bottom. The rest big square electrodes (blue squares) inside the array are the outputs for each logic gates. Figure 6.5 (b) shows the layout of inverter design. Two conducting materials are used for routing because we have routing lines intersected with each other. Red is for ITO, blue is for metal, and at intersection they are separated by dielectric (yellow). When the row selecting line 1 is high, transmission gate 3 is on, and the input signal 2 is transmitted into the gate of function transistor 4 through transmission gate 3as shown by solid arrow. If input is high, then gate of function transistor 4 is high, output 5 is pulled low to ground as shown by dashed arrow. Input acts as both signal electrodes and column selecting electrodes. 7 is the load transistor in saturation mode as the gate and drain are connected together. Figure 6.5(c) shows the layout of NAND gates. It works similar to inverter, except that function transistor 4 and 5 are connected in series between output 6 and ground. The input A and input B also need to go through transmission gate to function transistor 4 and 5 separately. Figure 6.5(d) shows the layout of NOR are gates and function transistor 4 and 5 connected in parallel between output 6 and ground. We can only pick one gate from the same one column, and from the full array, we can activate 2 inverters, 2 NAND gates and 2 NOR gates at the same time to realize more complex function. The following sections will focus on the electrical characterization of the transmission transistor and function transistor in the inverter gate pixel. Figure 6.6 (a) demonstrate the equivalent circuit schematic of inverter gate pixel and Figure 6.6 (b) shows the corresponding SEM picture. 139

161 (a) (b) FIG.6.6. (a) Equivalent circuit schematic of inverter gate pixel and the corresponding SEM picture (b). 6.4 Short Direct-Channel TFTs with Laser Interference Lithography Patterned IGZO Active Layer and Milled by FIB Much thicker Titanium (250nm) was deposited by electron beam evaporation compared with single TFT fabrication to guarantee low resistance because narrow and long routing metal lines were used to connect the terminals of each TFTs to the input and row selection electrodes, which locate at the boarder of the arrays. To mill away such thick metal by using Ga ion with low energy and low current, long time is inevitable. To save the time, ion beam with low energy (16 kv) and higher current (50 pa) was utilized for the milling, as current is of less importance, but low energy is necessary to get more straight side wall of milled trench, reduce the ion implantation depth and damage to the thin film. For each inverter gate pixel, the identical milling time was applied to both the transmission TFT and function TFT. 140

162 To test the transfer characteristics of the single TFTs in the inverter gate pixel, the source probe and drain probe were contacted to the terminal GND and terminal 5 respectively for the function TFT as shown in Figure 6.5 (b). The gate probe was contacted to the terminal input, which was connected to the terminal gate of function TFT through transmission TFT. The gate probe voltage was sweeping while the row selection terminal voltage kept constant. Figure 6.7 (a) shows the SEM picture of the function TFT after FIB milling. The dimension of the small IGZO island is about 1μm 1 μm ) and the metal line covers three or four islands. The nominal width of the milled trench is 200nm, so the dimension of the function TFT channel is W/L = 3μm (4μm)/200nm. Figure 6.8 (b) shows the cross-section view of the trench. It is obvious that the milling stopped right inside the IGZO film, so the direct channel was created between drain and source. (a) (b) FIG.6.7. (a) SEM image of the function TFT of the inverter gate pixel in the array after FIB milling. (b) The cross-section view of the milled trench. 141

163 6.4.1 Right After Milling Figure 6.8 shows the transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) right after milling for Vr = -5V and Vr = 5V, VDS is kept at 0.1V. The drain current is very high (10-4 A) and does not show on-off feature, which means the conduction originates from the surface residual Ga ions. The gate leakage current increase from A to A along with the increasing gate voltage, indicates that leakage current exist between gate and drain (source). The Ga ions were implanted into the SiO2 during FIB milling and made the dielectric more conductive FIG.6.8. Transfer characteristics of the function TFT of inverter gate pixel in the logic gate array at various row selection voltages Vr After Annealing in O2 At 250 C for 20 min & At 300 C for 20min Figure 6.9 (a) and (b) shows the transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after a annealing in O2 at 250 C for 20 min and annealing in O2 at 300 C for 20min separately. It is observed that the drain current was decreased to

164 A for 250 C annealing and A for 300 C annealing. Besides, the drain current shows clear increase at positive gate bias. The annealing removes part of the surface residual Ga ions and more mobile electrons were moving through the IGZO thin film. Because IGZO is not as conductive as Ga ions even with the existence of accumulation layer, so the overall drain current still drops. We also notice that for the curves with Vr = -5V, gate leakage raises dramatically when the gate bias increases above 0V, and for the curves with Vr = 5V. The gate leakage also decrease rapidly when the gate bias dropped below 0V. Figure 6.10 shows the intersection of input line and row selection line. The SiO2 was sandwiched by the bottom ITO row selection line in horizontal direction and top Ti input line in vertical direction. As the quality of PECVD SiO2 is not optimized, leakage happens between top and bottom layer when large voltage was applied on the dielectric, e.g. positive input voltage with negative row selection voltage or negative input voltage with positive row selection voltage. (a) (b) FIG.6.9. Transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after a annealing in O 2 at 250 C for 20 min (a) and annealing in O 2 at 300 C for 20min (b). 143

165 FIG SEM image of the intersection of input line and row selection line After Annealing in O2 At 350 C for 20 min & 50 min Figure 6.11 (a) and (b) shows the transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after a annealing in O2 at 350 C for 20 min and for 50min separately. It is obvious that the device begin to show on-off feature of TFT after annealing in O2 at 350 C. The on-off current ratio is 6 after annealing for 20 min, and further improved to above 10 3 after 50 min annealing. The two images also shows that the maximum drain current at VDS = 15V are similar for both annealing conditions, but annealing with shorter time (20min) shows much higher drain leakage current. This indicates that longer annealing at 350 C dramatically removes most of the surface residual Ga ions, but does not change the quality of IGZO thin film. With the VGS above VON, IGZO thin film with accumulation layer is more conductive than the residual Ga ions, and dominate the conduction between 144

166 drain and source, that explain the similar maximum drain current. Besides, we also notice that the device annealing in O2 shows lower gate leakage (~10-9 A) compared with the short direct channel TFT annealed in air at 300 C for 30 min demonstrated in last chapter (10-7 A). The reason is that ambient O2 during annealing will oxidize more Ga ions and prohibit the ions diffusing further into SiO2 film. (a) (b) FIG Transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after a annealing in O 2 at 350 C for 20 min (a) and for 50min (b) After Annealing in O2 At 400 C for 10 min Figure 6.12 shows the transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after another annealing in O2 at 400 C for 10 min. The drain current is increased to above 10-5 A, but the drain leakage current also increased from A to 10-7 A. It is postulated that such a high temperature tends to increase the concentration of oxygen vacancies and releases more mobile electrons [146]. The increase of mobile electrons also results in a negative shift of VON, which is demonstrated by comparing Figure 145

167 6.12 and Figure Besides, the curves exhibit negative VON shift during gate voltage sweep. The possible reason is that at positive gate bias, electric field induced extra Ga ions into SiO2 layer, which attract more mobile electron at the IGZO/SiO2 interface and leads to higher drain current. FIG Transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after a annealing in O 2 at 400 C for 10 min Compare of Transfer Characteristics at Different Vr The effect of row selection voltage Vr on the function TFT performance is demonstrated in Figure The drain current and gate leakage current with sweeping gate bias at varies Vr are shown respectively in Figure 6.13 (a) and (b). The idea of the design is using the transmission gate as a switch to turn the desired row on and off. If the row selection voltage is low, transmission gate is off, and the input will not interrupt the logic gates on this row. However, even the drain leakage is very low (10-12 ~10-9 A), the leakage current still has enough time to charge or discharge the gate of 146

168 function TFT during the gate bias sweep of IdVg characterization. For high speed VLSI, the cycle time is in the order of ps or ns, so the leakage current does not have enough time to charge or discharge the capacitor. However, for the transfer characterization, the gate voltage sweep duration is in seconds, so the transmission gate does not act as a row switch as we expect. High frequency AC test or shot pulse as input should be applied to test the function of the transmission gate. (a) (b) FIG Transfer characteristics of drain current (a) and gate leakage current (b) at varies row selection voltage Vr. But form Figure 6.13 (a), we can still conclude that, at higher Vr, the drain current of function TFTs shows lower VON, and reaches higher drain current, which means that at higher Vr, the transmission gate is fully on, and the input signal can pass through it to the gate of the function TFT faster; while at lower Vr (-10V), the transmission is off, and the input signal takes longer time to charge the gate of function TFT, and the effective gate 147

169 voltage reached on the gate of function TFT is lower. Figure 6.13 (b) demonstrates that device at more negative Vr shows higher gate leakage current at positive gate bias, the reason has been explained before that the leakage occurs in the SiO2 dielectric between input line and row selection line, and higher electrical potential difference results in higher leakage current. 6.5 Conclusions In this chapter, laser interference lithography was introduced in the fabrication of α- IGZO TFTs to replace the traditional photo-lithography for the IGZO active layer patterning by using 325nm He-Cd layer and Lloyd-mirror interferometer setup. Diluted photoresist was applied to ensure the interference pattern quality, and 2D array of IGZO islands was successfully fabricated after wet etching. The design of logic gate array based on laser interference patterned IGZO layer was also proposed and the transfer characteristics of function TFT in the inverter gate pixel were presented. The result shows that the device best on-off feature of TFTs when annealing in O2 at 350 C for 50 min, with on-off current ratio above Lower temperature annealing was not able to remove most of the residual Ga ions, while higher temperate created more oxygen vacancies in IGZO and made it too conductive, which result in higher leakage current and negative shift of VON. Besides, the Ga ion in SiO2 layer will also contribute to the VON variations by external electric field. To test the functionality of transmission gate, high frequency AC input is necessary. Furthermore, dielectric layer with good quality is especially essential for this logic gate arrays because the intersection of ITO routing lines and metal routing lines are inevitable, and leakage between this two layers will degrade the device performance and function of logic gates. 148

170 CHAPTER 7 CONCLUSIONS AND FUTURE WORKS 7.1 Conclusions The goal of the research presented in this dissertation is to simulate and fabricate short channel α-igzo thin film transistors. Focused ion beam was applied to define the channel and laser interference lithography was used to pattern the IGZO active layer. Electrical characterization was carried to demonstrate the switch ability of the short channel TFTs and the impact of Ga ions induced by FIB. In order to fabricate α-igzo TFTs with better stability, understanding how the trapped charge at the IGZO/SiO2 interface and in the dielectric is necessary by using the proper simulation model. The subgap density-of-states model, including exponentially distributed band-tail states (gcba) right below the conduction band minimum and the Gaussiandistributed donorlike OV states (ggd) in the bandgap, were utilized in the Synopsys Sentaurus TCAD simulation. For long channel TFTs, the result fit the experiment date very well, it indicates that the carrier density of IGZO with 25 mtorr oxygen partial pressure during PLD deposition is cm -3, and the maximum value of density of conduction band-tail states is cm -3 ev -1. The donor state locates 0.1eV below the conduction band minimum with peak value of density of state as cm -3 ev -1. It also presents that the trapped charge density at the interface is determined by trapping, detrapping of the interface state and donor state ionization. When the Fermi level dropped close to or below the donor state, donor ionization contributes more free electrons to be trapped by the interface states. For short channel TFTs milled by FIB, the implanted Ga ion during the milling plays an important role for the device performance. Induced Ga ions, along with other mobile charges created by tunneling or impact ionization tend to induce more 149

171 electrons accumulated at the interface, and extend the linear region of the output characteristics. Besides, the milling also introduces damages to the IGZO and reduces the mobility of the channel. To fabricate device with channel length below 1 μm, we applied focused ion beam to define the channel, which is photoresist free, fast and can be processed under room temperature. The sample fabricated for milling has glass substrate with 130~160nm ITO coated as the gate material. 100nm SiO2 was deposited by PECVD as the dielectric, and 40nm or 100nm IGZO thin film was deposited by PLD for active layer, followed by 180nm Ti deposition by electron beam evaporation. With high ion energy (30 kev) and current (30 pa), the milling etch through to the substrate, and one-side-channel or two-sidechannel were created depends on whether the IGZO layer is wider than metal line on one side or on both sides. The result shows that after annealing in air at 300 ºC, the devices shows best performance with on-off current ration above However, the annealing in high temperature also diffuse more surface residual Ga ion into dielectric, and increase the gate leakage current. Besides, Ga ions implanted into the IGZO also reduce the density of oxygen vacancies and positively shifted the VON. The leakage current may occur between gate and drain, or gate and source, depends on the beam quality. Ideally, the beam should be vertical to the sample surface, which leaves less residual Ga ion on the side wall of milled trench. However, the ion beam incident angle changes while moving the sample and introduce more surface Ga ion on one side and results in more leakage. The effective channel length of side-channel TFTs is determined by the length of trench beyond the metal line, and two-side channel also shows higher drain current and subthreshold swing. 150

172 For direct-channel TFTs, low ion energy (16kV) and current (11pA) was applied for the milling to guarantee the precise control of etching depth. The milling stopped in the IGZO, a direct channel was created between drain and source, which is wider and prohibits the current crowding effect of side-channel TFTs. We demonstrated that after annealing in air at 300 ºC for 30 min, it reaches on-off ratio of 10 5, and subthreshold swing of 0.29V/decade. The drain current (10 6 A) is one order of magnitude higher than that of sidechannel TFTs (10 5 A). The device also shows positive shift of VON and increased gate leakage current along with increasing annealing temperature. To increase the flexibility of TFT dimension modification in circuit and save the IGZO active layer mask design, laser interference lithography with Lloyd-mirror interferometer was applied to pattern the IGZO. By using the He-Cd 325nm laser, and set the angles of both mirror and substrate stage to 80 º, 2D arrays of diluted photoresist pattern was created on top of IGZO thin film. The AFM image shows that the thickness of photoresist is 250nm and the periodicity of the array is 2.5 µm. After wet etching, the array of IGZO islands with the same periodicity was fabricated. Compared with common method to pattern small features such as electron beam lithography or UV lithography, this method is simpler and does not need mask. The function TFT of the inverter gate pixel in the logic gate array was tested, and it shows the best performance after in O2 at 350 C for 50 min, with on-off current ration above 10 3.Higher temperature results in more oxygen vacancies in IGZO and the TFT begin to lose the switch feature due to the higher conductivity of channel. 7.2 Suggestions for Future Work Based on the result presented in this dissertation, there are several further research topics worth further investigating. 151

173 7.2.1 Different Dielectric Material with Better Quality As demonstrated in the result, the leakage current through the dielectric due to the implanted Ga ion from the FIB milling limits the device performance. The SiO2 thin film deposited by PECVD at low temperature (300 ºC) is not dense enough, thus the Ga ions diffuses easily in the SiO2, especially after annealing. SiO2 or Al2O3 deposited by atomic layer deposition (ALD) can be tried to improve the dielectric quality Further Investigation on the Material We proposed that Ga ion diffusion inside both IGZO and dielectric during annealing, to verify and analyze the Ga ion distribution quantificationally, energy dispersive x-ray spectroscopy analysis (EDS) or secondary ion mass spectrometry (SIMS) can be performed to better understand the change of the thin film quality. Besides, Hall measurement is also useful to determine the mobility of IGZO before and after the FIB milling and how it is affected by annealing. To compensate the positive shift of VON by incorporation of Ga ion after the annealing below 400 ºC, lower oxygen partial pressure can be applied in the IGZO deposition Improvement on the Profile of IGZO Islands In this research, after the photoresist was patterned by laser interference lithography, the wet etching was applied to define the IGZO islands, which causes undercutting of the IGZO layer by the same distance as the etch depth. This is demonstrated in Figure 7.1. When the size of the IGZO island is further shirked and comparable with the thin film thickness as shown in the bottom picture of Figure 7.1, the island size would be out of control. It also leaves less space for FIB milling and contact area with metal. To overcome this, dry etch such as low power RIE can be tried to get straight side wall of IGZO island. 152

174 Alternative approach is to use lift-off, which requires thicker photoresist. Either negative photoresist or image reversal photoresist combing with reversal bake can be used with lower concentration of solvent. To fully expose the thicker photoresist, laser with higher power is necessary. FIG.7.1. Schematic of isotropic wet etching profile for IGZO islands with larger size (top) and smaller size (bottom) Better Control of FIB Milling In this research, thicker IGZO (100nm) for the direct channel TFT milling, because the Ga ion beam etches amorphous IGZO very fast, in order to make the etching remove all the metal and stopped in the active layer, thicker IGZO is necessary to sacrifice. However, the shortcoming is that the remaining IGZO channel thickness is hard to control. The change for ion beam quality after sample moving will also results in different milling depth 153