AN ABSTRACT OF THE THESIS OF. Rick E. Presley for the degree of Master of Science in

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2 AN ABSTRACT OF THE THESIS OF Rick E. Presley for the degree of Master of Science in Electrical Engineering and Computer Science presented on February 27, Title: Transparent Electronics: Thin-Film Transistors and Integrated Circuits Abstract approved: John F. Wager This thesis focuses on two aspects of transparent electronics, SnO 2 transparent thin-film transistors (TTFTs) and transparent circuits. Both depletion- and enhancement-mode SnO 2 TTFTs are realized. The maximum effective mobility for the depletion- and enhancement-mode devices are 2 cm 2 V 1 s 1 and 0.8 cm 2 V 1 s 1, respectively. A variety of techniques to decrease the carrier concentration in the SnO 2 channel are investigated. However, the only successful technique is to decrease the channel thickness, which effectively decreases the channel conductivity, and is the procedure employed for successful realization of an enhancement-mode TTFT. The second part of this thesis focuses on the fabrication procedure and the electrical characteristics of transparent circuits, which include inverters and ring oscillators. These circuits are highly transparent, exhibiting 75% optical transmittance in the visible portion of the electromagnetic spectrum, and are fabricated using indium gallium oxide as the active channel material and standard photolithography techniques. The n-channel indium gallium oxide thin-film transistors exhibit a peak incremental mobility of 7 cm 2 V 1 s 1 and a turn-on voltage of 2 V. A five-stage ring oscillator circuit (which does not employ level-shifting) is fabricated, and exhibits an oscillation frequency of 2.2 khz with the gate and drain of the load transistor

3 biased at 30 V; the maximum oscillation frequency observed is 9.5 khz, with the gate and drain of the load transistor biased at 80 V.

4 c Copyright by Rick E. Presley February 27, 2006 All rights reserved

5 Transparent Electronics: Thin-Film Transistors and Integrated Circuits by Rick E. Presley A THESIS submitted to Oregon State University in partial fulfillment of the requirements for the degree of Master of Science Completed February 27, 2006 Commencement June 2006

6 Master of Science thesis of Rick E. Presley presented on February 27, 2006 APPROVED: Major Professor, representing Electrical Engineering and Computer Science Director of the School of Electrical Engineering and Computer Science Dean of the Graduate School I understand that my thesis will become part of the permanent collection of Oregon State University libraries. My signature below authorizes release of my thesis to any reader upon request. Rick E. Presley, Author

7 ACKNOWLEDGMENT I would like to thank my major professor, Dr. John F. Wager for providing the opportunity to work on this research topic and providing the funding and support for this research. Without this funding and support this research could not have been completed. I would also like to thank Hai Chiang and David Hong for all the helpful discussions and providing training on the equipment. I would like to thank Robert Kykyneshi from the physics department at Oregon State University with providing the optical measurements presented in this thesis. I would like to acknowledge Chris Tasker, who keeps the lab running, and Manfred Dittrich for making shadow masks and other parts used to complete this work. This work was funded by the U. S. National Science Foundation under Grant No. DMR , by the Army Research Office under Contract No. MURI E G3, and by the Hewlett-Packard Company.

8 TABLE OF CONTENTS Page 1. INTRODUCTION LITERATURE REVIEW Thin-film transistor operation Inverter operation Ring oscillator operation Previous reported TFTs based on wide band gap semiconductors ZnO based thin-film transistors Tin oxide based thin-film transistors Indium gallium zinc oxide thin-film transistors Zinc tin oxide thin-film transistors Thin-film transistors fabricated using zinc indium oxide Tin oxide material properties and conventional applications Tin oxide as a transparent interconnect Tin oxide as a gas sensor Tin oxide as a window coating Pentacene organic ring oscillators Conclusions EXPERIMENTAL TECHNIQUE Thin film deposition techniques Physical vapor deposition techniques Thermal evaporation Activated reactive evaporation Radio frequency sputtering Direct current sputtering Chemical vapor deposition techniques Plasma-enhanced chemical vapor deposition Etching processes Chemical etch

9 TABLE OF CONTENTS (Continued) Page Physical etch Reactive ion etch Photolithography techniques Types of photoresist Exposure and development Film patterning Electrical characterization Turn-on voltage Mobility Incremental mobility Average mobility Saturation mobility Drain current on-to-off ratio Operating frequency Conclusions TIN OXIDE TRANSPARENT THIN-FILM TRANSISTORS SnO 2 TTFT device fabrication SnO 2 TTFT electrical characteristics and discussion Conclusions TRANSPARENT CIRCUITS Transparent circuit fabrication Electrical characterization and discussion Conclusions CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK Conclusions Recommendations for future work

10 TABLE OF CONTENTS (Continued) Page BIBLIOGRAPHY APPENDICES

11 LIST OF FIGURES Figure Page 2.1 A bottom-gate thin-film transistor structure and several energy band diagrams as viewed through the gate of the TFT. (a) TFT structure. (b) Energy band diagram when biased in equilibrium. (c) Energy band diagram when a negative voltage is applied to the gate. (d) Energy band diagram when a positive voltage is applied to the gate contact A theoretical transfer curve and a circuit representation illustrating the essential features of the inverters employed in this thesis. Both the control and load transistors are n-channel, accumulationmode TFTs, operating in enhancement-mode, i.e., possessing positive turn-on voltages Schematic representation of a ring oscillator showing the voltages and currents present at different times throughout device operation Schematic drawing showing a parallel plate cold-wall plasma-enhanced chemical vapor deposition system. This configuration is used to deposit silicon dioxide used as a gate insulator in the transparent circuits Pattern transfer using positive and negative photoresist Log(I D ) versus V GS plot for an IGO TFT indicating the turn-on voltage, and leakage current/noise floor SPICE simulation output for an inverter stage, indicating how rise and fall times are measured. The solid line is the output voltage from the inverter. The dashed trace is the input voltage to the inverter stage, and the gray solid line indicates the switching voltage for the inverter stage Drain current-drain voltage (I DS -V DS ) characteristics for a SnO 2 TTFT with a SnO 2 channel layer that is 10 nm thick, deposited by RF magnetron sputtering, and rapid thermal annealed in O 2 at 600 C. The channel length and width are 1524 µm and 7620 µm, respectively. V GS is decreased from 40 V (top curve, showing maximum current) to 0 V in 5 V steps

12 LIST OF FIGURES (Continued) Figure Page 4.2 Log(I DS )-V GS and Log(I GS )-V GS characteristics at V DS = 35 V for a SnO 2 TTFT with a channel width-to-length ratio of 5. Inset shows an extrapolation of the linear portion of an I DS -V GS curve, resulting in an estimated threshold voltage of V T 10 V. The SnO 2 channel layer is 10 nm thick, deposited by RF magnetron sputtering, and rapid thermal annealed in O 2 at 600 C Optical transmittance as viewed through the ITO source/drain and the channel of a SnO 2 TTFT. Curve (a) is corrected for reflectance, i.e., T / (1 - R), whereas curve (b) is the raw transmission through the entire stack, including the substrate. Inset illustrates the bottomgate TTFT structure and biasing scheme employed X-ray diffraction patterns obtained from two sputter-deposited SnO 2 thin films which are either furnace or rapid thermal annealed (RTA) at 600 C, and for a SnO 2 thin film prepared by evaporation of SnO 2 powder in a Torr pressure of microwave-activated N 2 and subsequently furnace annealed at 600 C. The post-deposition anneal leads to increased crystallinity of the sputtered films, whereas films prepared by activated reactive evaporation in N 2 remain amorphous after annealing Schematic representation of (a) cross-sectional and (b) a plan view for a transparent inverter, where W 1 and W 2 are the widths of the load and control transistors respectively, L OV is the source/gate or drain/gate overlap, and L is the channel length The optical transmittance versus wavelength through the source/drain (black) and channel (grey) regions of IGO TTFTs. Both regions exhibit average transmittance in the visible portion of the electromagnetic spectrum of 75%. (Inset) Glass substrate containing two ring oscillators, three inverters, and several discrete transistors resting atop the label Transparent Circuits Log(I D )-V GS transfer curves with V DS = 1 (square symbols) and 20 V (triangle symbols) for an IGO TTFT. The channel width and length for this device are 2400 and 60 µm, respectively. (Inset) Incremental mobility versus gate voltage, extracted from the I D -V GS data with V DS = 1 V

13 LIST OF FIGURES (Continued) Figure Page 5.4 Transfer curve for a transparent inverter fabricated using IGO TTFTs and with V DD and V load = 30 V. (Inset) Inverter gain magnitude as a function of V DD Oscillation frequency as a function of V DD for a five-stage ring oscillator fabricated using IGO TTFTs. (Inset) Output characteristic of the transparent ring oscillator when V DD = V load = 30 V Oscillation frequency as a function of the channel length for a fivestage ring oscillator via SPICE simulation using a width-to-length ratio of 40 for the control transistor, width-to-length ratio of 10 for the load transistor, a overlap capacitance of 70.8 nfcm 1, mobility of 2.55 cm 2 V 1 s 1 for both transistors, a turn-on voltage of 2 V for both transistors, and biased at 30 V Oscillation frequency as a function of the contact overlap for a fivestage ring oscillator using SPICE with a width-to-length ratio of 40 for the control transistor, a width-to-length ratio of 10 for the load transistor, a channel length of 60 µm, a mobility of 2.55 cm 2 V 1 s 1 for both transistors, a turn-on voltage of 2 V for both transistors, and biased at 30 V

14 LIST OF TABLES Table Page 2.1 Wide band gap-based TFTs, processing methods employed, and electrical performance characteristics for several different channel materials. The maximum processing temperature, deposition method, mobility, drain current on-to-off ratio, and threshold voltage are included A summary of pentacene-based ring oscillator device geometry and performance. The mobility, channel length, channel width, contact overlap, use of level-shifting circuitry, and propagation delay are included

15 TRANSPARENT ELECTRONICS: THIN-FILM TRANSISTORS AND INTEGRATED CIRCUITS 1. INTRODUCTION Imagine a monitor or television as thin as a sheet of glass. This futuristic idea may not be that far from reality. With the recent demonstration of transparent thinfilm transistors (TTFTs) and transparent circuits, as presented in this thesis, this hypothetical display is one step closer to being realized. The main focus in the transparent electronics field has been with respect to zinc oxide TTFTs. [1, 2, 3, 4, 5, 6, 7] However, this is only one out of many possibilities in a new group of materials designated as heavy metal cation (HMC) oxides. [8, 9, 10] A portion of this thesis is devoted to a discussion of the development of tin oxide (SnO 2 ), another example of a HMC oxide. Current research at Oregon State University involves the development of amorphous multicomponent HMC (a-mhmc) oxides for transparent electronics applications. TFTs and TTFTs fabricated with a-mhmc oxide channel layers such as zinc tin oxide (ZTO) and zinc indium oxide (ZIO) exhibit improved performance compared to when simple HMC oxides are used as channel layers. [11, 12] An important transparent electronics concept is manufacturability. Can TTFT devices and circuits be processed using conventional techniques? The answer is yes. Work presented in this thesis shows that conventional photolithography techniques can be used to pattern these materials. Transparent inverters and five-stage ring oscillators patterned using photolithography are demonstrated. These transparent devices and circuits are fabricated using indium gallium oxide (IGO) as a channel layer. IGO is another example of an a-mhmc oxide. This thesis is organized as follows. Chapter 2 provides background information including overviews of thin-film transistor operation, previous work in the transparent

16 2 electronics field, material properties of SnO 2, past applications of SnO 2, and previous work on organic ring oscillators for a comparison of the work presented in this thesis. Chapter 3 consists of a discussion of thin film deposition methods and device characterization procedures. Chapter 4 describes results obtained with regard to the SnO 2 TTFTs developed in this work. Chapter 5 presents the results obtained from the fabrication of transparent inverters and transparent ring-oscillators. Chapter 6 consists of a summary of the conclusions drawn from the experiments performed for this thesis and recommendations for future work on transparent electronics.

17 3 2. LITERATURE REVIEW This chapter provides a background of thin-film transistor and simple circuit operation. Also included is a summary of previous work in the transparent electronics field. The material properties of SnO 2 and conventional applications in which this material is employed are also presented. Finally, previous work related to organic ring oscillators is summarized so that it can be compared to results obtained in this thesis. 2.1 Thin-film transistor operation Figure 2.1 shows the basic layout of a bottom-gate thin-film transistor (TFT) and energy band diagrams through the gate of an n-type accumulation-mode TFT under three modes of operation. Figure 2.1b shows the equilibrium energy band diagram, i.e., no bias is applied to the gate contact. As a negative bias is applied to the gate, delocalized electrons in the channel are repelled from the semiconductor/gate interface and create a depletion region, of positive charge, as indicated by the positive curvature in the conduction and valence bands in Fig. 2.1c near the insulator. When a positive voltage is applied to the gate contact, delocalized electrons in the channel are attracted to the semiconductor/insulator interface, creating electron accumulation at the interface, as indicated by the negative curvature in the conduction and valence bands in Fig. 2.1d near the insulator. The delocalized electrons that are accumulated near the semiconductor/insulator interface when a positive voltage is applied to the gate contact provide a path for current conduction, which is denoted as the channel. As a positive voltage is applied to the drain contact of the TFT, these delocalized electrons in the accumulation layer are extracted from the channel, giving rise to drain current through the TFT. At small positive drain voltages, i.e., voltages significantly less than the gate voltage minus the turn-on voltage, V DS << V GS - V ON, the drain current conduction can

18 4 (a) Channel (b) ITO/Source ITO/Gate SiO 2 Glass ITO/Drain E C E F E V Gate Insulator Semiconductor (c) (d) E C E F E C E F E V E V Gate Insulator Semiconductor Gate Insulator Semiconductor Figure 2.1: A bottom-gate thin-film transistor structure and several energy band diagrams as viewed through the gate of the TFT. (a) TFT structure. (b) Energy band diagram when biased in equilibrium. (c) Energy band diagram when a negative voltage is applied to the gate. (d) Energy band diagram when a positive voltage is applied to the gate contact.

19 5 be modeled as a linear relationship as is given by I DS = (1/2)µC ox (W/L)(2(V GS V ON )V DS V 2 DS), (2.1) where the turn-on voltage (V ON ) is the voltage at which current conduction begins to increase with an increase in the gate voltage and is discussed in further detain in Section 3.2.1[7], C ox is the oxide capacitance, µ is the mobility of the electrons, W is the width of the channel, L is the length of the channel, V GS is the gate to source voltage, and V DS is the drain to source voltage. When the drain voltage reaches the pinch-off voltage, i.e., the voltage at which the channel near the drain is depleted of carriers, the drain current saturates, thus becoming independent of the drain voltage, and is given by I DS = (1/2)µCox(W/L)((V GS V ON ) 2 ). (2.2) Transistors are classified into two different types, based on whether drain current flows through the TFT when no voltage is applied to the gate. If the TFT is on, i.e., drain current flows through the TFT when no voltage is applied to the gate, the TFT is distinguished as a depletion-mode device. If the TFT is off, i.e., only leakage current flows through the TFT with no voltage applied to the gate, the TFT is classified as an enhancement-mode TFT. 2.2 Inverter operation An inverter is the simplest electronic circuit possible, consisting of a series combination of a control transistor and a load, which is often another transistor. An inverter is the most basic digital electronic circuit building block, allowing for the creation of more complex logic. There are several different configurations for inverters, as is detailed in Sedra and Smith. [13] Only one configuration involving an enhancement-mode control and load transistor is discussed in this thesis. Figure 2.2 displays a circuit representation of an inverter along with a elucidatory transfer curve. In Fig. 2.2, the upper transistor is referred to as the load

20 6 transistor, and the lower transistor is denoted as the control transistor. These names are an accurate description for the role assumed by each transistor in the circuit. The load transistor provides a time-invariant nonlinear resistive load via application of a constat DC bias to its gate. The control transistor operates as a switch whose state is established by the polarity and magnitude of the applied gate voltage, which constitutes the inverter input. When the gate input voltage to the control transistor is below the turn-on voltage of the control transistor, negligible current flows through the load transistor so that a minimal voltage drops across the load transistor, resulting in the high output value indicated in Fig When the input gate voltage exceeds the turn-on voltage of the control transistor, the control transistor turns on and current starts to flow through both the load and control transistors. As the input gate voltage increases, but yet stays below the pinch-off voltage, V DS = V GS - V ON, the inverter current continues to increase with a concomitant decrease in the output voltage, as is shown in Fig Once the input gate voltage reaches the pinch-off voltage, the inverter current saturates, as does the output voltage, resulting in a low output value, as indicated in Fig An important characteristic of an inverter is gain. The gain is essentially the abruptness in which an inverter switches from on to off. A larger gain results in a more ideal transfer curve, approximating a step function in the ideal limit. Another important property of an inverter is the switching voltage, which is the voltage beyond which the inverter output begins to decrease. This switching voltage corresponds to the turn-on voltage of the control transistor. Both the inverter gain and the switching voltage are indicated in Fig Ring oscillator operation A ring oscillator consists of an odd number of inverters connected in series. The output of one inverter is connected to the input of another inverter, with the output of the last inverter connected to the input of the first inverter as shown in Fig.

21 7 high Vout gain = dvout dvin load bias input load output control low Vin switching voltage Figure 2.2: A theoretical transfer curve and a circuit representation illustrating the essential features of the inverters employed in this thesis. Both the control and load transistors are n-channel, accumulation-mode TFTs, operating in enhancementmode, i.e., possessing positive turn-on voltages.

22 8 V dd T2 I1 T4 I2 T6 I3 Vout V1 T1 V2 T3 V3 T5 t=0 V1 = 0 I1 = small t=τp V2 = high I2 = large t=2τp V3 = low I3 = small Figure 2.3: Schematic representation of a ring oscillator showing the voltages and currents present at different times throughout device operation A ring oscillator is used to assess the speed of an integrated circuit technology. The oscillation frequency of a ring oscillator is related to the switching speed of the transistors comprising the ring oscillator. In turn, the switching speed of a transistor is based on channel mobility, parasitic capacitances, and device dimensions. A brief discussion of ring oscillator operation is presented here. For a more thorough discussion see, Sedra and Smith [13]. The voltages and currents present in a ring oscillator at various times are displayed in Fig At time t = 0, no voltage is applied to the input of the first inverter, so that control transistor T1 is off. Since T1 is off, only a small amount of leakage current flows through this device. This small leakage current also flows through the load transistor T2, resulting in a negligible voltage drop across T2, thus producing a high output of the first inverter. At time

23 9 t = τ p, corresponding to one propagation delay or the time it takes for the output to switch from low to high, a high voltage is applied to the input of the second inverter. This high voltage turns on T3, thereby allowing current to flow through this second inverter. This current produces a voltage drop across T4, resulting in a low output voltage from the second inverter. At time t = 2τ p, the input of the third inverter is low yielding a high output voltage from the third inverter. This process continues until the output of the fifth inverter, which is high, is applied to the input of the first inverter at time t = 4τ p. This process constitutes a voltage whose oscillation continues as long as there are an odd number of inverters in series, and as long as the gain for each inverter stage is greater than 1. It should be noted that the oscillation frequency is equal to the inverse of 2nτ p, where n is the number of inverters in the ring oscillator. τ p is determined by both material properties and also by the device layout. Both the material properties and device geometry need to be considered when comparing ring oscillator frequencies. A large oscillation frequency does not necessarily mean superior device performance. The material property that determines τ p is mobility. Mobility is discussed in further detail in Section A higher mobility decreases the switching time, thereby increasing the operating frequency. The other important factor to consider when assessing oscillator frequency is device layout. The oscillation frequency is significantly affected by parasitic capacitances, which result from device layout. A large source-gate and/or drain-gate overlap increases the parasitic capacitance, thus decreasing the operating frequency of the ring oscillator. The operating frequency is also effected by the device dimensions, in particular, the width-to-length ratio of the control and load transistors. A straightforward method to increase the operating frequency of a ring oscillator is to decrease the channel length for the control and load transistors. As the channel length decreases, the propagation delay of each inverter stage decreases, since electrons do not have as far to travel across the channel, and the operating frequency increases.

24 Another factor that effects the ring oscillator operating frequency is the operating 10 voltage. As discussed in Section 3.2.2, mobility is dependant on the gate voltage applied to the transistor, and increases as the gate voltage increases. Consequently a higher operating voltage increases the ring oscillator operating frequency. Also, the width-to-length ratio of the load and control transistor can be adjusted to increase ring oscillator frequency. If the width of the load transistor is increased or the width of the control transistor is decreased the ring oscillator oscillation frequency increases but the voltage swing decreases. A sufficiently large voltage swing is required in order to sustain oscillations, i.e., the output voltage of one inverter has to be able to both turn-on and turn-off the control transistor of the following inverter, in order to sustain oscillations. In summary, when comparing different ring oscillator operating frequencies reported in literature, it is important to recognize that all of these factors, i.e., transistor dimensions (gate length and width-to-length ratio), parasitic capacitance (determined by source/gate and gate/drain overlap capacitance), and operating voltage, be taken into account in order to make an accurate comparison between different devices and technologies. 2.4 Previous reported TFTs based on wide band gap semiconductors A significant amount of work has been reported with regard to wide band gap semiconductors, both for use as transparent interconnects and also as TFTs. This section summarizes only the work regarding wide band gap semiconductors for use as TFTs, since this work is directly relevant to the research reported in this thesis. The materials that are currently being investigated as channel materials include zinc oxide, tin oxide, zinc indium oxide, zinc tin oxide, and indium gallium zinc oxide. Each of these materials is briefly discussed in the following sections and is also summarized in Table 2.1.

25 ZnO based thin-film transistors Zinc oxide (ZnO) is currently the most commonly reported wide band gap semiconductor employed as a TTFT channel material. In 2003, Hoffman et al. fabricated ZnO TTFTs by ion beam sputtering on glass substrates that had been coated with indium tin oxide and a superlattice of aluminum oxide and titanium oxide [2]. The channel material was deposited at near room temperature and then subjected to a 700 C rapid thermal anneal in oxygen to increase the channel resistance. The highest effective channel mobility achieved was 2.5 cm 2 V 1 s 1. These devices had a threshold voltage between 10 to 20 V, and an on-to-off ratio of These TTFTs exhibited little to no effect when exposed to light. Also in 2003, Masuda et al. demonstrated ZnO TFTs in which the ZnO layer was deposited by pulsed laser deposition (PLD). These devices used a double layer gate insulator consisting of silicon dioxide and silicon nitride to reduce gate leakage introduced by depositing ZnO directly onto the silicon dioxide. Masuda et al. found that the Zn diffused into the silicon dioxide, thereby increasing the leakage current, and that the introduction of a buffer layer of silicon nitride prevented Zn diffusion, thus decreasing the leakage current. The best field effect mobility obtained was 0.97 cm 2 V 1 s 1 with a threshold voltage of -1 V [3]. Additionally in 2003 Carcia et al. fabricated ZnO TFTs by rf magnetron sputtering on Si substrates in which the ZnO channel layer is deposited near room temperature. Their best devices exhibit field-effect mobilities of more than 2 cm 2 V 1 s 1 and an on-to-off ratio of 10 6 [1]. In 2003, Nishii et al. fabricated ZnO TFTs using PLD [4]. These devices employed a CaHfO x buffer layer between the ZnO channel layer and the amorphous silicon nitride gate dielectric to improve the channel mobility and decrease the processing temperature required to achieve good device performance. These devices were fabricated using conventional liquid crystal fabrication techniques, and mask layout. By using the CaHfO x buffer layer the field effect mobility is increased to 7 cm 2 V 1 s 1

26 12 when deposited at 300 C and hysteresis was minimized. When no buffer layer was used the films were too conductive, and possessed a large amount of hysteresis. The ZnO deposition temperature could be reduced to 150 C and no significant change in device performance was observed. In 2003, Norris et al. demonstrated a ZnO TTFT that had the channel layer deposited via spin-coating [5]. The device employed a staggered, bottom-gate configuration, and used a superlattice of aluminum oxide and titanium oxide as the gate dielectric. The channel was baked in air for 10 min at 600 C to oxidize the channel, then rapid thermal annealed to 700 C to improve crystallinity. The channel and source/drain regions were patterned using photolithography. The devices had an effective channel mobility of 0.2 cm 2 V 1 s 1 and exhibited a higher sensitivity to light when compared to ion-beam deposited channels. Norris et al. attributed this increased light sensitivity to increased surface roughness. In 2004, Kwon et al. fabricated TFTs using magnesium and phosphorous doped ZnO as a channel layer. The magnesium is used to increase the band gap and the phosphorous reduces the free carrier concentration. These TFTs were fabricated using a top-gate configuration and used hafnium oxide as the gate dielectric. The channel layer was deposited using PLD with a deposition temperature of 400 C. After deposition the channel layer was annealed to 600 C in the presence of oxygen to activate the phosphorous dopant and increase the resistance. The maximum field effect mobility achieved was 5.32 cm 2 V 1 s 1 [14] Tin oxide based thin-film transistors Even though ZnO is the most investigated wide band gap semiconductor for use in TFTs, other materials have been investigated as well. The following summarizes work related to tin oxide (SnO 2 ), another wide band gap semiconductor of specific relevance to this thesis.

27 13 In 1969, long before ZnO TFTs and TTFTs were investigated, Aoki et al. fabricated a tin oxide (SnO 2 ) TFT using a vapor phase reaction deposition methodology [15]. The substrates were glazed alumina and used a dual layer silicon monoxide and nitrocellulose gate dielectric. These TFTs operated as depletion-mode gate-controlled resistors, which could not be turned off and did not exhibit current saturation but which possessed a transconductance of 0.3 mmho. Since these devices could not be turned off and did not exhibit drain current saturation, they cannot really be considered to function as true TFTs. In 1996 almost 30 years after Aoki et al. demonstrated their SnO 2 TFT, Prins et al. fabricated a SnO 2 TFT using PLD of the SnO 2 channel onto a SrTiO 3 substrate [16]. The gate dielectric was PbZr 0.2Ti 0.8O 3, a ferroelectric material which allows the TFT to possess a memory. The TFT has a mobility of 5 cm 2 V 1 s 1 and an on-to-off ratio of 2. The TFT fabricated was a depletion-mode device. The voltage shift between the positive sweep and the negative sweep was 1.6 V Indium gallium zinc oxide thin-film transistors Another wide band gap semiconductor that has been reported as being used as a channel material in TTFTs is indium galium zinc oxide (InGaO 3 (ZnO) 5 ). In 2003, Nomura et al. fabricated a TTFT using a single crystal superlattice of InGaO 3 (ZnO) 5 by using a reactive solid-phase epitaxy process to deposit the epitaxial channel layer [17]. These devices employed a hafnium oxide gate insulator on a single-crystal yttriastabilized zirconia substrate. InGaO 3 (ZnO) 5 TTFTs exhibited a threshold voltage, on-to-off ratio, and field-effect mobility of 3 V, 10 6, and 80 cm 2 V 1 s 1, respectively. This is the highest reported mobility for a TTFT. In 2004, Nomura et al. demonstrated a flexible TTFT using an amorphous indium gallium zinc oxide channel material, deposited by PLD onto a polyethylene terephthalate substrate [18]. The devices utilized a yitrium oxide gate insulator. The devices were fabricated at room temperature, and exhibited a saturation mobility and

28 on-to-off ratio of 6-9 cm 2 V 1 s 1, 10 3 respectively. Only a small decrease in saturation mobility was observed while the substrate was flexed Zinc tin oxide thin-film transistors In 2005, Chiang et al. fabricated a TTFT using zinc tin oxide (ZTO), an amorphous wide band gap semiconductor, as the channel layer [11]. The ZTO was deposited using radio frequency magnetron sputtering. These devices utilized an ATO gate insulator, and exhibited a field-effect mobility of 5-15 cm 2 V 1 s 1 and cm 2 V 1 s 1 when annealed at 300 C and 600 C, respectively. ZTO TFTs have a turn-on voltage between -5 and 5 V, and have an on-to-off ratio greater than Thin-film transistors fabricated using zinc indium oxide Another wide band gap semiconductor that has been reported as being used as a channel material in TTFTs is zinc indium oxide (ZIO). Dehuff et al. demonstrated a TTFT using amorphous ZIO as the channel material in 2005 [12]. The ZIO channel was deposited using radio frequency magnetron sputtering. Both depletion- and enhancement-mode TTFTs were demonstrated. The TTFTs utilized an ITO-coated glass substrate, and a superlattice of ATO as the gate insulator. These TTFTs exhibited a large incremental mobility of cm 2 V 1 s 1, and cm 2 V 1 s 1 for enhancement- and depletion-mode devices, respectively. Dehuff et al. also reported the fabrication of ZIO TTFTs at room temperature. These TTFTs were enhancement-mode and had an incremental mobility of 8 cm 2 V 1 s Tin oxide material properties and conventional applications There are two forms of tin oxide, differing by the electronic state of the tin atom. When the tin atom is in the 4 + oxidation state, the tin oxide that is formed is stannic oxide (SnO 2 ) [19]. When the tin atom is in the 2 + oxidation state, stannous oxide (SnO) is formed [19]. Stannic tin oxide is a wide band gap semiconductor with

29 15 Table 2.1: Wide band gap-based TFTs, processing methods employed, and electrical performance characteristics for several different channel materials. The maximum processing temperature, deposition method, mobility, drain current on-to-off ratio, and threshold voltage are included. Channel Max Proc. Dep Mobility On-to-Off Threshold Ref Material Temp. ( C) Method (cm 2 /Vs) Ratio Volatge (V) ZnO Room Temp RFS a 2 f [1] ZnO 700 IBS b 2.5 g [2] ZnO 450 PLD c 0.97 f [3] ZnO 300 PLD c 7 f [4] (Zn,Mg)O 600 PLD c 5.32 f [14] ZnO 700 SC d 0.2 g [5] SnO 2 VPR e [15] SnO 2 PLD c [16] ZIO 600 RFS a h (-10) [12] ZTO 600 RFS a f [11] InGaO 3 (ZnO) PLD c 80 f [17] IGZO Room Temp PLD c 5.6 f [18] a radio frequency sputtering b ion beam sputtering c pulsed laser deposition d spin coating e vapor phase reaction f field-effect mobility g effective mobility h incremental mobility

30 16 a band gap of 3.6 ev [19], whereas stannous tin oxide has a band gap of ev. Stannic tin oxide has the rutile crystal structure, and starts to crystalize at 350 C, while the stannous form of tin oxide has the litharge structure. Stannic is the most common form of tin oxide and is the only form that is useful in gas sensing applications. The density of tin oxide is 6.99 g cm 3 [19]. Undoped, stoichiometric SnO 2 is an insulator, however, oxygen vacancies render it n-type. The formation energy of oxygen vacancies and tin intersticials is very low, so it is hard to deposit a stoichiometric film, and most films turn out to be conductive [19]. There are three major uses of tin oxide, gas sensors, transparent interconnects, and window coatings. These applications are discussed in the following sections Tin oxide as a transparent interconnect The most common transparent interconnect used today is indium tin oxide (ITO). Since indium is a rare metal and is quite expensive, a significant amount of research effort is being devoted towards the development of an alternative material to be used as a transparent interconnect. The most popular oxides that are being explored are zinc oxide and tin oxide. This section briefly describes techniques used to make tin oxide conductive for use as a transparent interconnect. Tin oxide is one of the materials being focused on as a alternative to ITO. The most common approaches to make tin oxide conductive is by doping with antimony as a cation dopant or fluorine as an anion dopant [19]. Even with these dopants the conductivity of SnO 2 is still lower than that of doped ZnO and ITO. Performance, process integration considerations, and cost normally determine which of these transparent conducting oxides are used. ITO has the highest conductivity of the transparent conductive oxides, but the limited amount of indium in the earth s crust is driving up the cost. ZnO has a higher conductivity than that of SnO 2, but ZnO is not very physically or chemically robust and can be etched very easily, so

31 process integration of ZnO can be challenging. In contrast, SnO 2 is chemically and physically robust Tin oxide as a gas sensor There are two types of gas sensing materials, surface sensing and bulk sensing [19]. In bulk sensing materials, their conductivity increases as a consequence of gas exposure due to the creation of bulk vacancies. An example of a bulk sensing material is titanium oxide [19]. Tin oxide is an example of a surface sensing material in which the surface conductivity is increased by reduction of the tin on the surface upon as exposure and the bulk of the material is unaffected by the presence of the gas. If the gas to be detected is an oxidizing gas the conductivity decreases upon gas exposure due to the formation of a depletion layer at the surface [19]. Tin oxide gas sensors are typically passive components. The tin oxide is intentionally doped to make it conductive. The type of dopant used can effect the sensors sensitivity to certain gases [19]. The conductivity of the SnO 2 is measured as the sensor is exposed to the gas. The tin oxide surface, when it is exposed to normal air atmosphere, adsorbs a layer of negatively charged O 2 atoms, leading to the creation of a depletion region at the surface and a corresponding decrease in the conductivity. When a reducing gas is then introduced, negatively charged surface oxygen atoms react with the gas and are replaced by other molecules which results in a decrease in the depletion layer and an increase in the conductivity [19] Tin oxide as a window coating Certain wide band gap oxide semiconductors have another useful characteristic. Since they have a wide band gap, the visible portion of the electromagnetic spectrum can pass through, but the infrared part is reflected. This is a useful property for window coating applications. Visible light is passed, but the infrared light, i.e., radiant heat is reflected, based on the plasma frequency of the material. The plasma fre-

32 18 quency is the frequency above which an electromagnetic wave is not be able to travel through a material. This phenomena is related to the frequency dependance of the dielectric constant of the material [20]. The dielectric constant of a material is a measure of the ability of a material to respond to an applied electric field. The frequency dependance of the dielectric constant of a material depends on the relaxation time of the material. At a given frequency, if the dielectric constant is positive, the electromagnetic wave is able to propagate through the material. However if the dielectric constant is negative, the electromagnetic wave cannot propagate in the material, but decays exponentially inside the material such that the incident wave is reflected from the material s surface [20]. The plasma frequency of a material is expressed as, ω p ((4πne 2 )/m) 1/2, (2.3) where n is the free electron density of the material and m is the mass of an electron [20]. The wavelength associated with the plasma frequency is given by, λ p (2πc)/ω p, (2.4) where c is the speed of light [20]. From Eqn. 2.3 it is eviden that the plasma frequency depends on the doping concentration of the material. A higher carrier concentration leads to a larger plasma frequency, which translates into a smaller critical wavelength at which electromagnetic radiation is reflected at the material s surface. Therefore the infrared transmission characteristics of a window can be tailored to a specific climate by changing the carrier concentration of the transparent coating deposited onto the window s surface. Tin oxide is the most widely used transparent semiconductor for this application due to its low cost, compared to ITO, and its chemically robust nature, compared to ZnO. 2.6 Pentacene organic ring oscillators A significant amount of research has been devoted to the realization of ring oscillators using organic filed-effect transistors (OFETs). The most common channel

33 19 material used in OFETs and OFET ring oscillators is pentacene. This section summarizes published literature related to pentacene OFET ring oscillators and thereby serves as a comparison to the inorganic TTFT ring oscillators presented in this thesis. Table 2.2 summarizes the results of published ring oscillators fabricated using pentacene as an active channel material. In 1999, Klauk et al. demonstrated a pentacene ring oscillator on a glass substrate using ion beam sputtered silicon dioxide as the gate insulator [21]. The pentacene OFETs have a field-effect mobility of 0.5 cm 2 V 1 s 1, and an on-to-off ratio of The pentacene OFETs are depletion-mode. Therefore, a level-shifting circuit is required to fabricate a ring oscillator. The control transistor has a channel length of 5 µm and a width of 800 µm, when the load transistor had a channel length of 30 µm and a width of 300 µm. The pentacene ring oscillators with level-shifting have a minimum propagation delay of 73 µs. This propagation delay is limited by the use of the level-shifting circuit, and not by the performance of the pentacene OFETs. In 2000, Gelinck et al. reported pentacene OFET seven-stage ring oscillators that have a frequency of 2 khz at a supply voltage of less than 5 V, with a channel length of 1 µm [22]. When the channel length is increased to 5 µm the frequency drops to 60 Hz. These devices were fabricated using a bottom-gate design, and deposited onto a glass substrate. The pentacene OFETs exhibited a mobility of 10 2 cm 2 V 1 s 1. After being exposed to air for one month the pentacene OFETs only showed a small degradation in performance. Also in 2000, Kane et al. demonstrated a five-stage OFET ring oscillator on a polyester substrate using pentacene as the active channel layer [23]. When biased at 20 V, these ring oscillators operated at a frequency of 1.7 khz, which translates into a propagation delay of 52 µs per stage. The pentacene OFETs had a mobility of 0.45 cm 2 V 1 s 1, and a threshold voltage of 3.2 V. Due to the positive threshold voltage of these p-channel pentacene OFETs, level-shifting circuits were incorporated into the ring oscillator design. The OFETs used to fabricate the five-stage ring oscillator had

34 20 a channel length of 10 µm. Kane et al. claim that a propagation delay of 52 µs is the shortest delay reported on plastic substrates. In 2000, Sheraw et al. reported pentacene OFET five-stage ring oscillators with a propagation delay as low as 40 µs on flexible substrates [24]. The pentacene OFETs exhibited a mobility of 0.4 cm 2 V 1 s 1, threshold voltage of 0.9 V and an on-to-off ratio of With the positive threshold voltage of these p-channel pentacene OFETs, the ring oscillators had to employ level-shifting circuitry. Sheraw et al. also report that the ring oscillators had a propagation delay of under 50 µs when biased at 8 V. These are very low propagation delays for pentacene circuits processed on flexible substrates. However, device dimensions were not specified for the ring oscillator circuit, so a direct comparison to other reports cannot be made. The propagation delay of a ring oscillator circuit is strongly based on the circuit layout and device geometries. Zschieschang et al. demonstrated pentacene OFET ring oscillators on flexible substrates using a printed gate electrode in 2003 [25]. The pentacene OFETs had a saturation mobility of 0.06 cm 2 V 1s 1, a threshold voltage of 1 V, and an on-tooff ratio of The ring oscillators were fabricated using pentacene OFETs with a channel length of 5 µm, channel width of 20 µm, and a contact overlap of 5 µm. The ring oscillators implemented a level-shifting circuit to accommodate the positive threshold voltage of the pentacene OFETs. The five-stage ring oscillators fabricated using a printed gate electrode had a propagation delay of µs. In 2004, Eder el al. demonstrated five-stage ring oscillators using both a paper substrate and a flexible polyetherether ketone film substrate. These five-stage ring oscillators used an organic pentacene channel layer [26]. The pentacene layer was deposited using thermal evaporation, and had a saturation mobility of 0.3 cm 2 V 1 s 1 and an on-to-off ratio of 10 6 when deposited onto a polyetherether ketone film. The OFET circuits fabricated on polyetherether ketone film employed a 5 µm channel length and had a contact overlap of 5 µ, and had an oscillation frequency of 4.5 khz,

35 Table 2.2: A summary of pentacene-based ring oscillator device geometry and performance. The mobility, channel length, channel width, contact overlap, use of levelshifting circuitry, and propagation delay are included. 21 Mobility Channel Channel Contact delay Level- Ref (cm 2 /Vs) Length(µm) Width(µm) Overlap(µm) (µs) shifting 0.5 a yes [21] 10 2a yes [22] 0.45 a yes [23] 0.4 a yes [24] 0.06 b yes [25] 0.2 b yes [26] a field-effect mobility b saturation mobility which translates into a propagation delay of 22 µseconds. Due to surface roughness the ring oscillators fabricated on a paper substrate had a channel length of 10 µm, and had a contact overlap of 10 µm. These ring oscillators had an oscillation frequency of 8 Hz, which is equivalent to a propagation delay of 12 milliseconds. All of these circuits employ level shifting due to the positive turn-on voltage of the p-channel pentacene OFETs. 2.7 Conclusions In this chapter basic operation of several different devices and circuits is presented, including thin-film transistors, inverters, and ring oscillators. A brief review of the literature pertaining to transparent electronics is presented. The material properties and conventional applications for tin oxide are discussed. Finally, a brief

36 review of pentacene ring oscillator literature is offered as a basis of comparison to the transparent ring oscillators presented in this thesis. 22

37 23 3. EXPERIMENTAL TECHNIQUE In this chapter the deposition techniques used to fabricate the devices presented in this thesis are discussed. Also device and integrated circuit figures-of-merit are presented and discussed. 3.1 Thin film deposition techniques This section contains information on the methods and tools used in the deposition of the semiconductor materials utilized in this work. These methods include physical vapor deposition, chemical vapor deposition, and photolithography Physical vapor deposition techniques A brief discussion of different physical vapor deposition (PVD) methods used for this work is presented. The PVD methods discussed include evaporation, radio frequency magnetron (RF), and direct current (DC) sputtering Thermal evaporation Thermal evaporation is a PVD method used to deposit materials with relatively low melting points. Evaporation is performed under high vacuum Torr. Evaporation of the material takes place as current is passed through a filament, or a boat, containing the material to be evaporated. As current flows through the boat the boat heats up, due to resistive heating, until the material either melts and evaporates or sublimes, i.e., changes directly from a solid to a vapor. The evaporation system used in this work is a VECO Thermal Evaporator. The system has three evaporation sources, which allows for deposition of multiple materials without breaking vacuum. This allows for higher efficiency and less contamination of the deposited films. Evaporation is an alternative method investigated for the deposition of SnO 2 and indium in this work.

38 Activated reactive evaporation Activated reactive evaporation (ARE) is another form of thermal evaporation. ARE also uses resistive heating to evaporate the source material. The only difference is that ARE uses a plasma source to ionize gas ions that reacts with the evaporated material. An example of a material deposited using ARE is titanium oxide. Titanium metal is evaporated and oxygen is ionized and reacts with the evaporated Ti, resulting in titanium oxide. ARE is investigated as an alternative method for depositing tin oxide. Tin metal is evaporated in the presence of activated O 2 ions to produce SnO 2 films. The ARE system at OSU has two thermal sources, and uses an electron cyclotron resonance (ECR) source to ionize the reactive gas Radio frequency sputtering RF sputtering uses a radio frequency power supply, operating at MHz, to generate a plasma, which creates ions which are used to sputter the target material. The ions are accelerated towards the target by a negative DC bias on the target due to the flux of electrons. The ions hit the target with enough energy to dislodge the target atoms, which are then redeposited onto the substrate. RF sputtering is performed under vacuum, typically between 1 mtorr and 50 mtorr, to improve the quality and the deposition rate of the deposited film. A lower pressure increases the mean free path, the distance between collisions, and results in the deposited species having more energy to diffse along the substrate surface in order to find the lowest energy state possible. A more thorough discussion of plasmas and sputtering can be found in Lieberman. [27] RF sputtering can be used to sputter both insulating and conducting targets, since charge does not build up on the surface of the target. The major disadvantages of RF sputtering are cost and deposition rate. A RF power supply is more expensive than an equivalent DC power supply, and the deposition rate is lower than

39 25 that obtained using DC sputtering, as a result of the alternating nature of the RF waveform Direct current sputtering The only major change from RF to direct current (DC) sputtering is the power supply used. In DC sputtering, as the name suggests, a DC power supply is used to create the plasma. The physics of the sputtering process is unchanged. Direct current sputtering allows for higher deposition rates and is less expensive than RF sputtering. Conventional DC sputtering can only be used to sputter conductive targets. The flux of electrons from the DC supply causes charge to build-up on the surface of an insulating target, rendering the plasma unstable so that it eventually extinguishes. One method used to sputter insulating targets using DC sputtering involves the use of a pulsed DC source. When using a pulsed DC source, the voltage is periodically pulsed positive for a very short time to remove the charge on the insulating target. This positive pulse duration is a very small fraction of the entire period, resulting in a higher sputter rate than that of RF sputtering. Another method utilized to allow DC sputtering of insulating targets is a secondary ion beam sputtering system. In this configuration, the plasma is generated in a chamber separate from that of the substrate. The ions are extracted from the plasma chamber and are accelerated towards the target. A neutralizer is used in this configuration to neutralize the ions, which eliminates the build up of charge on the surface of an insulating target. Therefore this configuration allows for sputtering of insulating targets, and is the configuration of the DC sputtering system used in this work Chemical vapor deposition techniques Unlike PVD, chemical vapor deposition (CVD) relies on a chemical reaction to deposit the film rather than a physical process. In CVD, multiple reactive gases

40 26 are combined and the reaction takes place at the heated substrate, resulting in the deposition of the film. There are many different types of CVD reactors including, atmospheric, low-pressure, and plasma-enhanced (PECVD). During this work only a PECVD system is used and is the only type of reactor discussed in this thesis Plasma-enhanced chemical vapor deposition In a PECVD system a plasma provides some of the activation energy required for the chemical reaction, in effect reducing the processing temperature required during the film deposition. PECVD systems allow for high deposition rates and the ability to deposit films on substrates with lower thermal stability than with other CVD systems.[28] Silicon dioxide (SiO 2 ) deposited in a PECVD system is used as a gate insulator for the transparent circuits presented in this thesis. The PECVD system at Oregon State University is a Semi Group PECVD system and uses silane and nitrous oxide as precursors. The chemical reaction to create silicon dioxide using these precursors is SiH 4 (gas) + 2N 2 O(gas) C,rf SiO 2 (solid) + 2N 2 (gas) + 2H 2 (gas). (3.1) The Semi Group PECVD system is a cold-wall reactor, the configuration of which is shown in Fig In a cold-wall reactor the chamber is actively cooled to reduce film formation on chamber walls, reducing a source of contamination. The PECVD system used for this research has been modified with an additional lamp heater to reduce particulate contamination, arising from poorly adhered films on the gas diffuser plate flaking off and being incorporated in the growing film. A detailed operating and maintenance procedure for the Semi Group PECVD system is presented in Appendix A.

41 27 Gas and RF inlet cooling water inlet cooling water inlet heater/bottom electrode Vacuum Pump gas diffuser plate/ top electrode Figure 3.1: Schematic drawing showing a parallel plate cold-wall plasma-enhanced chemical vapor deposition system. This configuration is used to deposit silicon dioxide used as a gate insulator in the transparent circuits Etching processes Etching is the process of removing material from a substrate. There are two major qualities that distinguish an etch process. These qualities are etch profile and selectivity. Etch profile refers to the topography of the etched film s surface, and is either isotropic or anisotropic. Isotropic etches remove the material in all directions at an equal rate. Anisotropic etches are directional etches; they remove the film in one direction much faster than in the other directions. Selectivity refers to how fast an etch process etches one film compared to the etch rate of a different film. There are three different types of etch processes discussed in the following sections, including chemical etch, physical etch, or a combination of both chemical and physical etches Chemical etch Often a chemical etch is referred to as a wet etch, since most chemical etches require the substrate to be exposed to a liquid etchant. Wet etches have a higher se-

42 28 lectivity than physical etches, with the ability to remove one film off of an existing film without damaging the bottom film. Chemical etches are commonly used to pattern devices with larger dimensions, since etch chemistries typically are well understood and greater selectivity can be achieved compared to physical etches. Wet etches are isotropic, which limits the minimum device dimensions that can be patterned. [28] Chemical etches are used to pattern gate contacts and channel layers in the transparent circuits described in Chapter 5. Both the gate contacts and the channel are etched using hydrochloric (HCl) acid. The gate contacts are etched using undiluted HCl, 37.5% HCl. When etching the channel layer, HCl is diluted with deionized water at a ratio of five parts deionized water to one part HCl Physical etch A physical etch, or dry etch as it is often called, uses a physical ion bombardment, i.e., sputtering, to remove unwanted material. A physical etch is an anisotropic etch, since the etch is directed in one direction. One disadvantage of a physical etch is poor selectivity. An example of a physical etching system is an ion beam etcher. An ion beam etcher uses a focussed beam of ions, as the name suggests, to sputter away unwanted material. No physical etches are used in this work, but the concept is presented to better understand the reactive ion etching process, which is used in this work Reactive ion etch Reactive ion etch (RIE) uses both a chemical and a physical process to remove unwanted material. In a RIE process, a reactive gas is introduced into the chamber and a glow discharge is created. The reactive gas reacts with the film and the ions created in the glow discharge are directed towards the substrate, weakening bonds and creating a more anisotropic etch. A RIE is used to etch the silicon dioxide gate dielectric in transparent circuits.

43 Photolithography techniques Photolithography is used in semiconductor processing to pattern films down to less than one micron. Photolithography involves transferring an image from a mask to the photoresist, an organic polymer which becomes soluble when exposed to ultraviolet light. The transparent circuits presented in this thesis are patterned using photolithography Types of photoresist There are two types of photoresist which differ from each other by the resulting pattern after development. A positive resist transfers an exact copy of the mask to the film, in other words what is exposed is removed in the developer. A negative photoresist transfers an inverted mask pattern to the film, or what is not exposed is removed while being developed. Figure 3.2 shows the pattern transfer for the different photoresist types Exposure and development Once the photoresist is spun onto the substrate, the pattern needs to be transferred into the resist. This is accomplished by exposure and development. Exposure refers to when the photoresist is placed under an ultraviolet light source. For a positive photoresist, the bonds in the exposed area are weakened. When using a negative resist, the bonds in the exposed area are cross-linked and become stronger. After the photoresist is exposed, the substrate is submersed in a developer bath. The developer removes the photoresist with the weaker bonds and leaves behind the desired pattern Film patterning The two methods used in this work to pattern thin films are etching and lift-off. Etching is the preferred process since the photoresist is spun on after the film has been deposited, which does not affect any of the deposition parameters. There is also no chance of contaminating the interface between the two films when etching is

44 30 Photoresist Film Substrate UV Light Mask Photoresist Film Substrate Positive Resist Negative Resist Photoresist Film Substrate Photoresist Film Substrate Film Substrate Film Substrate Figure 3.2: Pattern transfer using positive and negative photoresist.

45 31 employed. Lift-off is a technique used to remove unwanted material that cannot be etched. This technique requires pattering of the photoresist prior to the deposition of the film. After the film is deposited, the photoresist and unwanted film are removed by submersing the substrate in an acetone bath. After a long soak, the substrate is placed in an ultrasonic cleaner to help remove any remaining unwanted film. Liftoff has several disadvantages and is only used when etching is not feasible. One of these disadvantages is that the photoresist is on the substrate while the film is being deposited, which limits the deposition temperature. Another disadvantage of using lift-off is the possible contamination of the interface between the two films, since the photoresist is spun on before depositing the film. 3.2 Electrical characterization Electrical characterization is used to evaluate the performance of devices. The main figures-of-merit used to characterize a TTFT are turn-on voltage, mobility, and drain current on-to-off ratio. The main figure-of-merit used to characterize a ring oscillator is operating frequency. These figures-of-merit are discussed in the following sections Turn-on voltage Turn-on voltage (V ON ) is the voltage at which current conduction begins to increase with an increase in the gate voltage. [7] V ON is determined by plotting log(i D ) versus V GS and finding the voltage at which the drain current starts to increase from the leakage current/noise floor, as indicated in Fig A n-type device that has a positive turn-on voltage is distinguished as enhancement-mode and requires a gate voltage to be applied before drain conduction begins. When a n-type device has a negative turn-on voltage, it is identified as depletion-mode and requires a negative voltage to be applied to the gate to turn off the device.

46 Log(ID) -6-8 V ON -6-8 Log(IG) Leakae current/noise floor V GS (V) Figure 3.3: Log(I D ) versus V GS plot for an IGO TFT indicating the turn-on voltage, and leakage current/noise floor Mobility Mobility is a measurement of how fast carriers can move through a material. A higher mobility allows for a faster switching time, i.e., the time it takes for the device to toggle between the off state and on state. In the off state, a minimal amount of current flows through the device. In the on state, a significant amount of current flows. A larger mobility value means that the device can conduct more current. Three different mobilities used to characterize a device are incremental, average, and saturation mobility. [7] These mobilities are discussed briefly in the following sections. A more thorough discussion can be found in Hoffman s article. [7] Incremental mobility The incremental mobility is the mobility of differentially induced carriers introduced into the channel by a small increase in the gate voltage. [7] The incremental

47 mobility is calculated as [7] µ INC (V GS ) = G D (V GS) W L C I VDS 0 33, (3.2) where G D (V GS) is the change in channel conductance with a change in gate voltage as G D(V GS ) = G D(V GS ), V GS VDS 0, (3.3) where the channel conductance as a function of gate bias is given by [7] G D (V GS ) = I D, (3.4) V DS VDS 0 and where C I is the capacitance of the insulator, W and L are the width and length of the device, respectively, and VDS 0 indicates the device is biased in the linear regime of transistor operation Average mobility The average mobility is the average of all the carriers present in the channel and can be calculated as [7] µ AV G (V GS ) = G D (V GS ) W L C I(V GS V ON ) VDS 0. (3.5) Saturation mobility The saturation mobility is the least used type of mobility. It is extracted from an I D -V GS curve when the device is biased in saturation.[29] The saturation mobility is calculated as [29] µ SAT = 2m2 W L C I where m is the slope of the I DS versus V GS curve., (3.6) saturation Drain current on-to-off ratio The drain current on-to-off ratio is an indicator of how well a device will work as a switch. The drain current on-to-off ratio is obtained by plotting the log(i D )

48 34 versus V GS at a large V DS. A large drain current on-to-off ratio is required for certain switching applications, typically larger than 10 6 is preferred. The off current translates into how much power is lost when the device is off, whereas the on current indicates the maximum current drive for the device Operating frequency The operating frequency refers to the frequency of oscillation of a ring oscillator and is determined by the device physics, properties of the transistor, and the circuit layout. The operating frequency for a ring oscillator can be obtained as f = 1 T = 1 N2t d, (3.7) where N is the number of stages in the ring oscillator, and t d is the propagation delay for a single stage. SPICE simulation is an easy way to obtain an estimate of the propagation delay, as demonstrated in Fig The propagation delay for each stage is the sum of the rise time and the fall time of the output curve. The rise time and fall time is the amount of time between the input voltage switching and the switching voltage, when the output voltage reaches half of the maximum output voltage, as indicated in Fig Conclusions In this chapter the deposition techniques used to fabricate the devices presented in this thesis are discussed. These deposition techniques include physical and chemical vapor deposition, as well as photolithography. A brief discussion of mobility, turn-on voltage, on-to-off ratio, and operating frequency is presented.

49 Voltage (V) t r t f E-6 1.0E-5 1.5E-5 2.0E-5 2.5E-5 3.0E-5 Time (sec) 3.5E-5 4.0E-5 Figure 3.4: SPICE simulation output for an inverter stage, indicating how rise and fall times are measured. The solid line is the output voltage from the inverter. The dashed trace is the input voltage to the inverter stage, and the gray solid line indicates the switching voltage for the inverter stage.

50 4. TIN OXIDE TRANSPARENT THIN-FILM TRANSISTORS 36 This chapter is devoted to a discussion of the fabrication and characterization of SnO 2 TTFTs. 4.1 SnO 2 TTFT device fabrication Bottom-gate SnO 2 TTFTs are fabricated on glass substrates, manufactured by Nippon Sheet Glass Company, coated with 200 nm sputtered indium tin oxide (ITO) and a 220 nm atomic layer deposited superlattice of Al 2 O 3 and TiO 2 (ATO) provided by Planar Systems, Inc. The ITO and ATO layers constitute the gate contact and insulator, respectively. Typically, the channel layer is deposited by RF magnetron sputtering using a tin oxide target (Cerac) in Ar/O 2 (97%/3%) at a pressure of 5 mtorr, power density of 3 W cm 2, target-to-substrate distance of 7.5 cm, and no intentional substrate heating. The channel layers are typically nm thick. The channel length and width are 1524 µm and 7620 µm, respectively. Alternatively, SnO 2 channel layers are formed either by thermal evaporation at a pressure of 10 6 Torr or by activated reactive evaporation in either microwave-activated O 2 or N 2 at a pressure of Torr. In both cases, SnO 2 powder is used as the evaporation source material. After deposition of the SnO 2 channel layer the sample is annealed, typically via furnace or rapid thermal annealing (RTA) in O 2 at 600 C. Finally, ITO source and drain contacts are formed by ion-beam sputtering. 4.2 SnO 2 TTFT electrical characteristics and discussion Figure 4.1 displays the DC drain current-drain voltage (I DS -V DS ) characteristics for a SnO 2 TTFT. The slopes of most of the I DS curves shown in Fig. 4.1 are extremely flat at large V DS, indicating that a condition of hard saturation is achieved, due to complete pinch-off of the channel. However, the two uppermost I DS curves exhibit a small slope since the condition for pinch-off, i.e., V DS V GS - V T

51 IDS (µa) V DS (V) Figure 4.1: Drain current-drain voltage (I DS -V DS ) characteristics for a SnO 2 TTFT with a SnO 2 channel layer that is 10 nm thick, deposited by RF magnetron sputtering, and rapid thermal annealed in O 2 at 600 C. The channel length and width are 1524 µm and 7620 µm, respectively. V GS is decreased from 40 V (top curve, showing maximum current) to 0 V in 5 V steps. (where V T is the threshold voltage), is not achieved. It is evident from Fig. 4.1 that the TTFT is essentially off, at least on 90 µa scale used for this figure. This implies enhancement-mode behavior. A positive threshold voltage, V T 10 V, is obtained from extrapolation of the linear portion of the DC drain current-gate voltage (I DS -V GS ) characteristic, as shown in the insert of Fig. 4.2, indicating this to be an enhancement-mode device, i.e., negligible current flows at zero gate voltage; a positive gate voltage is required to turn on the drain current). However, as evident from the log(i DS )-V GS transfer characteristics shown in Fig. 4.2, the turn-on voltage, corresponding to the gate voltage at which the channel current first begins to increase [7], is approximately -20 V. Thus, a very large negative voltage is required to completely turn off the device. Note also from Fig. 4.2 that the gate leakage current for this device is very small, less than 1 na, and that the drain current on-to-off ratio is quite large, It

52 Current (A) I DS I GS IDS (µa) V T ~ 10 V V GS (V) V GS (V) Figure 4.2: Log(I DS )-V GS and Log(I GS )-V GS characteristics at V DS = 35 V for a SnO 2 TTFT with a channel width-to-length ratio of 5. Inset shows an extrapolation of the linear portion of an I DS -V GS curve, resulting in an estimated threshold voltage of V T 10 V. The SnO 2 channel layer is 10 nm thick, deposited by RF magnetron sputtering, and rapid thermal annealed in O 2 at 600 C. is apparent from Fig. 4.2 that this device has a poor inverse subthreshold slope of approximately 4 V/decade, which reduces its ability to function as a good switch. Although the threshold voltage assessed from Fig. 4.1 and the insert of Fig. 4.2 both indicate the SnO 2 TTFT to be enhancement-mode, it is clearly evident from Fig. 4.2 that a very large negative voltage is required to completely turn the device off. The essential attribute of enhancement-mode operation of significance is the drastic increase in the drain current on-to-off ratio with enhancement-mode operation. Note from Fig. 4.2 that a threshold voltage of -20 to -25 V, typical of what is observed for the depletion-mode TTFTs, would have a drain current on-to-off ratio less than 10. Thus from an application point-of-view, the achievement of enhancement-mode operation has significantly improved the dynamic range of transistor operation, which may prove advantageous if this device is employed as a gas sensor.

53 39 Transmittance (%) (a) (b) Wavelength (nm) 900 Figure 4.3: Optical transmittance as viewed through the ITO source/drain and the channel of a SnO 2 TTFT. Curve (a) is corrected for reflectance, i.e., T / (1 - R), whereas curve (b) is the raw transmission through the entire stack, including the substrate. Inset illustrates the bottom-gate TTFT structure and biasing scheme employed. As seen from the I DS -V DS curves shown in Fig.4.1, the TTFT exhibits a maximum drain current near 90 µa, a modest value for a TTFT with a channel width-tolength ratio of 5. The magnitude of I DS depends on the mobility of the electrons in the channel. The maximum effective mobility [7] for the enhancement-mode device corresponding to Fig. 4.1 is equal to 0.8 cm 2 V 1 s 1. The maximum effective mobility is 2 cm 2 V 1 s 1 for the depletion-mode SnO 2 TTFTs. The optical transmittance versus wavelength through the ITO source/drain and channel of a SnO 2 TTFT is shown in Fig Curve (a) is the transmittance corrected for reflectance, i.e., T / (1 - R), indicating an average transmission of 90% across the visible spectrum ( nm). Curve (b) is the raw transmittance through the entire stack, including the substrate, indicating an average transmission of 75% across the visible spectrum.

54 40 SnO 2 Intensity (a. u.) sputtered, 600 o C RTA, ~300 nm sputtered, 600 o C furnace, ~300 nm N 2 plasma, 600 o C furnace, ~200 nm θ (degrees) Figure 4.4: X-ray diffraction patterns obtained from two sputter-deposited SnO 2 thin films which are either furnace or rapid thermal annealed (RTA) at 600 C, and for a SnO 2 thin film prepared by evaporation of SnO 2 powder in a Torr pressure of microwave-activated N 2 and subsequently furnace annealed at 600 C. The postdeposition anneal leads to increased crystallinity of the sputtered films, whereas films prepared by activated reactive evaporation in N 2 remain amorphous after annealing. It is very difficult to fabricate enhancement-mode SnO 2 TTFTs. Although the as deposited SnO 2 thin films are invariably extremely insulating, they exhibit little or no gate modulation when employed as TTFT channel layers due to poor crystallinity, thus requiring a post-deposition anneal. Figure 4.4 shows an X-ray diffraction (XRD; performed with a Siemens D-5000 X-ray diffractometer using Cu Kα radiation) comparison of two sputter-deposited SnO 2 thin films, which are heated at 600 C with a furnace or RTA. Peak identification confirms these films to be SnO 2. Assessment of the XRD peak widths, using the Scherrer formula and a Lorentzian peak shape, yields an estimated average crystal size of 11 nm (furnace) and 7.5 nm (RTA), whereas Williamson-Hall plots give average crystal size, strain estimates of 17.1 nm, 0.023% (furnace) and 16.5 nm, 0.036% (RTA)

55 41 [30]. The Williamson-Hall analysis suggests that the RTA film is more strained than the furnace annealed film, and that the Scherrer formula significantly underestimates the crystal size due to the neglect of strain. Improving the crystallinity of the SnO 2 thin film via a post-deposition anneal does not ensure enhancement-mode TTFT behavior. Typically the annealed SnO 2 thin films are too conductive for TTFT applications, presumably due to the tendency of SnO 2 to form oxygen vacancies, which are shallow double-donors providing conduction-band electrons [31, 32]. Often the channel-layer conductivity is so high, to many free carriers, that it cannot be appreciably modulated by a gate voltage, making transistor operation impossible. If the channel-layer conductivity is sufficiently lowered, transistor behavior is possible, although such TFTs operate in depletion-mode unless the conductivity can be decreased to an appropriate level. Several methods for reducing the conductivity of the SnO 2 channel layer have been explored. One approach is to evaporate SnO 2 powder in a partial pressure of microwave-activated N 2. The idea here is to incorporate nitrogen into the SnO 2 film, since nitrogen substitution onto an oxygen atomic site results in acceptor doping which would compensate oxygen vacancies or other SnO 2 donors, thereby reducing both the carrier concentration and the conductivity of the film. Although films prepared in this manner are indeed highly resistive, they unfortunately remain amorphous after heat treatment at 600 C. Thus, TTFTs fabricated with such films as channel layers do not exhibit transistor action, presumably due to the very poor mobility of these amorphous films. Figure 4.4 includes the XRD pattern of such a film, confirming its amorphous nature. Compensation of SnO 2 films by indium diffusion doping was also explored, since indium substitution onto a tin atomic site also results in acceptor doping. Although indium incorporation into the SnO 2 film did result in a decrease in conductivity, as expected, this decrease was not sufficient to achieve the required degree of conductivity control of the channel. To date, the most successful approach for minimizing the channel-layer conductivity is to increase the resistance

56 of a relatively conductive SnO 2 channel by simply decreasing the channel thickness; this is the motivation for employing very thin channel layers ( nm) Conclusions A highly transparent SnO 2 TTFT with prototypical I DS -V DS characteristics, a modest channel mobility, and enhancement-mode behavior has been fabricated. The enhancement-mode nature of these SnO 2 TTFTs results in an I DS on-to-off ratio of 10 5, which is approximately four orders of magnitude larger than that of a depletion-mode device. This improvement in the I DS on-to-off ratio should dramatically increase the dynamic range of SnO 2 TFT gas sensors as proposed by Wöllenstein et al [33]. Moreover, the transparent nature of SnO 2 TTFTs may lead to improved sensor performance and new sensor applications, since heterogeneous processes occurring at the active sensor surface may be optically stimulated or probed from the sensor side opposite gas/analyte exposure.

57 43 5. TRANSPARENT CIRCUITS This chapter is devoted to a discussion of the fabrication and characterization of transparent circuits including, inverters and ring oscillators. 5.1 Transparent circuit fabrication Transparent circuits are fabricated using a staggered, bottom-gate TFT configuration; the fabrication process includes seven primary steps and employs four mylar masks (CAD/Art Services, Inc.). A schematic representation of an inverter crosssection and a plan view of a transparent inverter are shown in Fig The process begins with a Corning 1737 glass substrate, coated with 200 nm sputtered indium tin oxide (ITO, Delta Technologies). 1. Mask A: Gate electrodes are defined using standard photolithographic patterning and an 11.8M hydrochloric acid (HCl) wet etch. The etch rate is 0.33 nm/sec. 2. The silicon dioxide gate dielectric layer ( 100 nm) is deposited via plasmaenhanced chemical vapor deposition (PECVD) using SiH 4 + He and N 2 O precursors. 3. Mask B: Contact to the gate electrodes is established through vias opened using photolithography and reactive ion etching. 4. The IGO channel layer (40-50 nm) is deposited by rf magnetron sputtering from a 2 inch target (Cerac, Inc.; 1:1 molar ratio of In 2 O 3 :Ga 2 O 3 ). Process pressure, process ambient, rf power density, and target-to-substrate distance are 5 mtorr, Ar/O 2 (90%/10%), 3.7 Wcm 2, and 10 cm, respectively. 5. Mask C: The channel is patterned using an 2M HCl wet etch. The etch rate is 0.63 nm/sec.

58 44 Drain Source Drain Interconnect Source Channel Gate Insulator Substrate Gate Channel (a) L L ov W1 W 2 (b) Figure 5.1: Schematic representation of (a) cross-sectional and (b) a plan view for a transparent inverter, where W 1 and W 2 are the widths of the load and control transistors respectively, L OV is the source/gate or drain/gate overlap, and L is the channel length. 6. The sample is subjected to a 500 C furnace anneal for one hour. 7. Mask D: ITO source/drain contacts ( nm) are deposited by rf magnetron sputtering from a 3 inch ITO target (Cerac, Inc.; In 2 O 3 :Sn 10% wt.). Process pressure, process ambient, rf power density, and target-to-substrate distance are 5 mtorr, Ar, 1.6 Wcm 2, and 13 cm, respectively. Patterning is accomplished through lift-off. The optical transmittance versus wavelength through the source/drain and channel regions of the TFTs is shown in Fig Both regions exhibit average transmittance in the visible portion of the electromagnetic spectrum ( nm)

59 Transmittance Wavelength (nm) Figure 5.2: The optical transmittance versus wavelength through the source/drain (black) and channel (grey) regions of IGO TTFTs. Both regions exhibit average transmittance in the visible portion of the electromagnetic spectrum of 75%. (Inset) Glass substrate containing two ring oscillators, three inverters, and several discrete transistors resting atop the label Transparent Circuits. of 75%. The data represents raw transmission through the entire structure, including the substrate (i.e., the measured transmission is reduced by both absorption and reflection). It should be noted that the Corning 1737 substrate alone exhibits an average transmittance of 92% in the visible portion of the electromagnetic spectrum. A glass substrate with two ring oscillators, three inverters, and several discrete transistors is shown in the inset of Fig. 5.2; the circuits are highly transparent and difficult to identify on the substrate. 5.2 Electrical characterization and discussion The log(i D )-V GS transfer characteristics of an IGO TTFT with V DS = 1 and 20 V are displayed in Fig The V DS = 20 V curve is used to assess the turn-on voltage and drain current on-to-off ratio, which are 2 V and 10 4, respectively.