Thinking About Jitter:

Transcription

1 Thinking About Jitter: Circuit Structures and Analytic Techniques for Measuring and Understanding Oscillator Stability John A. McNeill Worcester Polytechnic Institute, Worcester, MA Chengxin Liu Motorola, N. Andover, MA 1

2 Presentation Outline Measurement Techniques Design Tools Measurement Techniques Relating Jitter / Phase Noise Measurements Application: Ring Oscillator Application: True Random Number Generation Conclusion 2

3 Presentation Outline Measurement Techniques Design Tools Measurement Techniques Relating Jitter / Phase Noise Measurements Application: Ring Oscillator Application: True Random Number Generation Conclusion 3

4 Typical Application : SONET Serial data transmission over fiber optic link; requires: - Low bit error rate (BER) - Low cost, low power, simple interface - Recover bit clock from serial data Transmit end Receive end Clock recovery TDATA TCLK fiber link Vin RCLK RDATA Vin RCLK RDATA 4

5 Clock Recovery with PLL Vin Vin PHASE DETECTOR D Q RDATA RETIMED DATA RCLK LOOP FILTER VOLTAGE CONTROLLED OSCILLATOR RCLK "LATE" RCLK "EARLY" RECOVERED CLOCK RCLK Advantage - Low cost: entire system can be integrated - Requires integrated, low jitter VCO 5

6 Jitter Referenced to Transmit Clock TCLK RCLK! X TCLK TDATA RCLK RDATA TRIG VERT DATA SOURCE CLOCK RECOVERY PLL (D.U.T) COMMUNICATIONS SIGNAL ANALYZER 6

7 Measurement of Jitter Referenced to TCLK AD MHz X8/X16 Synthesizer Measured closed-loop jitter σ x = 24.5ps rms 7

8 Time Domain: Two Sample Standard Deviation Equipment: Communications Signal Analyzer (CSA) Procedure - "Self referenced:" clock is both trigger and input - Observe histogram (distribution) of delay times to threshold crossings of clock - Plot standard deviation σ as a function of delay T D.U.T. CLK CLK VERT IN TRIG To CSA803A!!T TRIGGER!T Average delay = NTo 8

9 Standard Deviation σ vs. Delay T Delay T = 32.4 ns Standard Deviation σ = 7.35 ps Delay T = 3.00 µs Standard Deviation σ = 45.9 ps Longer Delay T More Jitter Accumulation Larger Standard Deviation σ IEEE I&M SOCIETY McNEILL: THINKING ABOUT JITTER... MAY 10,

10 PLL VCO Time Domain Measurements Open loop: σ proportional to square root of T! "T = # "T Closed loop: Action of loop limits σ for delays longer than loop bandwidth τ κ: Time Domain Figure-of-Merit 10

11 What is Phase? Phase is the argument of a trigonometric function: V(t) = V o sin Frequency [! t + " ] o Phase #(t) Initial phase Frequency is the time derivative of phase: " = d dt!(t) Phase is the integral of frequency: $(t) =! 0 t "(t) dt + # o 11

12 Time Domain Phase Measurement: Jitter Frequency Phase Observed Voltage 4" 3" 2" V(t)!(t) " 0 t #(t) t t 4" 3" 2" V(t)!(t) " 0 t #(t) t t 12

13 Simplified Noise Model Ideal VCO with white noise at input Vctl VCO Vout Vout(t) t!(t) "RANDOM WALK" IDEAL PHASE (NOISELESS) t 13

14 Frequency Domain Measurement: Phase Noise IDEAL SINE WAVE AMPLITUDE NOISE PHASE NOISE TIME DOMAIN FREQUENCY DOMAIN 14

15 Frequency Domain Measurement Equipment: Spectrum Analyzer "Direct Spectrum" Procedure - Feed clock into RF input - Observe spectrum near fundamental frequency RF IN SPECTRUM ANALYZER 15

16 PLL VCO Spectrum Measurements Open loop: Integration of white noise at VCO input gives 1/f 2 spectrum S!OL ( f ) = N 1 f 2 Closed loop: 1/f 2 spectrum shaped by loop filter Spectrum flattens for f < f L N 1 : Frequency Domain Figure-of-Merit 16

17 Measurement Technique Summary 17

18 Presentation Outline Measurement Techniques Design Tools Measurement Techniques Relating Jitter / Phase Noise Measurements Application: Ring Oscillator Application: True Random Number Generation Conclusion 18

19 Relating Jitter / Phase Noise Measurements Reason - Design in the domain that gives the most insight - Always able to relate to end user's specification Analysis Domains - Time - Frequency PLL Operating Conditions - Closed loop - Open loop (stand alone) 19

20 Open Loop VCO Phase Noise log SVctl(f) Vctl INPUT WHITE NOISE p.s.d. log f log S!(f) OPEN LOOP PHASE NOISE p.s.d. (INTEGRATED WHITE NOISE) "1" 1/ f 2 log f 20

21 PLL Response to Phase Noise PHASE DETECTOR LOOP FILTER VCO!n!i Kd (!i -!o) F(s) Ko s!o log H(f) log f!i!n Hs(f) PHASE INPUT!o!n Hn(f) PHASE NOISE TRANSFER FUNCTION fl 21

22 Phase Noise at PLL Output!n!o log H(f) OPEN LOOP PHASE NOISE p.s.d. (INTEGRATED WHITE NOISE) CLOSED LOOP p.s.d. (LOWPASS DUE TO SHAPING BY LOOP) LOOP PHASE NOISE TRANSFER FUNCTION log f!o!n fl 22

23 Developing Time/Frequency Relationships Frequency domain, VCO open loop S!(f) S!OL ( f ) = N 1 f 2 N1: Frequency domain figure-of-merit f Frequency domain, VCO closed loop S! (f) S!CL ( f ) = N 1 f L 2 ( ) 2 1+ f f L f L fl: Loop bandwidth (known by design) f 23

24 Developing Time/Frequency Relationships Time domain, closed loop, transmit clock referenced Variance (average power) is integral of phase noise PSD S! (f) +" #!" N 1 f L 2 ( ) 2 = 1 + f f L N 1 $ f L = % x 2 f L f Result is in radians; convert to seconds! x = 1 f 0 N 1 4"f L p(t)! x t 24

25 Developing Time/Frequency Relationships Time domain, closed loop, self referenced Two sample standard deviation related to autocorrelation: 2! "T = 2 ( 2!x # RXX ("T))!!T After Fourier transform of PSD: " 2 "! x" 2! "T = 2 2!x ( 1# e #2$f L "T ) Time domain, open loop, self referenced Limit as loop bandwidth 0! "T = N 1 f 0 # { "T Time, Frequency Domain Figures-of-Merit Linked!!!T!T!T 25

26 Mathematical Relationships 26

27 Experimental Results: AD809 X8/X16 Synthesizer OPEN LOOP: CLOSED LOOP: 1000 STDEV [ps] MEASURED DELAY [ns] FIT TO! = 2.94E-8! x = ( 2.94E " 8) Predicted: 1 4# 120kHz ( ) = 23.9 psrms Measured: σ x = 24.5ps rms 27

28 Benefits of time/frequency technique Can relate either open loop figure of merit (κ or N1) to closed loop jitter performance. Allows design to take place in most convenient domain Simplifies design and simulation: need only consider open loop VCO Allows stand-alone test of VCO contribution to jitter. Applies to any oscillator that fits 1/f 2 model BUT... κ and N1 describe jitter performance of the entire oscillator: How to relate to design decisions on the circuit level? 28

29 Presentation Outline Measurement Techniques Design Tools Measurement Techniques Relating Jitter / Phase Noise Measurements Application: Ring Oscillator Application: True Random Number Generation Conclusion 29

30 Effect of Length of Ring Rings of lengths 3, 4, 5, 7, and 9 stages were fabricated All delay stages identical N delay stages What effect does the length of the ring have on jitter? 30

31 Schematic of Ring Stage for Experiments VCC CS1 R1 500! R2 500! CS2 Q4 Q3 + Vin - Q1 Q2 + Vout - IEE VCC + VCTL - 250! VBIAS 300 µa 400 µa 200 µa 200 µa 4k! 3k! 6k! 6k! VEE 31

32 Results: Ring Length Not A Factor! RING STAGES! [E-08!s] fo [MHz] td [ps] Jitter depends only on number of gates traversed, not number of oscillator periods: 100 rms jitter [psec] predicted Length of ring is not a factor! Only need to consider κ of individual gate to know jitter performance of ring!t delay [nsec]

33 Ring length experiment: Handwaving explanation Example: two rings: 3 -stage and 5-stage 10nsec delay per stage (all stages identical) What is jitter after 150nsec delay? A B C D E A' B' C' 150 nsec 150 nsec A A' B B' C C' D E

34 Ring length experiment: Handwaving explanation Jitter will be the same for each ring In both cases, edge has traversed 15 gate delays Jitter errors added in each delay are independent Note: edge has not traversed same number of oscillator periods When analyzing jitter in ring oscillators, the gate delay is the fundamental unit of time, not the oscillator period A B C D E A' B' C' 150 nsec 150 nsec A A' B B' C C' D E

35 Meaning of ring length experiment Can design ring from single gate Determine κ for one gate Within gate, find κ for each noise source 35

36 Differential CMOS Noise Sources Differential pair delay stage VDD Delay stage with noise sources VDD enrl enrl CL1 CL2 RL1 RL2 CL1 CL2 Vout - + RL1 RL2 Vout Vin - M1 M2 ISS + Vin - en1 M1 M2 en2 VBIAS M3 ISS inss VSS VSS 36

37 κ expression: switched input noise model Delay: Voltage noise σ V from noise analysis Jitter σ t from σ V, slope S κ from T d = ln(2)r L C L " t = # T d $ # = " t T d σ V S σ t 37

38 κ expression: switched input noise Approximating g m as shown: κ due to input referred e n : +ISS!IOUT " = 1 2 ln(2) e n g m I SS 2 R L!VIN Using e n = 8 3 kt g m -VLIN +VLIN -ISS " = 2 3ln(2) kt I SS 2 R L gm(!vin) gm!vin 38

39 κ expressions: load resistance, tail current Differential pair drain load resistance 2 kt! = ln(2) I 2 SS R L Tail current! = 1 2 ln(2) i n I SS If tail current is shot noise, use: i n = 1 " = 2ln(2) q I SS 2qI SS 39

40 MOS Differential Pair κ Expression Summary Differential pair drain load resistance! = Tail current! = Differential pair input referred noise 2 kt " = 3ln(2) I 2 SS R L Input referred noise of VCO control path! = ln(2) 1 2 ln(2) kt I SS 2 RL i n I SS K O " O e n (VCO) Does not include short channel effects! 40

41 Intuitive meaning of Κ expressions Time domain figure of merit κ : - has dimensions of square root (time) - quantifies gate's ability to measures time accurately All equations for κ take form: UNCERTAINTY!IN!QUANTITY QUANTITY!FLOW!RATE κ from thermal noise in collector load resistor! = κ from shot noise in tail current IEE " = 2 ln(2) 1 2ln(2) kt I SS 2 RL q I SS joule joule/sec coul coul/sec 41

42 κ Expressions: Implications for Design For lower jitter, need lower κ Denominator of all gate-level κ expressions have current I power dissipation I 2 R voltage signal swing IR For lower jitter, need to increase current, power, swing Implication: As supply voltages, allowable power dissipation decrease, low jitter becomes harder to achieve 42

43 Benefits of Time/Frequency Relationships Can relate either open loop figure of merit (κ or N 1 ) to closed loop jitter performance. Allows design to take place in most convenient domain Simplifies design and simulation: only need open loop VCO Allows stand-alone test of VCO contribution to jitter. Applies to any oscillator that fits 1/f 2 model AND... κ and N 1 can also be related to circuit-level parameters Power dissipation Signal amplitude Q of resonator Link from system level to circuit-level design decisions 43

44 Presentation Outline Measurement Techniques Design Tools Measurement Techniques Relating Jitter / Phase Noise Measurements Application: Ring Oscillator Application: True Random Number Generation Conclusion 44

45 Application: Smart Card Embedded 16-bit microprocessor Electronic commerce: store financial information Security: Need Random Number Generator (RNG) to generate encryption keys True RNG: Not pseudo (e.g. MLSG register with feedback) Immune to supply variations 45

46 Conventional RNGs Noise High Freq. Oscillator D Q Digital P ost-processing Random Bits Amplifier Thermal N oise Source Noisy Low Freq. Oscillator Data '1' CLK The jitter of the low speed oscillator must be much greater than the period of the high speed oscillator The jitter to mean period ratio is less than 1E-4 for ring oscillators in TSMC 0.18um digital library The speed ratio for the two oscillators is 100:1 for the Intel RNG Data CLK '0' B. Jun and P. Kocher, The Intel random number generator, Technical Report, Intel, M. Bucci et al., A high speed oscillator-based TRN source for smart card, IEEE Trans. Computers,

47 Architecture of Digital PLL-based RNG 9 bits DAC Ctrl Ring Oscillator II Data Post-processing Random Bits Bias D Q 24-bit up/dow n counterp 8 bits DAC Ctrl Ring Oscillator I Clk 1-bit up/dow n 1 bit counter z Analog IC Off-chip FPGA 47

48 Digital PLL-based RNG Problem: Loop startup transient Long wait for loop to lock rings together 48

49 Architecture of DLL-based TRNG Delay-lock loop: Maintain equal average delay in inverter chains CLK Voltage Controlled Delay Chain II Bias Data D Q Loop Filter Voltage Controlled Delay Chain II Clk Post-processing Random Bits Analog IC Input clock edge races to DFF clock, data inputs 49

50 Jitter Sampling VCO II (Data) VCO I (CLK) '1' '0' PDF of t diff [ n ] _ x '1' '0' 50% 50% 0 t diff [ n ] 50

51 DLL Delay Stage Delay control: V ctl controls resistance of drain loads Tail current controlled with V tail Maintain amplitude of signal swing 51

52 Die Micrograph of DLL-based RNG AMI 1.5um Process Die Size: 2.2x2.2mm 52

53 Spectrum, Autocorrelation of Raw DLL-based TRNG Output Problem: Strong DC component Highly correlated (non-random) output! Reason: not exactly (finite loop filter gain; input offset) 53

54 Digital Post-Processing: Von Neumann Corrector Take FF output bits in pairs {0,1} and {1,0} equally probable Disadvantage: reduces output bit rate INPUT BITS 0,0 0,1 1,0 1,1 PROBABILITY (1-p) 2 p(1-p) p(1-p) p 2 OUTPUT BIT none 0 1 none 54

55 Spectrum, Autocorrelation of Processed DLL TRNG Output White-noiselike: no strong peaks Uncorrelated (random) output! 55

56 19K 1K 19K 1K Data V ctl V ctl 0.1u 0.1u CLK CLK Jitter Measurement Force fixed delay; Break loop; Measure P{Q=1} Voltage Controlled Delay Chain II Voltage Controlled Delay Chain II Bias Bias Voltage Controlled Delay Chain II Voltage Controlled Delay Chain II Analog IC Analog IC Data Data D Clk D Clk Q Q Loop Filter Loop Filter Post-processing Post-processing DAQ on PC DAQ on PC Random Bits Random Bits % of '0' % of '0' CLK P{Q=1} 0 < >0.5 1 P (Q='1') 0% <50% 50% >50% 100% r Nice: ps time measurement from digital, DC analog 56

57 Jitter Measurement Result Best fit Gaussian CDF: σ = 210ps rms Prediction from κ model: 190ps rms Gaussian shape: Some confidence in true thermal noise 57

58 Presentation Outline Measurement Techniques Design Tools Measurement Techniques Relating Jitter / Phase Noise Measurements Application: Ring Oscillator Application: True Random Number Generation Conclusion 58

59 Conclusion Simplified noise model allows quick translation between time / frequency domain measurements of jitter / phase noise Relating different jitter measurements allows design in domain that gives most insight. Enables linkage between system-level description and circuit-level sources of jitter / phase noise Design for simple measurement of jitter to confirm prediction 59