DATASHEET 82C54. Features. Pinouts. CMOS Programmable Interval Timer. FN2970 Rev 6.00 Page 1 of 23. Sep 15, FN2970 Rev 6.00.

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1 DATASHEET 8C5 CMOS Programmable Interval Timer The Intersil 8C5 is a high performance CMOS Programmable Interval Timer manufactured using an advanced micron CMOS process. The 8C5 has three independently programmable and functional 6-bit counters, each capable of handling clock input frequencies of up to 8MHz (8C5) or MHz (8C5-) or MHz (8C5-). The high speed and industry standard configuration of the 8C5 make it compatible with the Intersil 8C86, 8C88, and 8C86 CMOS microprocessors along with many other industry standard processors. Six programmable timer modes allow the 8C5 to be used as an event counter, elapsed time indicator, programmable one-shot, and many other applications. Static CMOS circuit design insures low power operation. The Intersil advanced CMOS process results in a significant reduction in power with performance equal to or greater than existing equivalent products. Features 8MHz to MHz Clock Input Frequency Compatible with NMOS 85 - Enhanced Version of NMOS 85 Three Independent 6-Bit Counters Six Programmable Counter Modes Status Read Back Command Binary or BCD Counting Fully TTL Compatible Single 5V Power Supply FN97 Rev 6. Sep 5, 5 Low Power - ICCSB µA - ICCOP ma at 8MHz Operating Temperature Ranges - CX8C C to +7 C - IX8C C to +85 C - MD8C C to +5 C Pb-Free Plus Anneal Available (RoHS Compliant) Pinouts 8C5 (PDIP, CERDIP) TOP VIEW 8C5 (PLCC/CLCC) TOP VIEW D7 D6 VCC D5 D6 D7 NC VCC RD D5 D D 5 D 6 D 7 D RD CS A A D 5 D 6 D 7 D 8 D 9 NC 5 9 NC CS A A GND GND NC FN97 Rev 6. Page of Sep 5, 5

2 8C5 Ordering Information PART NUMBERS 8MHz MHz MHz CP8C5 CP8C5- (No longer available, CP8C5- recommended replacement: (No longer CP8C5-Z) available, recommended replacement: CP8C5-Z) CP8C5Z (See Note) CP8C5-Z (See Note) CP8C5-Z (See Note) CS8C5* CS8C5-* CS8C5- (No longer available, recommended replacement: CS8C5-Z) CS8C5Z* (See Note) CS8C5-Z* (See Note) CS8C5-Z* (See Note) TEMP RANGE ( C) PACKAGE PKG. DWG. # to +7 Lead PDIP E.6 to +7 Lead PDIP** (Pb-free) E.6 to +7 8 Lead PLCC N8.5 to +7 8 Lead PLCC (Pb-free) N8.5 ID8C to +85 Lead CERDIP F.6 IP8C5 IP8C to +85 Lead PDIP E.6 IP8C5Z (See Note) IP8C5-Z (See Note) - - to +85 Lead PDIP** (Pb-free) E.6 IS8C5* IS8C5-* - - to Lead PLCC N8.5 IS8C5Z (See Note) IS8C5-Z (See Note) - - to Lead PLCC (Pb-free) N8.5 MD8C5/B to +5 Lead CERDIP F.6 SMD # 865JA to +5 Lead CERDIP F.6 SMD# 865A - 865A -55 to +5 8 Lead CLCC J8.A Contact factory for availability. *Add 96 suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. FN97 Rev 6. Page of Sep 5, 5

3 8C5 Absolute Maximum Ratings Supply Voltage V Input, Output or I/O Voltage GND-.5V to V CC +.5V ESD Classification Class Operating Conditions Operating Voltage Range V to +5.5V Operating Temperature Range CX8C C to +7 C IX8C C to +85 C MD8C C to +5 C Thermal Information Thermal Resistance (Typical) JA ( o C/W) JC ( o C/W) CERDIP Package CLCC Package PDIP Package* N/A PLCC Package N/A Storage Temperature Range C to +5 C Maximum Junction Temperature Ceramic Package C Maximum Junction Temperature Plastic Package C Maximum Lead Temperature Package (Soldering s) C (PLCC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Die Characteristics Gate Count Gates CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications V CC = +5.V ± %, Includes all Temperature Ranges SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage. - V CX8C5, IX8C5. - V MD8C5 VIL Logical Zero Input Voltage -.8 V - VOH Output HIGH Voltage. - V IOH = -.5mA V CC -. - V IOH = - A VOL Output LOW Voltage -. V IOL = +.5mA II Input Leakage Current - + A VIN = GND or V CC DIP Pins 9,,-6,8- IO Output Leakage Current - + A V = GND or V CC DIP Pins -8 ICCSB Standby Power Supply Current - A V CC = 5.5V, VIN = GND or V CC, Outputs Open, Counters Programmed ICCOP Operating Power Supply Current - ma V CC = 5.5V, = = = 8MHz, VIN = GND or V CC, Outputs Open Capacitance T A = +5 o C; All Measurements Referenced to Device GND, Note SYMBOL PARAMETER TYP UNITS TEST CONDITIONS CIN Input Capacitance pf FREQ = MHz C Output Capacitance pf FREQ = MHz CI/O I/O Capacitance pf FREQ = MHz NOTE:. Not tested, but characterized at initial design and at major process/design changes. FN97 Rev 6. Page of Sep 5, 5

4 8C5 AC Electrical SpecificationsV CC = +5.V ± %, Includes all Temperature Ranges SYMBOL PARAMETER 8C5 8C5-8C5- MIN MAX MIN MAX MIN MAX UNITS TEST CONDITIONS READ CYCLE () TAR Address Stable Before RD ns () TSR CS Stable Before RD ns () TRA Address Hold Time After RD ns () TRR RD Pulse Width ns (5) TRD Data Delay from RD ns (6) TAD Data Delay from Address ns (7) TDF RD to Data Floating ns, Note (8) TRV Command Recovery Time ns ITE CYCLE (9) TAW Address Stable Before ns () TSW CS Stable Before ns () TWA Address Hold Time After ns () TWW Pulse Width ns () TDW Data Setup Time Before ns () TWD Data Hold Time After ns (5) TRV Command Recovery Time ns CLOCK AND (6) T Clock Period 5 DC DC 8 DC ns (7) TPWH High Pulse Width ns (8) TPWL Low Pulse Width ns (9) TR Clock Rise Time ns () TF Clock Fall Time ns () TGW Gate Width High ns () TGL Gate Width Low ns () TGS Gate Setup Time to ns () TGH Gate Hold Time After ns (5) TOD Output Delay from ns (6) TODG Output Delay from Gate ns (7) TWO Delay from Mode Write ns (8) TWC Delay for Loading ns (9) TWG Gate Delay for Sampling ns () TCL Setup for Count Latch ns NOTE:. Not tested, but characterized at initial design and at major process/design changes. FN97 Rev 6. Page of Sep 5, 5

5 8C5 Functional Diagram D 7 - D 8 DATA/ BUS BUER INTERNAL BUS CONTROL WORD REGISTER STATUS LATCH CR M CR L RD A A CS READ/ ITE LOGIC INTERNAL BUS CONTROL LOGIC STATUS REGISTER CE CONTROL WORD REGISTER OL M OL L n n n INTERNAL BLOCK DIAGRAM Pin Description SYMBOL DIP PIN NUMBER TYPE DEFINITION D7 - D - 8 I/O DATA: Bi-directional three-state data bus lines, connected to system data bus. 9 I CLOCK : Clock input of Counter. O : Output of Counter. I : Gate input of Counter. GND GROUND: Power supply connection. O : Output of Counter. I : Gate input of Counter. 5 I CLOCK : Clock input of Counter. 6 I : Gate input of Counter. 7 O : Output of Counter. 8 I CLOCK : Clock input of Counter. A, A 9 - I ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write operations. Normally connected to the system address bus. A A SELECTS Counter Counter Counter Control Word Register CS I CHIP SELECT: A low on this input enables the 8C5 to respond to RD and signals. RD and are ignored otherwise. RD I READ: This input is low during CPU read operations. I ITE: This input is low during CPU write operations. V CC - V CC : The +5V power supply pin. A. F capacitor between pins VCC and GND is recommended for decoupling. FN97 Rev 6. Page 5 of Sep 5, 5

6 8C5 Functional Description General The 8C5 is a programmable interval timer/counter designed for use with microcomputer systems. It is a general purpose, multi-timing element that can be treated as an array of I/O ports in the system software. The 8C5 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control. Instead of setting up timing loops in software, the programmer configures the 8C5 to match his requirements and programs one of the counters for the desired delay. After the desired delay, the 8C5 will interrupt the CPU. Software overhead is minimal and variable length delays can easily be accommodated. Some of the other computer/timer functions common to microcomputers which can be implemented with the 8C5 are: Real time clock Event counter Digital one-shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller Data Bus Buffer This three-state, bi-directional, 8-bit buffer is used to interface the 8C5 to the system bus (see Figure ). D 7 - D 8 DATA/ BUS BUER Read/Write Logic The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 8C5. A and A select one of the three counters or the Control Word Register to be read from/written into. A low on the RD input tells the 8C5 that the CPU is reading one of the counters. A low on the input tells the 8C5 that the CPU is writing either a Control Word or an initial count. Both RD and are qualified by CS; RD and are ignored unless the 8C5 has been selected by holding CS low. Control Word Register The Control Word Register (Figure ) is selected by the Read/Write Logic when A, A =. If the CPU then does a write operation to the 8C5, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the Counter operation. The Control Word Register can only be written to; status information is available with the Read-Back Command. D 7 - D RD A A CS 8 DATA/ BUS BUER READ/ ITE LOGIC CONTROL WORD REGISTER INTERNAL BUS RD A A CS READ/ ITE LOGIC CONTROL WORD REGISTER INTERNAL BUS FIGURE. CONTROL WORD REGISTER AND FUNCTIONS Counter, Counter, Counter These three functional blocks are identical in operation, so only a single Counter will be described. The internal block diagram of a signal counter is shown in Figure. The counters are fully independent. Each Counter may operate in a different Mode. The Control Word Register is shown in the figure; it is not part of the Counter itself, but its contents determine how the Counter operates. FIGURE. DATA BUS BUER AND READ/ITE LOGIC FUNCTIONS The status register, shown in the figure, when latched, contains the current contents of the Control Word Register and status of FN97 Rev 6. Page 6 of Sep 5, 5

7 8C5 the output and null count flag. (See detailed explanation of the Read-Back command.) The actual counter is labeled CE (for Counting Element). It is a 6-bit presettable synchronous down counter. CONTROL WORD REGISTER CONTROL LOGIC STATUS LATCH STATUS REGISTER INTERNAL BUS CR M CE CR L 8C5 System Interface The 8C5 is treated by the system software as an array of peripheral I/O ports; three are counters and the fourth is a control register for MODE programming. Basically, the select inputs A, A connect to the A, A address bus signals of the CPU. The CS can be derived directly from the address bus using a linear select method or it can be connected to the output of a decoder. Operational Description General After power-up, the state of the 8C5 is undefined. The Mode, count value, and output of all Counters are undefined. How each Counter operates is determined when it is programmed. Each Counter must be programmed before it can be used. Unused counters need not be programmed. n OL M OL L Programming the 8C5 Counters are programmed by writing a Control Word and then an initial count. n n FIGURE. INTERNAL BLOCK DIAGRAM OLM and OLL are two 8-bit latches. OL stands for Output Latch ; the subscripts M and L for Most significant byte and Least significant byte, respectively. Both are normally referred to as one unit and called just OL. These latches normally follow the CE, but if a suitable Counter Latch Command is sent to the 8C5, the latches latch the present count until read by the CPU and then return to following the CE. One latch at a time is enabled by the counter s Control Logic to drive the internal bus. This is how the 6-bit Counter communicates over the 8-bit internal bus. Note that the CE itself cannot be read; whenever you read the count, it is the OL that is being read. Similarly, there are two 8-bit registers called CRM and CRL (for Count Register ). Both are normally referred to as one unit and called just CR. When a new count is written to the Counter, the count is stored in the CR and later transferred to the CE. The Control Logic allows one register at a time to be loaded from the internal bus. Both bytes are transferred to the CE simultaneously. CRM and CRL are cleared when the Counter is programmed for one byte counts (either most significant byte only or least significant byte only) the other byte will be zero. Note that the CE cannot be written into; whenever a count is written, it is written into the CR. The Control Logic is also shown in the diagram. n, n, and n are all connected to the outside world through the Control Logic. All Control Words are written into the Control Word Register, which is selected when A, A =. The Control Word specifies which Counter is being programmed. By contrast, initial counts are written into the Counters, not the Control Word Register. The A, A inputs are used to select the Counter to be written into. The format of the initial count is determined by the Control Word used. A A A A CS ADDRESS BUS (6) CONTROL BUS DATA BUS (8) I/OR I/OW Write Operations The programming procedure for the 8C5 is very flexible. Only two conventions need to be remembered: 8 D - D7 8C5. For Each Counter, the Control Word must be written before the initial count is written.. The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). RD FIGURE. INTERNAL BLOCK DIAGRAM FN97 Rev 6. Page 7 of Sep 5, 5

8 8C5 Since the Control Word Register and the three Counters have separate addresses (selected by the A, A inputs), and each Control Word specifies the Counter it applies to (SC, SC bits), no special instruction sequence is required. Any programming sequence that follows the conventions above is acceptable. CONTROL WORD FORMAT A, A = ; CS = ; RD = ; = D7 D6 D5 D D D D D SC SC RW RW M M M BCD SC RW SC SC - SELECT Select Counter Select Counter Select Counter Read-Back Command (See Read Operations) RW RW - READ/ITE Counter Latch Command (See Read Operations) Read/Write least significant byte only. Read/Write most significant byte only. Read/Write least significant byte first, then most significant byte. M M M Mode Mode X Mode X Mode Mode Mode 5 M - MODE BCD - BINARY CODED DECIMAL Binary Counter 6-bit Binary Coded Decimal (BCD) Counter ( Decades) NOTE: Don t Care bits (X) should be to insure compatibility with future products. POSSIBLE PROGRAMMING SEQUENCE A A Control Word - Counter LSB of Count - Counter MSB of Count - Counter Control Word - Counter LSB of Count - Counter MSB of Count - Counter Control Word - Counter LSB of Count - Counter MSB of Count - Counter POSSIBLE PROGRAMMING SEQUENCE A A Control Word - Counter Control Word - Counter Control Word - Counter LSB of Count - Counter LSB of Count - Counter LSB of Count - Counter MSB of Count - Counter MSB of Count - Counter MSB of Count - Counter POSSIBLE PROGRAMMING SEQUENCE A A Control Word - Counter Control Word - Counter Control Word - Counter LSB of Count - Counter MSB of Count - Counter LSB of Count - Counter MSB of Count - Counter LSB of Count - Counter MSB of Count - Counter FN97 Rev 6. Page 8 of Sep 5, 5

9 8C5 A new initial count may be written to a Counter at any time without affecting the Counter s programmed Mode in any way. Counting will be affected as described in the Mode definitions. The new count must follow the programmed count format. If a Counter is programmed to read/write two-byte counts, the following precaution applies. A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter. Otherwise, the Counter will be loaded with an incorrect count. READ OPERATIONS It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily done in the 8C5. There are three possible methods for reading the Counters. The first is through the Read-Back command, which is explained later. The second is a simple read operation of the Counter, which is selected with the A, A inputs. The only requirement is that the input of the selected Counter must be inhibited by using either the input or external logic. Otherwise, the count may be in process of changing when it is read, giving an undefined result. LATCH COMMAND The other method for reading the Counters involves a special software command called the Counter Latch Command. Like a Control Word, this command is written to the Control Word Register, which is selected when A, A =. Also, like a Control Word, the SC, SC bits select one of the three Counters, but two other bits, D5 and D, distinguish this command from a Control Word.. POSSIBLE PROGRAMMING SEQUENCE Control Word - Counter Control Word - Counter LSB of Count - Counter Control Word - Counter LSB of Count - Counter MSB of Count - Counter LSB of Count - Counter MSB of Count - Counter MSB of Count - Counter NOTE: In all four examples, all counters are programmed to Read/Write two-byte counts. These are only four of many programming sequences. A, A = ; CS = ; RD = ; = D7 D6 D5 D D D D D SC SC X X X X A A SC, SC - specify counter to be latched SC SC Read-Back Command D5, D - designates Counter Latch Command, X - Don t Care. NOTE: Don t Care bits (X) should be to insure compatibility with future products. The selected Counter s output latch (OL) latches the count when the Counter Latch Command is received. This count is held in the latch until it is read by the CPU (or until the Counter is reprogrammed). The count is then unlatched automatically and the OL returns to following the counting element (CE). This allows reading the contents of the Counters on the fly without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one Counter. Each latched Counter s OL holds its count until read. Counter Latch Commands do not affect the programmed Mode of the Counter in any way. If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued. With either method, the count must be read according to the programmed format; specifically, if the Counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other; read or write or programming operations of other Counters may be inserted between them. Another feature of the 8C5 is that reads and writes of the same Counter may be interleaved; for example, if the Counter is programmed for two byte counts, the following sequence is valid.. Read least significant byte.. Write new least significant byte.. Read most significant byte.. Write new most significant byte. If a counter is programmed to read or write two-byte counts, the following precaution applies: A program MUST NOT transfer control between reading the first and second byte to another routine which also reads from that same Counter. Otherwise, an incorrect count will be read. READ-BACK COMMAND The read-back command allows the user to check the count value, programmed Mode, and current state of the pin and Null Count flag of the selected counter(s). The command is written into the Control Word Register and has the format shown in Figure 5. The command applies to the FN97 Rev 6. Page 9 of Sep 5, 5

10 8C5 counters selected by setting their corresponding bits D, D, D =. A, A = ; CS = ; RD = ; = D7 D6 D5 D D D D D COUNT STATUS CNT CNT CNT D5:=Latch count of selected Counter (s) D:=Latch status of selected Counter(s) D:=Select Counter D:=Select Counter D:=Select Counter D:Reserved for future expansion; Must be FIGURE 5. READ-BACK COMMAND FORMAT The read-back command may be used to latch multiple counter output latches (OL) by setting the COUNT bit D5 = and selecting the desired counter(s). This signal command is functionally equivalent to several counter latch commands, one for each counter latched. Each counter s latched count is held until it is read (or the counter is reprogrammed). That counter is automatically unlatched when read, but other counters remain latched until they are read. If multiple count read-back commands are issued to the same counter without reading the count, all but the first are ignored; i.e., the count which will be read is the count at the time the first read-back command was issued. The read-back command may also be used to latch status information of selected counter(s) by setting STATUS bit D =. Status must be latched to be read; status of a counter is accessed by a read from that counter. The counter status format is shown in Figure 6. Bits D5 through D contain the counter s programmed Mode exactly as written in the last Mode Control Word. PUT bit D7 contains the current state of the pin. This allows the user to monitor the counter s output via software, possibly eliminating some hardware from a system. D7 D6 D5 D D D D D NULL COUNT bit D6 indicates when the last count written to the counter register (CR) has been loaded into the counting element (CE). The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions, but until the counter is loaded into the counting element (CE), it can t be read from the counter. If the count is latched or read before this time, the count value will not reflect the new count just written. The operation of Null Count is shown below. THIS ACTION: CAUSES: A. Write to the control word register:().... Null Count = B. Write to the count register (CR):()..... Null Count = C. New count is loaded into CE (CR - CE).. Null Count =. Only the counter specified by the control word will have its null count set to. Null count bits of other counters are unaffected.. If the counter is programmed for two-byte counts (least significant byte then most significant byte) null count goes to when the second byte is written. If multiple status latch operations of the counter(s) are performed without reading the status, all but the first are ignored; i.e., the status that will be read is the status of the counter at the time the first status read-back command was issued. Both count and status of the selected counter(s) may be latched simultaneously by setting both COUNT and STATUS bits D5, D =. This is functionally the same as issuing two separate read-back commands at once, and the above discussions apply here also. Specifically, if multiple count and/or status read-back commands are issued to the same counter(s) without any intervening reads, all but the first are ignored. This is illustrated in Figure 7. If both count and status of a counter are latched, the first read operation of that counter will return latched status, regardless of which was latched first. The next one or two reads (depending on whether the counter is programmed for one or two type counts) return latched count. Subsequent reads return unlatched count. PUT NULL COUNT RW RW M M M BCD D7:=Out pin is =Out pin is D6:=Null count =Count available for reading D5-D=Counter programmed mode (See Control Word Formats) FIGURE 6. STATUS BYTE FN97 Rev 6. Page of Sep 5, 5

11 8C5 COMMANDS D7 D6 D5 D D D D D DESCRIPTION RESULT Read-Back Count and Status of Counter Count and Status Latched for Counter Read-Back Status of Counter Status Latched for Counter Read-Back Status of Counters, Status Latched for Counter, But Not Counter Read-Back Count of Counter Count Latched for Counter Read-Back Count and Status of Counter Count Latched for Counter, But Not Status Read-Back Status of Counter Command Ignored, Status Already Latched for Counter FIGURE 7. READ-BACK COMMAND EXAMPLE CS RD A A Write into Counter Write into Counter Write into Counter Write Control Word Read from Counter Read from Counter Read from Counter No-Operation (Three-State) X X X X No-Operation (Three-State) X X No-Operation (Three-State) FIGURE 8. READ/ITE OPERATIONS SUMMARY MODE DEFINITIONS The following are defined for use in describing the operation of the 8C5. PULSE - A rising edge, then a falling edge, in that order, of a Counter s input. TRIGGER - A rising edge of a Counter s Gate input. LOADING - The transfer of a count from the CR to the CE (See Functional Description ) MODE : INTERRUPT ON TERMINAL COUNT Mode is typically used for event counting. After the Control Word is written, is initially low, and will remain low until the Counter reaches zero. then goes high and remains high until a new count or a new Mode Control Word is written to the Counter. = enables counting; = disables counting. has no effect on. After the Control Word and initial count are written to a Counter, the initial count will be loaded on the next pulse. This pulse does not decrement the count, so for an initial count of N, does not go high until N + pulses after the initial count is written. If a new count is written to the Counter it will be loaded on the next pulse and counting will continue from the new count. If a two-byte count is written, the following happens:. Writing the first byte disables counting. Out is set low immediately (no clock pulse required).. Writing the second byte allows the new count to be loaded on the next pulse. This allows the counting sequence to be synchronized by software. Again does not go high until N + pulses after the new count of N is written. FN97 Rev 6. Page of Sep 5, 5

12 8C5 If an initial count is written while =, it will still be loaded on the next pulse. When goes high, will go high N pulses later; no pulse is needed to load the counter as this has already been done. CW = LSB = CW = LSB = FE MODE : HARDWARE RETRIGGERABLE ONE-SHOT will be initially high. will go low on the pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero. will then go high and remain high until the pulse after the next trigger. After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting low on the next pulse, thus starting the one-shot pulse N cycles in duration. The one-shot is retriggerable, hence will remain low for N pulses after any trigger. The oneshot pulse can be repeated without rewriting the same count into the counter. has no effect on. If a new count is written to the Counter during a one-shot pulse, the current one-shot is not affected unless the Counter is retriggerable. In that case, the Counter is loaded with the new count and the one-shot pulse continues until the new count expires. CW = LSB = CW = LSB = LSB = FIGURE 9. MODE CW = LSB = N NOTES: The following conventions apply to all mode timing diagrams.. Counters are programmed for binary (not BCD) counting and for reading/writing least significant byte (LSB) only.. The counter is always selected (CS always low).. CW stands for Control Word ; CW = means a control word of, Hex is written to the counter.. LSB stands for Least significant byte of count. 5. Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the most significant byte. Since the counter is programmed to read/write LSB only, the most significant byte cannot be read. 6. N stands for an undefined count. 7. Vertical lines show transitions between count values. CW = LSB = LSB = N N FE FIGURE. MODE FN97 Rev 6. Page of Sep 5, 5

13 8C5 MODE : RATE GENERATOR This Mode functions like a divide-by-n counter. It is typically used to generate a Real Time Clock Interrupt. will initially be high. When the initial count has decremented to, goes low for one pulse. then goes high again, the Counter reloads the initial count and the process is repeated. Mode is periodic; the same sequence is repeated indefinitely. For an initial count of N, the sequence repeats every N cycles. = enables counting; = disables counting. If goes low during an output pulse, is set high immediately. A trigger reloads the Counter with the initial count on the next pulse; goes low N pulses after the trigger. Thus the input can be used to synchronize the Counter. After writing a Control Word and initial count, the Counter will be loaded on the next pulse. goes low N pulses after the initial count is written. This allows the Counter to be synchronized by software also. Writing a new count while counting does not affect the current counting sequence. If a trigger is received after writing a new count but before the end of the current period, the Counter will be loaded with the new count on the next pulse and counting will continue from the end of the current counting cycle. CW = LSB = MODE : SQUARE WAVE MODE Mode is typically used for Baud rate generation. Mode is similar to Mode except for the duty cycle of. will initially be high. When half the initial count has expired, goes low for the remainder of the count. Mode is periodic; the sequence above is repeated indefinitely. An initial count of N results in a square wave with a period of N cycles. = enables counting; = disables counting. If goes low while is low, is set high immediately; no pulse is required. A trigger reloads the Counter with the initial count on the next pulse. Thus the input can be used to synchronize the Counter. After writing a Control Word and initial count, the Counter will be loaded on the next pulse. This allows the Counter to be synchronized by software also. Writing a new count while counting does not affect the current counting sequence. If a trigger is received after writing a new count but before the end of the current half-cycle of the square wave, the Counter will be loaded with the new count on the next pulse and counting will continue from the new count. Otherwise, the new count will be loaded at the end of the current half-cycle. CW = 6 LSB = CW = LSB = CW = 6 LSB = 5 CW = LSB = LSB = 5 CW = 6 LSB = FIGURE. MODE 5 FIGURE. MODE FN97 Rev 6. Page of Sep 5, 5

14 8C5 Mode Is Implemented As Follows EVEN COUNTS - is initially high. The initial count is loaded on one pulse and then is decremented by two on succeeding pulses. When the count expires, changes value and the Counter is reloaded with the initial count. The above process is repeated indefinitely. CW = 8 LSB = ODD COUNTS - is initially high. The initial count is loaded on one pulse, decremented by one on the next pulse, and then decremented by two on succeeding pulses. When the count expires, goes low and the Counter is reloaded with the initial count. The count is decremented by three on the next pulse, and then by two on succeeding pulses. When the count expires, goes high again and the Counter is reloaded with the initial count. The above process is repeated indefinitely. So for odd counts, will be high for (N + )/ counts and low for (N - )/ counts. CW = 8 LSB = FE FD MODE : SOFTWARE TRIGGERED MODE will be initially high. When the initial count expires, will go low for one pulse then go high again. The counting sequence is Triggered by writing the initial count. = enables counting; = disables counting. has no effect on. After writing a Control Word and initial count, the Counter will be loaded on the next pulse. This pulse does not decrement the count, so for an initial count of N, does not strobe low until N + pulses after the initial count is written. If a new count is written during counting, it will be loaded on the next pulse and counting will continue from the new count. If a two-byte count is written, the following happens:. Writing the first byte has no effect on counting.. Writing the second byte allows the new count to be loaded on the next pulse. This allows the sequence to be retriggered by software. strobes low N + pulses after the new count of N is written. CW = 8 LSB = N N N N MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE) will initially be high. Counting is triggered by a rising edge of. When the initial count has expired, will go low for one pulse and then go high again. After writing the Control Word and initial count, the counter will not be loaded until the pulse after a trigger. This pulse does not decrement the count, so for an initial count of N, does not strobe low until N + pulses after trigger. LSB = FIGURE. MODE A trigger results in the Counter being loaded with the initial count on the next pulse. The counting sequence is triggerable. will not strobe low for N + pulses after any trigger has no effect on. If a new count is written during counting, the current counting sequence will not be affected. If a trigger occurs after the new count is written but before the current count expires, the FN97 Rev 6. Page of Sep 5, 5

15 8C5 Counter will be loaded with new count on the next pulse and counting will continue from there. CW = A LSB = N Counter New counts are loaded and Counters are decremented on the falling edge of. The largest possible initial count is ; this is equivalent to 6 for binary counting and for BCD counting. The counter does not stop when it reaches zero. In Modes,,, and 5 the Counter wraps around to the highest count, either hex for binary counting or 9999 for BCD counting, and continues counting. Modes and are periodic; the Counter reloads itself with the initial count and continues counting from there. CW = A LSB = SIGNAL STATUS MODES LOW OR GOING LOW RISING HIGH Disables Counting - Enables Counting CW = A LSB = N N LSB = 5 - ) Initiates Counting ) Resets output after next clock ) Disables counting ) Sets output immediately high Initiates Counting Enables Counting - ) Disables counting ) Sets output immediately high Initiates Counting Enables Counting Operation Common To All Modes Programming N When a Control Word is written to a Counter, all Control Logic, is immediately reset and goes to a known initial state; no pulses are required for this. Gate The input is always sampled on the rising edge of. In Modes,, and the input is level sensitive, and logic level is sampled on the rising edge of. In modes,, and 5 the input is rising-edge sensitive. In these Modes, a rising edge of Gate (trigger) sets an edge-sensitive flip-flop in the Counter. This flip-flop is then sampled on the next rising edge of. The flip-flop is reset immediately after it is sampled. In this way, a trigger will be detected no matter when it occurs - a high logic level does not have to be maintained until the next rising edge of. Note that in Modes and, the input is both edge-and levelsensitive. FIGURE. MODE 5 FE 5 ) Disables Counting - Enables Counting 5 - Initiates Counting - FIGURE 5. PIN OPERATIONS SUMMARY MODE MIN COUNT MAX COUNT 5 NOTE: is equivalent to 6 for binary counting and for BCD counting. FIGURE 6. MINIMUM AND MAXIMUM INITIAL COUNTS FN97 Rev 6. Page 5 of Sep 5, 5

16 8C5 Timing Waveforms A - A CS (9) taw () tsw twa () DATA BUS VALID () tdw twd () () tww FIGURE 7. ITE A - A tar () tra () CS RD DATA BUS () tsr (5) trd (6) tad () trr VALID (7) tdf FIGURE 8. READ (8) (5) trv RD, FIGURE 9. RECOVERY FN97 Rev 6. Page 6 of Sep 5, 5

17 8C5 Timing Waveforms (Continued) MODE COUNT (SEE NOTE) (7) tpwh (8) tpwl (9) tr tgs () (7) two tgh twc (8) () () tgl (6) t tf () todg (6) FIGURE. CLOCK AND () tgw () tgs tod (5) tgh () tcl () NOTE: LAST BYTE OF COUNT BEING ITTEN Burn-In Circuits Q Q VCC GND F9 F F F F A Q6 GND R R R R R R R R R R MD8C5 (CERDIP) V CC R R R R R 9 R 8 7 R 6 R 5 R C Q VCC GND Q5 Q F A A Q8 F Q7 A V CC R R GND F9 F F F F OPEN R R R R R R MR8C5 (CLCC) VCC C VCC Q Q OPEN Q VCC R R R R R R R R R R5 R OPEN GND Q5 Q F VCC/ Q8 R5 R R5 R R VCC/Q6 GND VCC/Q7 OPEN F NOTES:. V CC = 5.5V.5V. GND = V. VIH =.5V %. VIL = -.V to.v 5. R = 7k 5% 6. R =.k 5% 7. R =.7k 5% 8. R =.8k 5% 9. R5 =.k 5%. C =. F Min. F = khz %. F = F/, F = F/,...F = F/ FN97 Rev 6. Page 7 of Sep 5, 5

18 8C5 Die Characteristics DIE DIMENSIONS: 9mils x 55mils x 9mils (7µm x 9µm x 8µm) Metallization Mask Layout 8C5 METALLIZATION: Type: Si-Al-Cu Thickness: Metal : 8kÅ ±.75kÅ Metal : kå ±.kå GLASSIVATION: Type: Nitrox Thickness: kå ±.kå D5 D6 D7 VCC RD D CS D A D A D D GND FN97 Rev 6. Page 8 of Sep 5, 5

19 8C5 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE September 5, 5 FN Updated Ordering Information Table on page. - Added Revision History. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at FN97 Rev 6. Page 9 of Sep 5, 5

20 8C5 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.5M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.5mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.5mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ + ) for E8., E6., E8., E8., E.6 will have a B dimension of. -.5 inch (.76 -.mm). -B- A. (.5) M C A A L B S A e C E C L e A C e B E.6 (JEDEC MS--AA ISSUE B) LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B C D D E E e. BSC.5 BSC - e A.6 BSC 5. BSC 6 e B L N 9 Rev. /9 FN97 Rev 6. Page of Sep 5, 5

21 8C5 Plastic Leaded Chip Carrier Packages (PLCC). (.7).8 (.) PIN () IDENTIFIER D D. (.5) MAX PLCS.6 (.66). (.8) C L. (.7).56 (.).5 (.7) TP E E C L A A. (.). (.5). (.) C.5 (.6).5 (.) R D/E D/E VIEW A NOTES:. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact.. Dimensions and tolerancing per ANSI Y.5M-98.. Dimensions D and E do not include mold protrusions. Allowable mold protrusion is. inch (.5mm) per side. Dimensions D and E include mold mismatch and are measured at the extreme material condition at the body parting line.. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. N is the number of terminal positions. -C-. (.5) MIN SEATING PLANE N8.5 (JEDEC MS-8AB ISSUE A) 8 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A D D D , 5 E E E , 5 N Rev. /97.5 (.) MIN VIEW A TYP..5 (.6) MIN FN97 Rev 6. Page of Sep 5, 5

22 8C5 Ceramic Leadless Chip Carrier Packages (CLCC) j x 5 o. S E H S D D J8.A MIL-STD-85 CQCC-N8 (C-) 8 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A , 7 A B B , B E E B.7 REF.8 REF - B D D. BSC 7.6 BSC - h x 5 o. S E F S D.5 BSC.8 BSC - D E A A PLANE E. BSC 7.6 BSC - E.5 BSC.8 BSC - E E- PLANE e.5 BSC.7 BSC - e h. REF. REF 5 L.7 M E F S HS B -H- e L j. REF.5 REF 5 L L L L ND 7 7 NE 7 7 -F- E E e L D B D B L N 8 8 Rev. 5/8/9 NOTES:. Metallized castellations shall be connected to plane terminals and extend toward plane across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane terminals.. Unless otherwise specified, a minimum clearance of.5 inch (.8mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.). Symbol N is the maximum number of terminals. Symbols ND and NE are the number of terminals along the sides of length D and E, respectively.. The required plane terminals and optional plane terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension A controls the overall package thickness. The maximum A dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y.5M Controlling dimension: INCH. FN97 Rev 6. Page of Sep 5, 5

23 8C5 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S b ccc M bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- NOTES:. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.. Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness.. Corner leads (, N, N/, and N/+) may be configured with a partial lead paddle. For this configuration dimension b replaces dimension b. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y.5M Controlling dimension: INCH. E L M c ea/ S D S aaa M C A - B LEAD FINISH BASE METAL b M (b) SECTION A-A S ea c D S (c) F.6 MIL-STD-85 GDIP-T (D-, CONFIGURATION A) LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c D E e. BSC.5 BSC - ea.6 BSC 5. BSC - ea/. BSC 7.6 BSC - L Q S o 5 o 9 o 5 o - aaa bbb ccc M , N 8 Rev. /9 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN97 Rev 6. Page of Sep 5, 5