An Ultra-Low-Power temperature compensated voltage reference generator

Transcription

1 Università di Pisa An Ultra-Low-Power temperature compensated voltage reference generator #$%&'((')*')+$,-) I,'J%3'(K#A'#L'3)# #$%&'((').-//-/') I,'J%3'(K#A'#L'3)#!"#$%#&'()*#!"#+),,)--.,%*#/,#!"#$%&'()&*()+$,#+-.+$%#/$+,(-.+%#+3,4("#%5+,$+6+$++,5++$%#($*# '-.%%-(.,'-3#4.5,)*#!"*#6*#"69:;69<#=:>?"## #

2 IEEE 5 CUSOM INEGAED CICUIS CONFEENCE An Ultra-Low-Power, emperature Compensated Voltage eference Generator Giuseppe De Vita, Giuseppe Iannaccone Dipartimento di Ingegneria dell Informazione: Elettronica, Informatica, elecomunicazioni Università degli Studi di Pisa, Via Caruso, I-56 Pisa, Italy Abstract A CMOS voltage reference, based on te difference between te gate-source voltages of two NMOS transistors, as been realized wit AMS.35 µm CMOS tecnology (V tn =.45 V and V tn =.5 V at C). e minimum and maximum supply voltages are.5 V and 4.3 V, respectively. e supply current at te maximum supply voltage and at C is.4 µa. A temperature coefficient of 5 and a line sensitivity of.6 are acieved. e power supply rejection ratios witout any filtering capacitor at Hz and MHz are larger tan -4 and -59 d, respectively. e occupied cip area is. mm. I. INODUCION HE widespread use of battery-operated systems, te relatively slow progress of battery performance/cost ratio and te need to minimize simple maintenance procedures, suc as battery replacement, are pusing te design of very low voltage and low power systems, bot digital and analog. Here we focus on a ubiquitous component of suc systems, te voltage reference generator, wic in turn as to be powerscaled, in order to be able to operate wit a very small fraction of te total power budget. Many solutions exist in literature to generate a reference voltage. A typical approac consists in using a bandgap reference, wic can be implemented in any standard CMOS tecnology exploiting te parasitic vertical Js [, ]. Oter voltage references exploit te principle of tresold voltage difference, wic can be based on a selective cannel implant [3, 4], flat-band voltage difference obtained by different gate materials [5] and wor function difference obtained by different gate dopings [6]. Suc solutions can not be implemented in a standard CMOS tecnology because tey require additional fabrication steps. An additional type of voltage reference, implemented wit a standard CMOS tecnology, is based on weigted gate-source voltage difference between an NMOS and a PMOS transistor [, ]. In tis paper we present a voltage reference, wic can be implemented in any standard CMOS tecnology, based on te weigted gate-source voltage difference between two NMOS transistors. Suc solution leads to a perfect cancellation of te effect of te temperature dependence of carrier mobility. In Sections II-V te circuit implementation is discussed in detail. In Section VI te experimental results are sown. II. CICUI DESCIPION e proposed voltage reference generator is sown in Fig.. It consists of a circuit tat generates a current I almost independent of te supply voltage ; suc current is ten amplified and injected into an active load to generate te reference voltage. A low temperature drift voltage reference is obtained by compensating te temperature dependence of te generated current wit te temperature dependence of te NMOS tresold voltage. e particular configuration used allows us to suppress te effect of te temperature dependence of mobility. e proposed voltage reference was implemented in AMS.35 µm CMOS IC tecnology. A. Current Generator Circuit In te current generator circuit a current mirror imposes equal currents in te two brances of te circuit. In order to reduce te cannel modulation effect tat causes a mismatc between te currents in te two brances, te cannel lengts of te two transistors M 5 and M 6 are cosen large enoug. ransistors M and M are biased in te subtresold region, wile transistors M 3 and M 4 wor in te saturation region. Suc beavior is acieved troug careful biasing: te gate-source voltage of M 3 (M 4 ) must be larger tan te gate-source voltage of M (M ). As a consequence, since te four transistors ave te same drain current, te W/L ratio of M (M ) as to be larger tan tat of M 3 (M 4 ). e I-V caracteristics of a MOS transistor tat operates in te saturation and in te subtresold region can be approximated by () and (), respectively, C ox W I V V V V, () D GS t GS t L V GS Vt V W DS I D V exp exp, () L mv V were µ is te carrier mobility in te cannel, V is te termal voltage, V t is te tresold voltage, W and L are te cannel widt and lengt, respectively. Assuming tat te currents in te two brances of te current circuit generator are equal, te current I, in Fig., becomes I m V 4 N W / L ln N W / L, (3) were N 3 / 4. e proposed configuration of te current generator allows us not to use a resistance to generate te /5/$. 5 IEEE

3 M5 M M3 M6 I M M4 MI M M Current Generator Active Load Fig. : Proposed Voltage eference Circuit. V EF current I, as it usually appens in suc ind of circuits [, 9]. is is particularly important if te current to be generated as to be very small, to drastically reduce te power consumption of te voltage reference circuit. In suc case a large resistance would be required causing a large area occupation on te cip. Furtermore, as will be clearer later, te use of M 3 and M 4 allows us to fully suppress te effect of te temperature dependence of mobility, leading to excellent temperature compensation. Moreover, since te two transistors M and M operate in te subtresold region, te effect of cannel lengt modulation is negligible provided tat teir drain-source voltages are muc larger tan te termal voltage, as evident from (). On te oter and, te cannel lengt modulation effect of M 3 and M 4 is negligible since tey are long-cannel devices, and since teir drain-source voltages ave very small variations, wen te supply voltage is varied, because tey are equal to teir gate-source voltages, wic, for small variation of te current I, are almost constant. Almost all te variation of te supply voltage drops ) on te drain-source voltage of M, witout causing large variations of te current I, since it wors in te subtresold region, ) on te drain-source voltage of M 5. In te latter case, in order to drastically reduce te cannel lengt modulation effect, te cannel lengt of M 5 as to be quite large. Since te reference voltage generator as two stable states, corresponding to te current given by (3) and to zero current, a start-up circuit is used to ensure tat te former stable state is acieved. Suc a circuit compares te current I wit a muc smaller nown current. If I is zero, it provides a start-up current to cange te stable state.. Active Load e active load used to generate a reference voltage wit a low temperature drift consists of two NMOS transistors biased by a current obtained by mirroring te current I and amplifying it by a factor M. ot transistors M and M operate in te saturation region. e output voltage reference as te expression sown below, VEF VGS VGS. (4) As will be clearer later, in order to ensure te correct temperature compensation, it is necessary tat most of te bias current MI flows troug te transistor M and M rater tan troug te resistances and. As a consequence, once we fix te maximum resistance values acceptable for a reasonable area occupation on te cip, we determine te minimum value of te bias current tat ensures te correct operation of te voltage reference generator, from te condition V V DS GS MI. (5) Equation (5) limits te minimum power consumption of te voltage reference generator. e resistances will be implemented by using ig resistive poly to minimize te area occupation on te cip. III. SUPPLY VOLAGE DYNAMIC e minimum supply voltage is imposed by te current generator circuit. In particular, we ave to ensure tat te transistor M as a drain-source voltage of at least mv so tat te effect of te drain-source voltage in () and ten te cannel lengt modulation of M can be neglected. Consequently, te following expression as to be satisfied, V V V V. (6) DD GS 6 DS MIN GS 4 en te supply voltage must be larger ten.5 V in te AMS.35 µm CMOS process. e maximum supply voltage is imposed by te maximum drain-source voltage allowed for MOS transistors, as sown below, V V V V. () DD DS 5MAX GS GS 3 Since in te AMS.35 µm CMOS process te maximum value for te drain-source voltage of a MOS transistor is 3.3 V, te maximum value of te supply voltage is about 4.3 V. IV. EMPEAUE COMPENSAION As a first approximation we can consider tat te tresold voltage of an NMOS transistor decreases linearly wit te temperature, as sown below, V ) V ( ) K ( ), () t ( t t were K t is a SIM3v3 coefficient tat models te temperature dependence of te tresold voltage. In te case of te AMS.35 µm CMOS IC tecnology, suc parameter is.33 mv/ C for an NMOS transistor and.45 mv/ C for a PMOS transistor. Let us define as,

4 -4 Fig. : Die Potograp (core). W 4 N W / L Mm ln. (9) L N W / L 4 From (3), (4) and (9), and assuming tat (5) is fulfilled, we can derive te following expression for te reference voltage, V EF Vt V Vt V W / L.() W / L Differentiating () wit respect to te temperature and taing into account (), one obtains V EF K t W / L q K t, () W / L q were is te oltzmann constant and q is te electron carge. Equating () to zero, we obtain q W / L W / L. () K t q W / L erefore, if () is satisfied, we obtain tat te temperature coefficient () is zero for any temperature. It is clear tat tis is true witin te approximation done in () and te simplified transistor caracteristics expressions () and (). Since te temperature dependence of te tresold voltage is not perfectly linear, a temperature dependent error will appear at te output of te reference voltage generator as we move away from te reference temperature at wic te coefficient K t was computed. Once te two transistors M and M are dimensioned for te minimum value of te bias current, given by (5), from () we can derive te ratio between te two resistance values, in order to acieve te best temperature compensation. If we tae into consideration an error in te resistor ratio /, from () it is clear tat wen te resistor ratio increases (decreases) wit respect to its nominal value te temperature coefficient becomes positive (negative). Anyway, since in our design te value of te resistor ratio is muc smaller tan unity, an error on te resistance ratio is drastically Output Voltage (mv) Supply Voltage (V) PS (d) Frequency (Hz) Fig. 3: Experiments: a) Output Voltage vs. Supply voltage at room temperature, b) PS at room temperature and for a supply voltage of V. reduced by summing it to in (). is allows us not to use trimming procedures. V. LINE SENSIIVIY ecause of te cannel modulation effect, wen te supply voltage varies, te bias current I varies as well, causing te variation of te output reference voltage. y calculating V GS and V GS from () and substituting tem in (4), we can derive te following expression for te output voltage, V EF Vt Vt MI. (3) As sown in (3), only one term of te output reference voltage wealy depends on te bias current (via a square root). Furtermore, suc term as a very small weigt in (3), due to te fact tat a variation of te bias current varies te gatesource voltages of M and M in te same direction, even if by a different amount; and, as can be better seen in (4), V EF is obtained from te weigted difference of suc two voltages, furter suppressing te dependence on I of te reference voltage. VI. EXPEIMENAL ESULS e proposed voltage reference as been realized wit a standard.35 µm CMOS process from AMS. e die potograp is sown in Fig.. Measurements sow tat te proposed voltage reference generates a mean reference voltage of about 6 mv wit a variation of ±.3 mv at room temperature wen te supply voltage varies from.5 V to 4.3 V, as sown in Fig. 3a. Fig. 4 sows te output voltage dependence on temperature for different values of te supply voltage. e measured temperature coefficient at = V and =3 V is 5 and increases to 3 and 39 at =4.3 V and =.5 V, respectively, corresponding to te maximum and minimum allowed supply voltage. At C te current drawn at te maximum supply voltage is.4 µa and at te minimum supply voltage is.5 µa. At room temperature,

5 Output Voltage (mv) =.5 V = V =3 V =4.3 V emperature ( C) Fig. 4: Measured output voltage vs. temperature for 4 values of te supply voltage. instead, te current drawn at te maximum supply voltage is. µa and at te minimum supply voltage is. µa. e power supply rejection ratio, witout any filtering capacitor, is -65 d at Hz and -5 d at MHz, for te smallest supply voltage. At larger supply voltage te power supply rejection ratio increases to -4 d at Hz and to -59 d at MHz, as sown in Fig. 3b. e occupied cip area is. mm. VII. COMPAISON WIH HE SAE OF HE A A comparison wit oter voltage reference reported in literature is summarized in able I. In suc comparison only te solutions tat can be implemented in a standard CMOS process are taen into consideration excluding te solutions tat require tecnologies wit low tresold voltage, native NMOS transistor, DMOS or icmos processes. From able it is possible to note tat te proposed voltage reference as te smallest power consumption and te igest PS wit a very good performance in terms of temperature coefficient. e occupied cip area and te line sensitivity are comparable to oter solutions presented in literature. VIII. CONCLUSION A 5 voltage reference wit a supply current of only. µa, at.5 V, as been presented. e proposed voltage reference as been implemented wit a standard.35 m CMOS process. e design conditions and possible optimizations ave been studied in detail. Particular attention as been put at minimizing te power consumption, acieving at te same time very good PS and temperature compensation, witout any trimming procedure, tans to te suppression of te effects of mobility temperature dependence. e occupied cip area and te line sensitivity are comparable wit oter solution already reported in literature. ALE I: COMPAISON WIH VOLAGE EFEENCE GENEAOS AVAILALE IN HE LIEAUE is wor Leung et al. [] Leung et al. [] anba [9] ecnology.35 µm.6 µm.6 µm.4 µm CMOS CMOS CMOS CMOS Supply Voltage (V) Supply Current (µa).5 to to 3.9 to.5. to 4.4.5@.5V.4@4.3V <9. < >. V ref 6 mv 39.3mV 63 mv 55 mv C Line Sensitivity PS =.5V =.4 =.9 MHz -65 d -5 d -4 d - d -44 d - d Cip Area (mm ) ACKNOWLEDGMENS is wor as been supported by Fondazione Cassa di isparmio di Pisa. e autors wis to acnowledge fruitful discussions wit Dr. P. Andreani, ecnical University of Denmar. EFEENCES [].S. Song, P.. Gray, A precision curvature-compensated CMOS bandgap reference, IEEE Journal of Solid State Circuits, vol. DC-, pp , December 93. [] K.N. Leung, P.K.. Mo, A sub- V 5 CMOS andgap Voltage eference witout requiring Low resold Voltage Device, IEEE Journal of Solid State Circuits, vol. 3, pp , April. [3].A. lauscild, P.A. ucci,.s. Muller,.G. Meyer, A new NMOS emperature Stable Voltage eference, IEEE Journal of Solid State Circuits, vol. SC-3, pp. 6-4, December 9. [4] H. anaa, Y. Naagome, J. Eto, E. Yamasai, M. Aoi, K. Miyazawa, Sub- µa Dynamic eference Voltage Generator for battery-operated DAMs, IEEE Journal of Solid State Circuits, vol. 9, pp , April 994. [5] M.C. obey, D.J. Gialiani, P.. Asin, Flat-and Voltage eference, U.S. Patent , August 96. [6] H.J. Oguey,. Gerber, MOS Voltage eference based on polysilicon gate wor function difference, IEEE Journal of Solid State Circuit, vol. SC-5, pp , June 9. [] K.N. Leung, P.K.. Mo, K.C. Kwo, CMOS Voltage eference, US Patent , August. [] K.N. Leung, P.K.. Mo, A CMOS Voltage eference ased on Weigted V GS for CMOS Low-Dropout Linear egulators, IEEE Journal of Solid State Circuits, vol. 3, pp. 46-5, January 3. [9] H. anba et al., A CMOS andgap eference Circuit wit Sub-V Operation, IEEE Journal of Solid State Circuits, vol. 34, pp. 6-64, May