Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation

Transcription

1 Polypase Filter Approac for Hig Performance, FPGA-Based Quadrature Demodulation J.M.P. Langlois 1, D. Al-Kalili 1, R.J. Inkol 1 Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, Ontario, Canada K7K 7B4 {langlois-p, alkalili-d}@rmc.ca Electronic Warfare Section, Defense Researc Establisment Ottawa, National Defence, Ottawa, Ontario, Canada K1A Z4 Robert.Inkol@dreo.dnd.ca Abstract e polypase filter approac to quadrature demodulation is presented. It is sown to be well suited for te implementation of purpose-designed ig performance, wide bandwidt quadrature demodulators in low-cost Field-Programmable Gate Array (FPGA) tecnology. e duplicated polypase filter approac is introduced, as a way to increase te maximum allowable input signal bandwidt wile maintaining a processing rate compatible wit FPGA implementation. Oter algoritmic considerations are discussed, and arcitectural considerations specifically applicable to te realization of digital filtering in FPGAs are discussed. A design example suitable for processing input signals centered on an intermediate frequency of 16 MHz wit a bandwidt of ~45 MHz is presented. is design occupies 83% of te Configurable Logic Blocks (CLBs) in a low-cost Xilinx X41E-3 FPGA. Additional tecniques for furter performance optimization are presented. Keywords - Quadrature Demodulation, Digital Down Conversion, Polypase Filtering, Field Programmable Gate Arrays, Digital Filtering. I. INRODUCION Quadrature demodulation is a fundamental signal processing operation in communications, electronic warfare and radar systems. e resulting complex signal representation preserves te information present in te original real signal, and facilitates subsequent processing, suc as spectral analysis or te extraction of modulation information. e specialized requirements for accuracy and wide bandwidt encountered in many radar and electronic warfare systems are often difficult to satisfy wit software implementations or available function-specific integrated circuits. 1

2 is paper addresses te implementation of purpose-designed quadrature demodulators in Field Programmable Gate Array (FPGA) tecnology for applications requiring ig performance and wide bandwidt. FPGAs offer attractive advantages over oter implementations of Application Specific Integrated Circuits (ASICs). Specifically, tey are easily programmable, reducing significantly development time and non-recurring engineering costs. A design can be quickly conceptualized, particularized to a specific application, ten implemented and tested at low cost and minimal risk. e low unit cost for te smaller and slower devices is also attractive. However, te acievable data rates in FPGAs ave traditionally been well below te performance attainable wit oter tecnologies. Consequently, for ig performance applications, special attention must be devoted to arcitectural and algoritmic issues if designs well matced to te capabilities and limitations of FPGAs are to be realized. We present quadrature demodulator design concepts designed to minimize data processing rates. Specifically, we discuss a novel polypase filtering approac to quadrature demodulation, and its extension, te duplicated polypase filtering approac, as a means of allowing area to be traded against processing rate and power consumption. We present design examples demonstrating te viability of using FPGAs for selected ig performance quadrature demodulators. e paper is organized as follows. Section II includes general principles about digital quadrature demodulation. Section III takes an in-dept look at te basic polypase and duplicated polypase approaces. Section IV discusses filter, multiplier and adder arcitecture selection as it relates to FPGA implementation of digital filtering. Section V presents some of our designs and simulation results. A conclusion can be found in section VIII. II. DIGIAL QUADRAURE DEMODULAION In te traditional analog approac to quadrature demodulation, a real input signal x(t) of bandwidt B, centered on a carrier frequency f c, is mixed wit two quadrature sinusoids. Hig frequency components are ten removed by two low-pass filters, and te resulting baseband in-pase (I) and quadrature (Q) components can be digitized by Analog-to-Digital Converters (ADCs) for subsequent digital processing. Implementation issues affecting te acievable performance include te gain and pase mismatc between te I and Q cannels, DC offsets, and ADC timing skews. Digital quadrature demodulation tecniques [1][] ave te advantages tat only one ADC is required and tat te error mecanisms can be eliminated or accurately controlled. A possible implementation is sown in Figure 1. e decimator following te in-pase and quadrature filters reduces te output data rate to a value consistent wit te desired input bandwidt and Nyquist criterion.

3 Important simplifications result from selecting te sampling frequency f s to be equal to 4 f c [1][]. e quadrature sinusoids can ten be reduced to te trivial sequences {1,, -1,,...} and {, -1,, 1,...}, eliminating te need for digital multipliers or te syntesis of te quadrature signals. cos( cn) x(t) ADC f s = 4 f c x(n) digital multiplier Digital Low Pass Filter I(n) M I(Mn) digital multiplier Digital Low Pass Filter Q(n) M Q(Mn) -sin( cn) Figure 1 - Digital Quadrature Demodulator For te radar and electronic warfare applications of interest, linear-pase caracteristics are desirable to preserve te modulation information of te signal [3]. Consequently, our approac begins wit an odd lengt symmetric finite impulse response (FIR) filter wic we refer to as te prototype filter. Given tat te prototype low-pass filter as an impulse response (n) of order N, te output of te in-pase and quadrature cannels can be expressed as: I( n) x( n) cos( n) N m 1 ( m) x( n m) cos( ( n m)) (1) and Q( n) x( n) sin( n) N 1 m ( m) x( n m) sin( ( n m)) () e process of multiplication by quadrature sinusoids is effectively replaced by te de-interleaving of te ADC output data, since alternating samples for eac branc are multiplied by zero and can be eliminated. Half of te remaining samples must undergo a sign cange, but tis operation can be embedded in te filter coefficients [4]. e processing rate in eac of te filters is consequently reduced by a factor of two. Figure illustrates tis concept, wic is applicable for an input signal aving bandwidt, B, satisfying B < f c. 3

4 e I and Q low-pass filters are formed by sub-sampling te prototype filter, according to: I Q (n) (n 1) (3) Corresponding signal spectra at different stages of te processing are sown in Figure 3. x(t) ADC f s = 4 f c x(n) x(n) Low Pass Filter I I(n) 1, -1, 1, -1, 1,... 1/(4f c) x(n - 1) Low Pass Filter Q Q(n) Figure - Digital Quadrature Demodulator wit f s = 4 f c and Decimation by wo B < fc -fc fc fc 3fc 4fc a) f B < - / / 3 / B/ < / b) - / / 3 / c) - / / 3 / d) - - / / 3 / 5 / 3 7 / 4 e) Figure 3- Spectra for Decimation-by-wo Case a) analog input signal. b) digitized signal, wit f s = 4 f c. c) digitized signal sifted to baseband. d) result after ideal low-pass filtering. e) result after decimation by two. 4

5 Selecting te sampling frequency to be equal to four times te carrier frequency may be unnecessary if te signal bandwidt is small in comparison wit its center frequency and may adversely affect te cost of te ADC and processing ardware. For example, a sampling frequency f s = 64 MHz is necessary for a target IF center frequency of f c = 16 MHz. An alternative approac would be to use undersampling to translate a signal from a ig frequency to a lower one, wen allowable by te signal bandwidt. If te sampling frequency f s is cosen suc tat: 4 fc f (4) s m 1 were m is a positive integer, ten te center frequency of te signal, f c, will be aliased to f s /4. is maintains te advantages of satisfying f s = 4 f c witout te costs incurred by a correspondingly ig sampling rate. III. POLYPHASE FILER APPROACH A. Basic Approac Altoug te bandwidt B can teoretically approac f c in te limit, it is often desirable for te quadrature demodulator to provide a band-pass filtering caracteristic to suppress undesired signals outside te bandwidt of interest. Furter, in some applications, te coice of a sampling frequency equal to four times te signal s center frequency greatly exceeds te requirements of te Nyquist criterion. If te input signal is sufficiently oversampled, ten te output sampling rate can be reduced by an integer factor, M, greater tan. Wen te signal bandwidt satisfies B < f c, a decimation factor M of 4 is appropriate. Figure 4 sows signal spectra at different stages of te processing for tis situation. In suc a case, polypase filtering [5][6] can reduce te processing rate in te filters to a quarter of te sampling rate. Starting from equations (1) and (), and decimating te output of te in-pase and quadrature cannels by 4 gives: N 1 m I (4n) ( m) x(4n m) cos( ) (5) m and N 1 m Q (4n) ( m) x(4n m) sin( ) (6) m ese expressions can be re-written as te differences between two distinct summations: 5

6 I(4n) RI I (4r) x(4( n r)) r r x(4n) I1 RI 1 (4r x(4n ) ) x(4( n r) ) (7) and Q(4n) RQ r Q (4r 1) x(4( n r) 1) x(4n 1) Q1 RQ1 r (4r x(4n 3) 3) x(4( n r) 3) (8) B < fc -fc fc fc 3fc 4fc B < / a) f - / / 3 / B/ < /4 b) - / / 3 / c) - / / 3 / d) e) Figure 4- Spectra for Decimation-by-Four Case a) analog input signal. b) digitized signal, wit f s = 4 f c. c) digitized signal sifted to baseband. d) result after ideal low-pass filtering. e) result after decimation by four e four new low-pass polypase filters of impulse responses I (n), I1 (n), Q (n) and Q1 (n) are: I ( n) (4n), for n =, 1,,, R I (9) I 1( n) (4n ), for n =, 1,,, R I1 (1) 6

7 Q ( n) (4n 1), for n =, 1,,, R Q (11) Q 1( n) (4n 3), for n =, 1,,, R Q1 (1) e values of te constants R I, R I1, R Q and R Q1 are given in able 1. R I R I1 R Q R Q1 N mod 4 = N/4 1 N/4-1 N/4 1 N/4 1 N mod 4 = 1 (N 1)/4 (N 1)/4 1 (N 1)/4 1 (N 1)/4-1 N mod 4 = (N )/4 (N )/4 (N )/4 1 (N )/4-1 N mod 4 = 3 (N 3)/4 (N 3)/4 (N 3)/4 (N 3)/4-1 able 1 - Upper Bounds for Prototype Filter Subsampling into Polypase Filters (M = 4) A quadrature demodulator based on polypase filtering is sown in Figure 5. Eac sub-filter processes a different subset of te signal data. e data samples are tus de-interleaved four ways, and all processing occurs at a quarter of te input sampling rate, i.e. at f c. is is consistent wit te assumption tat B < f c. Assuming tat te de-interleaving operation is done off-cip, te system requires a single clock at a rate equal to a quarter of te ADC s sampling rate. is greatly reduces difficulties associated wit ultra-fast ig speed input/output interfaces. From Figure 5, it is apparent tat te system is composed of four blocks tat are almost completely independent of eac oter; eac one can tus be designed and optimized separately. Placement and routing of tese four blocks on a cip is greatly simplified. Furtermore, te filters can be partitioned among separate cips if desired. B. Duplicated Polypase Filters Approac In te previous section, an appealing use of polypase filters was made to keep te data processing rate as low as possible wen decimating by four. Here, an alternative metod will be described. It as te advantage of maximizing te allowable input signal bandwidt wile maintaining te processing rate at a quarter of te sampling rate. Equations (5) and (6) give expressions for I(4n) and Q(4n), te decimated-by-four filter outputs. If an overall decimation by two is desired instead, ten te number of calculated output samples must be doubled. Since I(4n) and Q(4n) are available, ten I(4n - ) and Q(4n - ) must be calculated. Following te same approac as before, tese extra I and Q components are calculated as: 7

8 I(4n ) N 1 RI I m ( m) x(4n m)cos( ) (4r) x(4( n r) ) r r m x(4n ) I1 RI 1 (4r x(4n 4) ) x(4( n r) 4) (13) and Q(4n ) N 1 RQ Q m ( m) x(4n m)sin( ) (4r 1) x(4( n r) 3) r r m x(4n 3) Q1 RQ1 (4r x(4n 5) 3) x(4( n r) 5) (14) wit te values of te constants R I, R I1, R Q and R Q1 given in able 1. x(t) ADC x(n) x(n) x(4n) F I f s = f c f s = 4f c + I(4n) x(n-) x(4n-) F I1 f s = f c - f c x(n-1) x(n-1) x(4n-1) F Q f s = f c + Q(4n) 4f c x(n-3) x(4n-3) F Q1 f s = f c - f c Figure 5 - Quadrature Demodulator wit Polypase Filter Approac (M = 4) is sows ow cip area is traded for speed of operation. e four polypase filters are duplicated. e input to te second set of filters is formed by delaying te input to te first set by exactly two clock periods, and te signs of te branc adders are reversed. A possible resulting block diagram is given in Figure 6. In suc a configuration, te processing rate in te filters can be alved or te acievable bandwidt doubled for a given tecnology, and te ardware implementation problem now becomes one of data de-interleaving and re-interleaving. 8

9 x(t) ADC f s = 4f c 4 I Delay = 1/f s 4 Q + - I(4n) Delay = 1/f s 4 I Q(4n) Delay = 1/f s 4 Q 1 4 I Delay = 1/f s 4 Q - + I(4n - ) Delay = 1/f s 4 I Q(4n) - Delay = 1/f s 4 Q 1 Figure 6 - Duplicated Polypase Filter Arcitecture is approac is particularly interesting for an FPGA implementation. Since te maximum data rate is typically less tan for custom ASICs, te possibility of trading area for processing rate means tat an FPGA may be used for a lower cost or sorter design time. For oter tecnologies, trading area for speed can be advantageous from a power consumption perspective. Lowering te processing rate may allow a reduction in te power supply voltage. Since power is directly proportional to te clock frequency and to te square of te supply voltage, alving te frequency wile doubling cip area can reduce power consumption. For an FPGA implementation, owever, tis would not be te case since operation at nonstandard supply voltages is not normally feasible. e design needs to be done only once for te four sub-filters, and all placement and routing information can be duplicated. Again, te problem is no longer one of processing te data, but rater of deinterleaving a ig-rate data stream to te FPGA. C. Odd-Lengt, N t -Band Prototype Low-Pass Filter Selecting te prototype filter to be an odd-lengt, N t -band filter can lead to important design simplifications. Suc a filter s impulse response is symmetric about te origin and is given [7] by: 9

10 1, n ( ) N 1/ N n (15) 1 sin( n / N),oterwise N ( n / N) e term sin(n /N) being null for all values of n tat are integer multiplies of N, te filter will terefore ave almost 1 out of N zero coefficients. Note tat te symmetry property of te impulse response is necessary for linear pase [8]. Equation (15) can be used to design an N t -band filter, in conjunction wit a window function appropriately selected to trade-off transition bandwidt for reduced pass and stop band ripples. e passband must be consistent wit te overall decimation factor, M, and te Nyquist criterion. For te polypase filter approac of section A, te prototype filter can be designed as a quarter-band oddlengt filter. Sub-sampling based on equations (9) - (1) leads to: one sub-filter aving a single non-zero coefficient (i.e. it is a delay line); one symmetric sub-filter aving no zero coefficients; and, two asymmetrical sub-filters aving no zero coefficients. For te duplicate polypase filter approac of section B, te prototype filter can be designed as a alfband odd-lengt filter. Sub-sampling it based on equations (9) - (1) leads to: one symmetrical sub-filter aving no non-zero coefficients; one sub-filter aving a single non-zero coefficient (i.e. it is a delay line); and, two asymmetrical sub-filters aving no zero coefficients. erefore, appropriately designing te prototype filter considerably reduces te requirements for te duplicated polypase approac. Instead of te 8 sub-filters and 4 adders sown in Figure 6, only six subfilters and two adders are required. Furter, two of te sub-filters are realized wit simple weiged delaylines. IV. ARCHIECURAL CONSIDERAIONS A. Filter Arcitecture Selection e coice of a filter arcitecture is usually made between te so-called direct and transposed forms. See Figure 7 and Figure 8. In full-custom realization of FIR filters [9], te direct form is often preferred. Multiplication and addition of delayed input samples by te filter coefficients is combined in one large multi-operand adder were all sign-inversion carries can be pre-computed. Register requirements are limited to te delay line, wic is 1

11 of fixed widt, unless pipeline levels are introduced in te combined sifter-adder. Oter autors [1], owever, ave favored te transposed form. x(n) Delay x(n-1) Delay x(n-) Delay x(n-(n-)) Delay x(n-(n-1)) () (1) () (N-) (N-1) y(n) Figure 7 - Direct Form Realization x(n) (N-1) (N-) (N-3) (1) () Delay Delay Delay Delay y(n) Figure 8 - ransposed Form Realization For Xilinx FPGAs, we ave found tat te transposed form was superior in terms of overall Configurable Logic Block (CLB) count and cip utilization. e inerent pipelining of te transposed form is an excellent matc for CLB resources suc as function generators, dedicated carry logic and output registers [11]. Placement and routing of a filter wit te transposed form is bot easier and more efficient. Given tat te target FPGA is large enoug, signals only ave to travel a sort distance from te output of one registered adder to te next. e main disadvantage to using te direct form in an FPGA comes from te tapped delay-line. It requires output flip-flops from oterwise unused CLBs, and terefore wastes a great amount of cip resources. Anoter advantage of te transposed form is te possibility of combining all multipliers in a single multiplier block, as sown in Figure 9. Inside te multiplier block, partial products between coefficients can be reused, so tat te number of adders is minimized [1]. Pipelining of te multipliers can also be optimized between tose wit coefficients represented by many signed digits and tose equal to a single 11

12 power of two. An example multiplier block is sown in Figure 1 for a filter wit coefficients 1,, 4, 8, 16, 3 and 13 (all normalized by a factor of 56). x(n) Multiplier Block Delay Delay Delay y(n) Delay Delay Delay Delay Figure 9 - ransposed Form Symmetric FIR Filter wit Multiplier Block, N Even input data x 8 8 Delay -7x Delay Delay 9x 16-13x Delay Delay multiplier results to adder cain Figure 1 Multiplier Block Example Finally, were appropriate, te symmetry property of te impulse response of te sub-filters sould be used to reduce te ardware implementation cost by folding te filter arcitecture. B. Multiplier Arcitecture Selection e selection of a multiplier arcitecture for best performance and cip utilization depends directly on te values of te filter coefficients and teir representation. 1

13 For FPGAs, te Look-Up able (LU) approac to multiplication [13] offers interesting advantages. Eac CLB in te Xilinx 4 series can be programmed as a 16 -bit memory, by using te F and G function generators as 16 1-bit memories. is is te basic building block for te LU multiplier. In general, for a coefficient expressed wit c bits, ten c + 4 bits are required to express all possible results from te multiplication of tat coefficient wit a 4-bit number. Since eac CLB can store bits, ten (c + 4)/ CLBs are required for eac LU. e multiplicand is decomposed into slices of 4 bits. ese four bits select one of te 16 possible pre-calculated products of a LU. If te multiplicand is expressed wit m bits, ten m/4 LUs will be required, were te brackets signify rounding up to te nearest integer. Figure 11 [13] below gives a block diagram for a LU multiplier were bot te multiplicand M and te coefficient C are expressed wit 8 bits, wit a product P of 16 bits. M(7:) M(7:4) LU 8 4 x C 1 1-bit adder 1 P(15:4) P(15:) 8 M(3:) LU x C 4 1 Figure 11 - LU Multiplication Block Diagram 4 P(3:) e LU approac to multiplication by a constant coefficient presents many advantages in FPGAs. ese include a significantly reduced cip resource and area requirement over te general-purpose multiplier. Also, wen creating a system wit many multipliers, tis approac can greatly simplify te design process since te multiplier only needs to be designed once for a given set of multiplicand and coefficient size. e placement of CLBs and routing of signals internal to te multiplier can be carefully optimized for speed, area and/or power consumption, ten te multiplier can be considered as a building block. Modifying te value of te coefficient doesn t involve any structural canges, only te stored values in te CLBs need to be replaced. e multiplier building block can ten be reused as necessary. e LU approac, altoug straigtforward and widely used in FPGA implementations of digital filters, still does not acieve te most efficient utilization of ardware resources. A signed digit representation, were eac coefficient is represented as te sum of a minimal number of powers of two, is known to require te fewest non-zero binary digits [14] to acieve a given numerical accuracy. A furter issue is tat te coefficients of FIR digital filters vary over a large range in magnitude and tat te filter caracteristics are particularly sensitive to te relative accuracy wit wic te largest filter coefficients 13

14 are represented. e signed digit representation is adaptable to designs were te number of signed digits used for eac filter coefficient is tailored to economically meet te application performance requirements. Acceptable results can often be acieved wen most of te filter coefficients are represented wit one or two signed digits. In te first case, te multiplication is accomplised by a trivial sift (and a sign inversion if te coefficient is negative). e second case is only sligtly more complex, requiring a single sift-adder. In te signed digit approac, te number of CLBs used to implement a multiplier depends directly on te number of non-zero digits used for te coefficient. If a coefficient as d non-zero digits, ten d 1 twooperand additions will ave to be performed by te multiplier. e number of bits tat need to be added at every step of te sift-and-add process is equal to te number of bits in te multiplicand plus one, for two s complement addition. At every step, a portion of te least significant bits do not require an adder, since tey would be added to zero. If te multiplier is fully pipelined, owever, ten tese leastsignificant bits will need to be pipelined. Implementing te addition of two s-complement, 8-bit numbers requires 5 CLBs for a 9-bit result in a Xilinx X4 family FPGA. Assuming an 8-bit multiplicand, te number of CLBs in a non-pipelined multiplier is equal to (d 1) 5, were d is te number of non-zero digits in te coefficient. If te multiplier is pipelined, te required number of CLBs varies depending on te coefficient. In te worst case, te coefficient as non-zero digits in extreme positions. As an example, for te coefficient 11 te seven least significant bits of te multiplicand need to be registered, wic requires 3.5 CLBs. able below gives worst-case quantities of CLBs for non-pipelined and fully pipelined signed digit multipliers wit a coefficient between -18 and +17. Column of te table lists te distribution of tese 56 possible coefficients according to te number of non-zero digits tey ave, and column 3 gives te amount as a percentage of te total. For te LU approac, te calculation of te number of required CLBs is straigtforward. For an 8-bit multiplicand, and a coefficient expressed wit 8 bits (i.e. between 18 and +17), we ave te situation of Figure 11. Eac 1-bit LU occupies 6 CLBs. e 1-bit, two-operand adder requires 7 CLBs. e total is terefore 19 CLBs for a non-pipelined case. If one level of pipelining is added between te LUs and te adder, ten te four least-significant bits must be registered, necessitating two more CLBs for a total of 1. erefore, from te strict point of view of area utilization, te LU approac to multiplier implementation is preferable for only 19% of te coefficients between -18 and +17 for fully pipelined 14

15 multipliers. As long as a coefficient as less tan 4 non-zero digits, te signed-digit approac is better. For non-pipelined designs, te signed-digit approac is always preferable for tis coefficient range. # of non zero ow many % of total # of CLBs # of CLBs digits in coefficients coefficients (non-pipelined) (pipelined) coefficient (typical) (typical) % % % % % able - 8-bit Signed Digit Coefficient (-18 to +17) Multiplier Statistics From te point of view of maximum processing rate, te signed digit approac is preferable. For te LU approac sown in Figure 11, tere is one 1-bit wide adder, and typically only one level of pipelining. For te signed digit approac, te addition of any two sifted replicas of an 8-bit multiplicand requires a 9-bit adder. Assuming a simple ripple carry adder, te approac is generally always faster tan te LU approac by a small margin. It would be possible to improve te speed of te LU approac by pipelining its adder, but its implementation cost would ten increase furter. C. Adder Arcitecture Selection e selection of an arcitecture for te cain of adders sown in Figure 8 as a significant impact on te filter performance and cip resource requirements. e use of carry-save addition is advocated in [1]. However, we found tat tis coice was poorly adaptable to FPGA-based filters because of its ig register requirement. e Dedicated Carry Logic in te Xilinx X4 series FPGAs leads to very fast two-operand ripple carry adders. e dedicated carry pats usually make sopisticated adder configurations suc as te Carry Bypass and Carry Look-Aead adders unnecessary. For te X4XL family of cips wit a -9 speed grade, te fastest ripple carry adders run at 139 MHz for 8 bits, 115 MHz for 16 bits, 98 MHz for 4 bits and 86 MHz for 3 bits [15]. Wile impressive, tese results may not be sufficient were adders tat are bot fast and wide are required. Suc cases occur for quadrature demodulator designs were a large 15

16 number of coefficients aving accurately controlled values are needed to meet stringent magnitude response specifications. e Carry Select Adder configuration is a prime candidate to accelerate addition operations in te filter. In tis adder configuration, te addition is partitioned among a number of stages, eac andling a fraction of te total number of bits to be added. All adders in all stages can be ripple carry adders. e advantage of te Carry Select Adder is tat te delay on its critical pat is muc reduced wen compared to te regular ripple carry adder, since te carry doesn t need to propagate as far. It also doesn t require pipeline registers. However, it requires more silicon real-estate for te extra adder and a multiplexer required at every stage. e pipelined ripple carry can offer te same performance [16] and is attractive if cip area is limited. e disadvantage is an increased latency and a requirement for extra registers. For quadrature demodulators, latency is usually not a concern, and registers are available at low cost in te targeted FPGAs. As for any oter pipelining strategy, te idea is to break te addition into different stages and to add a level of registers at eac stage. e addition in eac stage is delayed in time by one clock cycle from te previous stage. e carry from one stage is also delayed, and fed to te next stage as it begins processing its data. e results of eac stage are also registered as many times as required to ensure tat te adder output bits are syncronized. Figure 1 below illustrates te metod for a 3 bit adder segmented into two 16-bit adder stages. In te first stage of te adder, te least significant alves of te two operands are added togeter. e sum is registered, togeter wit te last carry out. e most significant alves of te two operands are registered as well. In te second stage of te adder, te registered most significant alves of te operands are added togeter wit te carry out from te previous stage. e most significant alf sum is ten combined wit te registered least significant alf sum for te final result. e advantage of te pipelined ripple carry adder is tat te processing rate is now only limited by te speed of one of te adder stages (as for a Carry Select approac wit two-level segmentation). Wit te previous Xilinx specifications given, and for te example illustrated above, tis means tat a 3-bit adder could run at almost te 16-bit adder speed of 115 MHz, wit a small reduction due to te extra routing delay between te stages and troug te registers. e main disadvantage, oter tan increased latency, is an obvious increase in te storage requirements. For te present example, 33 extra registers are required to delay te most significant portion of te operands and te delayed carry. In general, for an N- 16

17 bit adder segmented into k stages of equal size, te extra register requirement grows as te square of te stage size N/k. A 3-bit adder segmented into 4 stages of 8 bits would require 147 extra registers. Carry In A(15:) B(15:) C in 16-bit Adder Sum(15:) Sum(15:) C out Delayed Carry C in A(31:16) 16-bit Adder 16 Sum(31:16) B(31:16) C out Carry Out Figure 1 - Pipelined Ripple Carry Adder Example Altoug considered too expensive in register overead, te pipelined ripple carry adder concept opens up an interesting alternative, only alluded to in [13]. In te case of FIR filters implemented wit one of te transposed forms, te wole pipelined adder cain can be segmented into a number of adder subcains. A simple example wit a 4 t order filter is sown in Figure 13, wit a segmentation into two stages. Eac adder in te adder cain is decomposed into a number of stages corresponding to portions of te data to be processed. Results from eac adder in a stage are not syncronized but passed immediately along te cain. Adder stages of more significant levels must receive te previous level s carry out before proceeding, and te carry is terefore delayed as in te pipelined ripple carry adder. Syncronization is done only at te end of te adder cain, wit te consequence tat a very ig device utilization density can be reaced. Except for te end of te adder cain, no CLBs need to be reserved for register realization only. e input data to te adder cains must be properly segmented and skewed in time. In te example of Figure 13, it is seen tat te multiplier outputs are divided into most and least significant alves. Eac 17

18 alf is fed to its corresponding adder cain, but te most significant data is first delayed by one clock cycle. is is necessary to ensure tat te carry from te least significant cain arrives at te same time as te most significant multiplier result to be added in te most significant adder cain. e system overead as two components: te additional registers in te multiplier block used to delay te arrival of operands to te adder cain, and te additional registers in te adder cain itself. e first overead component depends on te value of te filter coefficients, since te number of registers required will depend on te widt of te multiplication product. If a multiplication product is expressed wit a number of bits smaller tan te adder cain bus widt at tis stage, ten only one bit needs to be carried for sign extension. x(n) (3) () (1) () Most Most Most Most Least Least Least Least Least Significant Cain y(n) (Least Significant) Delayed Carry Cain Carry Carry Carry Most Significant Cain y(n) (Most Significant) Figure 13 - Pipelined Delayed-Carry Adder Cain Example (ransposed Form) For te adder cain, te overead can be calculated as a function of te number of segmentation levels, S, te order of te filter N, and te number of bits in eac level, n s. is value is assumed to be constant for every segmentation level, but a generalization could be made. First, N - 1 registers are required per segmentation level for te delayed carries. Second, te overead due to te final syncronization is equal to ( (S 1)) n s. e total adder cain overead in registers, R, is terefore equal to: 18

19 R S ( N 1) ns ( 1 S( S 1) S ( N 1) ns ns ns S S( N 1 ) ( S 1)) (16) It is seen tat for te adder cain te overead is proportional to N and to te square of S. e increase in processing rate is dependent on te speed obtainable from te ripple carry for te target cip. An adder caracterization study was performed for different X4 families of FPGAs [17]. Disregarding routing delays to te adder, te latency for different ripple carry adders is approximately linear wit a coefficient k, for adders wider tan 4 bits. Applying te delayed-carry concept to an adder cain reduces te widest adder widts from n to (n s + 1). Given tat te initial latency was o, te new latency is terefore approximated to: k n n 1), n n 1 (17) s ( s s e latency decrease can be expressed as a ratio to te initial adder latency: k( n ns 1) (18) Alternatively, te increase in processing rate is expressed as te ratio of te new processing rate to te initial processing rate: speedup 1 s (1 1 k( n k ( n n s n s 1) 1)) 1 (19) It sould be obvious from tis relationsip tat te increase in processing rate will be greater if k is large and if te number of segmentation levels is increased suc tat n s gets very small in relation to n. From te results obtained in [17], te value of k gets progressively smaller for te faster X4 FPGA families, and smaller as well for faster speed grades witin a family. e increase in processing rate for a digital filter in wic te delayed carry adder cain is implemented would terefore be greatest for te slowest FPGA families, and for cases were te initial adder cain widt is widest. is last condition will most likely occur for ig filter orders. e delayed-carry adder cain as additional advantages oter tan speed. A ig device density is maintained because few CLBs are reserved for teir flip-flops only. A digital filter to wic tis 19

20 approac is applied also benefits from facilitated placing and routing, for X4 FPGAs. is is a consequence from te fact tat using te dedicated carry logic requires ripple carry adders to be placed as a column for maximum speed. Segmenting large adders into smaller ones makes teir placement easier. Finally, as sown in Figure 13, an additional advantage comes from te regular structure tat can be easily repeated across an FPGA. V. DESIGN DESCRIPION AND SIMULAION RESULS We ave produced a number of designs based on te polypase approac described in section III.A, and targeted low-cost Xilinx FPGAs of te 4-series family. e designs were described in VHDL wit a ierarcical structural description. Beavioral descriptions were restricted to te most basic blocks suc as registers and adders. After syntesis, manual placement of blocks on te critical pats was done to minimize routing delays and maximize performance. One of our designs was implemented for 8-bit signal data in a X41E-3 FPGA aving an 84-pin package. is device contains a array of CLBs, and is one of te smaller devices of its family. e 3 speed grade is te second slowest. Our design uses 333 of te device CLBs (83.3%), 589 of te 8 flip-flops (73.6%), and 58 of te 61 input/output pins (95.1%). Suc ig utilization rates typically make it impossible to perform effectively performance optimization. However, following te various design considerations described in tis paper, particularly te decomposition into four almost-independent sub-filters, enabled a ig-performance to be acieved. A target clock period of 17 ns, of wic 15.6 ns were required by te widest adders, was easily reaced wit manual placement of only te 1 most critical pats. is implies a maximum data rate of 58.8 MHz. By applying te undersampling concept, an IF signal wit a center frequency 16 MHz can be sampled at 13.3 MHz and, to acieve a 3 db and widt of ~45MHz wit a data rate 53.3 MHz for te I and Q output data. In order to increase te processing rate furter, two main options are possible. One is simply to use faster devices, suc as ones from te X4XL or Virtex families. Simulations for te same design implemented in a X41XL-9 FPGA sow tat te maximum data rate would exceed 1 MHz. e second option is to increase te speed of te adders trougout te design. In te basic design, we selected simple ripple-carry adders because of te availability of dedicated carry logic circuitry in te X4-series FPGA family. No extra CLBs or routing resources are required by tis coice. For an improved design, te widest adders were partitioned according to te delayed-carry design strategy described in section IV.C to reduce teir widt to 11. is reduced te maximum critical component delay from 15.6 ns (17-bit adder) to 1.9 ns (11-bit adder) for an increase in clock rate to 67.8 MHz (tese figures are again for te low-cost X4-E series of FPGAs). Again, by manual

21 intervention, tis improved design was fitted into te same low-cost X41E-3 FPGA. e final utilization counts were 39 out of 4 (98%) CLBs, and 74 out of 8 (9.8) flip-flops. e input/output pin count was uncanged. able 3 below summarizes tese results. basic design delayed-carry design variation critical component 17-bit-wide adder 11-bit-wide adder critical component delay 15.6 ns 1.9 ns -15.3% max. routing 1.74 ns 1.83 ns +5.% minimum period 17 ns ns -13.% maximum data rate 58.8 MHz 67.8 MHz +15.3% CLB count 333/4 39/4 +17.% flip-flop count 589/8 74/8 +6.% able 3 Comparison of te Basic and Delayed-Carry Designs VI. CONCLUSION In tis paper, various design considerations for te implementation of ig-speed digital quadrature demodulators in FPGAs are presented. In particular, te advantages of te polypase approac, bot in computation requirements and in on-cip realization, were discussed. e duplicated polypase filter approac, presented as an extension to te basic approac, furter enances te allowable input signal bandwidt relative to te processing rate. Arcitectural issues for te realization of digital filtering in FPGAs were also discussed. is included te efficient delayed-carry cain pipelining of simple ripple carry adders for FIR filters. Finally, design examples were presented to confirm te viability of tese concepts and verify te feasibility of implementing ig performance quadrature demodulators wit low cost FPGAs. REFERENCES [1] V. Considine, Digital Complex Sampling, Electronic Letters, vol. 19, no. 16, pp , August [] C. M. Rader, A Simple Metod for Sampling In-Pase and Quadrature Components, IEEE ransactions on Aerospace and Electronic Systems, vol., no. 6, pp , November [3] R. L. Mitcell, Creating Complex Signal Samples From a Band-Limited Real Signal, IEEE ransactions on Aerospace and Electronic Systems, vol. 5, no. 3, pp , May

22 [4] G. Zang, D. Al-Kalili, R. Inkol, and R. Saper, A Novel Approac to te Design of I/Q Demodulation Filters, IEE Proceedings on Vision, Image and Signal Processing, vol. 141, no. 3, pp , June 94. [5] M.G. Bellanger, J.L. Daguet, and G.P. Lepagnol, Interpolation, Extrapolation, and Reduction of Computation Speed in Digital Filters, IEEE ransactions on Acoustics, Speec and Signal Processing, vol., no. 4, pp , August [6] M.G. Bellanger, G. Bonnerot, and M. Coudreuse, Digital Filtering by Polypase Network: Application to Sample-Rate Alteration and Filter Banks, IEEE ransactions on Acoustics, Speec and Signal Processing, vol. 4, no., pp , August [7] V. Anastassopoulos and. Deliyannis, Efficient Implementation of N t -band FIR filters Based on a Simple Window Metod, IEE Proceedings, vol. 137, pt. G, no. 4, pp. 3-38, August 199. [8] A.V. Oppeneim and R.W. Scafer, Digital Signal Processing, Prentice-Hall, [9] R. J. Inkol, V. Szwarc, L. Désormeaux, M. Esonu, and D. Al-Kalili, A 4 Megasample Per Second Digital Receiver ASIC, IEEE ASIC Conference, September [1] B. C. Wong and H. Samueli, A -MHz All-Digital QAM Modulator and Demodulator in 1.- m CMOS for Digital Radio Applications, IEEE Journal of Solid-State Circuits, vol. 6, no. 1, pp , December [11] XC4E and XC4X Series FPGA Product Specification v. 1.6, San Jose CA: Xilinx Inc., [1] A.G. Dempster and M.D. Macleod, Use of Minimum-Adder Multiplier Blocks in FIR Digital Filters, IEEE ransactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 4, no. 9, pp , September [13] K. Capman, Constant Coefficient Multipliers for te XC4E, Xilinx Application Note 54, version 1.1, 11 December [14] G.W. Reitwiesner, Binary Aritmetic, Advances in Computers, Vol. 1, F.L. Alt, Ed. Academic Press, 196. [15] Speed Metrics for Hig-Performance FPGAs. Xilinx Application Brief XBRF15, version 1., November 1997.

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