Published in: Proceedings of 8th Annual IEEE Energy Conversion Congress & Exposition (ECCE 2016)

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1 Aalborg Universitet A Multi-Pulse Front-End Rectifier System wit Electronic Pase-Sifting for Harmonic Mitigation in Motor Drive Applications Zare, Firuz; Davari, Pooya; Blaabjerg, Frede Publised in: Proceedings of 8t Annual IEEE Energy Conversion Congress & Exposition (ECCE 2016) DOI (link to publication from Publiser): /ECCE Publication date: 2016 Document Version Publiser's PDF, also known as Version of record Link to publication from Aalborg University Citation for publised version (APA): Zare, F., Davari, P., & Blaabjerg, F. (2016). A Multi-Pulse Front-End Rectifier System wit Electronic Pase- Sifting for Harmonic Mitigation in Motor Drive Applications. In Proceedings of 8t Annual IEEE Energy Conversion Congress & Exposition (ECCE 2016) IEEE Press. DOI: /ECCE General rigts Copyrigt and moral rigts for te publications made accessible in te public portal are retained by te autors and/or oter copyrigt owners and it is a condition of accessing publications tat users recognise and abide by te legal requirements associated wit tese rigts.? Users may download and print one copy of any publication from te public portal for te purpose of private study or researc.? You may not furter distribute te material or use it for any profit-making activity or commercial gain? You may freely distribute te URL identifying te publication in te public portal? Take down policy If you believe tat tis document breaces copyrigt please contact us at vbn@aub.aau.dk providing details, and we will remove access to te work immediately and investigate your claim. Downloaded from vbn.aau.dk on: juni 14, 2018

2 A Multi-Pulse Front-End Rectifier System wit Electronic Pase-Sifting for Harmonic Mitigation in Motor Drive Applications Firuz Zare Power and Energy Group Te University of Queensland, St. Lucia, 4072, Australia Pooya Davari, Frede Blaabjerg Department of Energy Tecnology Aalborg University, 9220 Aalborg, Denmark Abstract In tis paper, an electronic pase-sifting strategy as been optimized for a multi-parallel configuration of linecommutated rectifiers wit a common dc-bus voltage used in motor drive application. Tis feature makes te performance of te system independent of te load profile and maximizes its armonic reduction ability. To furter reduce te generated low order armonics, a dc-link current modulation sceme and its pase sift values of multi-drive systems ave been optimized. Analysis and simulations ave been carried out to verify te proposed metod. Keywords active filter; adjustable speed drive; electronic inductor; armonic elimination; rectifier I. INTRODUCTION Modern power electronics ave revolutionized te course of motor drive industry by introducing te Adjustable Speed Drive (ASD) tecnology (also known as Variable Speed Drives (VSD) or Frequency Converters (FC)). An ASD improves energy efficiency of a system by controlling te speed of motor at an optimal speed and/or torque. Hence, te energy consumption of te motor is reduced from full power to a partial power for te same performance (i.e., speed and/or torque). However, ASD systems ave witnessed as one of te major sources of armonics, wic may deteriorate te grid power quality. From a power quality point of view, te generation of current armonics from an ASD system as become a major concern as tey may lead to ig losses and stability issues in te grid [1],[2]. Typically, te majority of tree-pase motor drive applications are equipped wit a double-stage power converter. As Fig. 1(a) sows, te first stage employs a tree-pase line commutated rectifier suc as diode-rectifier (DR) or Silicon Controlled Rectifier (SCR) to perform AC to DC conversion and a voltage source inverter to convert DC back to AC at te demanded voltage and frequency. Tis configuration provides a unidirectional power flow and is te most common topology employed in industrial and commercial drives. Employing line commutated rectifier at te front-end stage imposes ig level of input current armonics. Altoug many armonic mitigation solutions ave been introduced [3], [4], most ASD manufacturers are still using conventional passive filtering tecnique (e.g., using inductor at ac-side or dc-side as sown in Fig. 1(a)) as a simple, reliable and an effective solution to some extent [4]. Wit te global sift towards energy saving, more ASD systems are adopted as an energy efficient solution. However, te undesirable effect of generated armonics can be substantially elevated wen te number of industrial drives is increased at te Point of Common Coupling (PCC). Terefore more advanced filtering metod is required rater tan using passive inductors (Fig. 1 (a)). Notably, a proper arrangement of tese nonlinear loads can contribute to an effective armonic mitigation [5]-[8]. In fact, tis idea was first introduced in multi-pulse rectifiers using pase-sifting transformers [10]. Many ASD manufacturers advocate te use of 12-pulse or 18- pulse pase-sifting transformer, mainly because of its simplicity and reliability [10], [11]. Transformer-based multi-pulse rectifiers significantly impair te power density of ASD systems and are costly. In addition, teir performance depends on te load profile. For instance depending on te output power level a 12-pulse rectifier system can obtain a Total Harmonic Distortion (THD i ) in te range of 10% < THD i < 15% [7], [10], [11]. In te real-world situation most ASD systems operate in partial loading conditions depending on te application demands, locations and even safety margins. Operating at partial loading conditions adversely affect te ASD system THD i as te effective impedance of te passive filter is proportional to te load current (output power). Terefore, te input current THD i and power factor (λ) will be worsened wen te rectifier is partially loaded. Fig. 1(b) exemplifies te input current waveforms of a conventional ASD system under different loading conditions wen te passive filter inductor is placed at te dc-side. In practice te inductance value is selected in te range of 3-5% (e.g., L dc = 2 mh) [12]. Tus, maintaining te THD i and te power factor (λ) independent of te load profile is very beneficial. In tis paper an electronic pase-sifting metod (transformer-less) is proposed based on aving multiple linecommutated rectifiers. Te proposed topology as a common dc-bus, wic makes it suitable for single and multi-drive configuration especially for medium and ig power applications were employing a pase-sifting transformer is

3 Fig. 1: Standard adjustable speed drive system wit double stage conversion: (a) system block diagram, (b) input current waveforms at different loading conditions wen dc-side passive filtering is utilized (Ldc = 2 mh, see Table I for te applied system parameters). quite bulky. In addition, a current modulation tecnique at te dc-link using Electronic Inductor (EI) tecnique is employed wic substantially improves te input current quality. Te proposed tecnique is an enanced metod based on previous introduced strategies by te autors in [5]-[8], [12]. Te introduction of a common dc-bus in tis metod makes te performance of te system independent of te load profile. Te proposed controller and topology ave been analyzed and simulated in order to verify te proper operation of te multirectifier system. II. PROPOSED HARMONIC MITIGATION METHOD Te proposed metod comprises of two features as illustrated in Fig. 2. First, an electronic pase-sifting is proposed based on using multiple line-commutated rectifiers wit a common dc-bus. Te pase-sifting capability can improve te input current quality. Secondly, a current modulation tecnique is applied, wic can furter reduce te low order armonics and significantly improve te current THD i. Te novel advantage of te proposed topology lies in its configuration and control strategy, wic enables te system to operate properly wit a common dc-link (see Fig. 2(b)). Te new configuration wit te common dc-bus not only can improve te current quality at different loading conditions, but also can sare te dc-link current among different numbers of motor drives (Fig. 2(a)). A. Electronic Pase Sifting Tecnique Te armonic elimination based on pase-sifting te input currents is a well-known tecnique wic traditionally as been employed in multi-pulse rectifier systems using pasesifting transformers [10], [11]. Te novelty of te proposed metod is applying te same principle excluding te use of Fig. 2. Te proposed multi-rectifier system wit electronic pasesifting: (a) circuit block diagram, (b) applied control strategy. bulky pase-sifting transformer. As Fig. 3(a) sows, two linecommutated rectifiers (i.e., M = 2) ave been used to perform a pase-sifting among te input currents. By applying different firing angles (α f ) to te Silicon Controlled Rectifier (SCR) te input currents will be pase-sifted and it is possible to reduce specific low order armonics. Notably, since te firing angle of te first unit is always zero (α f1 = 0), a Diode Rectifier (DR) is selected (i.e., i s1,abc = i d,abc ). Here at te dc-side of eac rectifier a dc-dc converter is installed. Controlling te dc-link current by incorporating a dcdc converter enables to emulate te beavior of an ideal infinite inductor [5]-[8]. Fig. 3(a) sows a simplified representation of te proposed metod, wic te dc-dc converter will operate as a current source. Basically, by controlling te dc-link current at

4 Fig. 3. Simplified representation of te proposed metod: (a) scematic wit ideal current sources at te dc-link, (b) stair-case waveform of te total input current (ig,a) based on electronic pase-sifting (αf) and flat current control of eac rectifier. a constant level (i.e., I dc ) te input current of eac rectifier (i.e., i d,a and i s2,a ) will be a square-wave wit 120 degrees conduction (Fig. 3(b)). As it can be seen from Fig. 3(b), applying a pasesift (α f ) using te SCR will generate a multilevel total input current i g,abc. In fact, by applying a suitable pase-sift to te SCR unit certain armonic orders ( t ) can completely be eliminated (i.e., α f = 180 o /). Tis as been validated as one of simulation cases in Section III. To acieve te maximum armonic reduction performance, te current drawn by eac rectifier sould be at te same level (i.e., I Ld = I Ls2 = I dc ). Since te motors mostly operate at different partial loading conditions, aving a common dc-bus and controlling te dc-link current can ensure suc beavior. However, aving a pase-sift of te controlled rectifier canges te rectified voltage (u rec,sm ) and makes te controlling of all rectifiers at same current level quite callenging due to presence of circulating currents. Te proposed solution applies a passive metod in order to minimize te circulating current. Fig. 4. Circuit diagram of te proposed rectifier system in operating Mode II: (a) circuit diagram wen bot switces S1 and S2 are in OFF-state, (b) simplified circuit diagram of te system sowing te voltage difference across te negative dc-link legs and circulating current. Te passive metod is based on utilizing extra inductors at negative dc-link leg of eac rectifier (i.e., L dc- ). Te operation modes are briefly explained for two parallel connected rectifier units as sown in Fig. 3(a). Te operation modes can be generally analyzed as two modes, wic is Mode I were bot units ave te same input voltage wile in te second mode te rectifiers are connected to different input voltages. Mode I (αf 60 o ): In tis time interval te same pase voltages (e.g., u a & u b ) appear across bot rectifiers. In tis situation as it can be seen from Fig. 3(b) te rectified voltage across bot rectifiers are equal (e.g., u rec,d = u rec,s1 = u ab ). In tis interval, tere are four possible switcing states based on S 1 and S 2. Wen at least one of te switces is in te ON-state, te rectifiers are separated from eac oter because of te blocking diodes D 1 -D 4. Terefore, te circulating currents are prevented and eac boost converter controls te dc-link currents. Te current saring in te last switcing state can be an issue as bot switces are in te OFF-state and te capacitor (C dc ) is connected to bot rectifiers. However, since bot rectifier units are connected to te same pase voltages, applying te proposed passive and active current control metods can keep te current at its reference value. Notably, te extra inductors (L dc- ) and te diodes in te negative dc-link

5 leg (D 2 and D 4 ). Tis means tat any mismatc between te passive components sould be prevented in order to ensure a better performance of te system. However, as it is sown in Section III, even under significant mismatc condition te proposed controller can maintain te dc-link current at its reference value to some extent. Mode II (0 αf /60 o 60 o +αf): In tis mode te negative dclink leg of te DR conducts troug anoter pase oter tan te one in Mode I (see Fig. 4(a)). For instance, if during Mode I te DR was conducting troug u ab during te second mode it starts conducting troug u ac. Tis is due to te fact tat following Fig. 3(b), te pase voltage u c becomes lower tan u b. However, te SCR unit, since te next firing event as not occurred, will keep conducting in te Mode I line-to-line voltage (i.e., u rec,s2 = u ab ). Tus te negative dc-link legs of te rectifiers are connected to different pase voltages (e.g., u b and u c ) wile te positive legs are connected to te same voltage (e.g., u a ) as it is sown in Fig. 4(a). As mentioned, te current saring can be an issue if bot switces S 1 and S 2 are in te OFF-state. Te simplified circuit diagram of tis switcing state is sown in Fig. 4(b). Tus, during tis interval and switcing state, te current troug te negative dc-link legs are influenced by te magnitudes of te pase voltages u b and u c. On te oter and, te current troug te positive dclink legs are te same. Te rate of current cange of te dclink current troug te positive legs of te rectifiers are given as, di di Ld + Ls,2+ ua udc+ = Ldc+ = Ldc+ (1) dt dt During tis time interval, te input voltage across te SCR u ab, is less tan te input voltage across te DR u ac (see Fig. 3(b)). Te difference in te input voltages gives different di/dt values for te negative dc-link currents as, uab < uac dils, 2 dils, 2 dild di (2) + + Ld Ldc+ + udc + Ldc < Ldc+ + udc + Ldc dt dt dt dt Following (1) and considering identical inductors, di dt Ls, 2 di dt Ld < (3) Tis means tat te rates of te current canges in te negative legs of te rectifiers are different wile te di/dt values of te positive legs are te same. Tis issue as been elaborated more based on u bc across te negative dc-link legs of te rectifiers as sown in Fig. 4(b). As te diodes D 2 and D 4 conduct, te circulating current i cr is affected by u bc. During tis time interval and te switcing time (i.e., S 1 and S 2 = 0), u bc > 0, tus di cr /dt is positive as, dicr dicr dicr ubc = Ldc + Ldc = 2Ldc > 0 (4) dt dt dt Terefore, following (3) and (4) at te end of te switcing state i Ld- and i Ls,2- may ave different magnitudes. Te difference in te inductor currents depends on te dc-link inductor values. Tese currents will be adjusted during te next switcing states wen at least one of te switces S 1 and Fig. 5. Conceptual illustrations of te applied multi-pulse modulation sceme for armonic elimination: (a) detailed analysis, (b) typical waveforms in generating multi-level current waveform at te grid-side current (ig) [5]-[8]. S 2 is turned on. Tis issue as been simulated and analyzed furter in Section III. B. Current Modulation Metod Te current modulation metod is based on te calculation of a pre-programmed switcing pattern for te DC-link current to acieve te elimination of specific armonics in te grid currents [5]. In tis approac, a DC-link current modulation sceme is generated by adding or subtracting te pasedisplaced current levels. Fig. 5(a) illustrates te principle of tis multi-pulse modulation sceme (i sm,a = p 0 + p 1 p 2 ). As it is sown in Fig. 5(a), te new modulation signal i sm,a consists of flat signals p 0, p 1, and p 2 wit a conduction angle of β 0 (120 o ), β 1, and β 2, a pase-sift of α 0, α 1, and α 2 and a magnitude of m 0, m 1, and m 2, correspondingly. Hence, following te Fourier series, te armonic components of te square-wave signals (i.e., p 0, p 1, and p 2 ) can be expressed as, p () t = a cos( ωt) + b sin( ωt) (5) i i i in wic, i = 0, 1, 2, and = 1, 3, 5, 7, is te armonic order, ω te fundamental grid angular frequency, ai and bi are te Fourier coefficients tat are given by, 2mi a = + + π 2mi b = + π [ sin( α ) sin( α β )] i i i i [ cos( α ) cos( α β )] i i i i (6)

6 Notably, in te case of aving only flat current modulation (i.e., Fig. 3(b)) m 1 = m 2 = 0. Subsequently, according to te superposition principle and Fig. 5(a), te armonic components of te modulation signal (i.e., i sm ) can be obtained as, i ( t) = ( a + a a )cos( ( ωt θ )) +... sm, p ( b + b b )sin( ( ωt θ )) p p (7) in wic p = a, b, and c wit θ a = 0, θ b = -120, and θ c = 120. As a result, te -order armonic magnitude ( I sm, p) of te resultant DC-link modulation sceme can be expressed as, 1/2 2 2 IsM, p = ( a0 + a1 a2 ) + ( b0 + b1 b2 ) (8) Finally, te following condition sould old, o α1 + α2 = 2α (9) o α0 < α1 < α2 < α As Fig. 5(b) sows, applying te above current modulation in conjunction wit pase-sifting results in a multi-level current waveform at te grid side. In tat case, te resultant total armonics of te grid current ( ig, abc () t ) for parallel connected rectifier systems will become, i () t = i () t (10) g, abc sm, abc M Hereafter, according to (6) and (8) it is possible to acieve armonic cancellation by calculating te armonic magnitude of te total input current and solving I = 0 ( 1) and 1 Ig = MI wit MI being te desired Modulation Index. In order to obtain more suitable solution to reduce te armonics of interest, an optimization can be carried out. Using optimization allows applying te maximum allowable armonic levels defined by te application or te grid code [14]. Moreover, te above multi-pulse current modulation can be extended by adding more current levels, wic increase te flexibility of armonic reduction approac [7]. III. RESULTS In tis section te proposed metod is validated troug numerical simulations. Table I sows te list of te applied parameters in te system. As it can be seen from Table I, an RC snubber branc is considered for SCR units. In practice, to Table I. Parameters of te Multi-Rectifier System Symbol Parameter Value u abc Grid pase voltage 230 Vrms f g Grid frequency 50 Hz L g, R g Grid impedance 0.1 mh, 0.1Ω L scr SCR AC-side filter 0.18 mh C snub, R snub SCR snubber 100nF, 100 Ω L dc+ = L dc- DC link inductor 1 mh C dc DC link capacitor 0.5 mf U dc Output voltage 700 Vdc HB Hysteresis band 0.5 A P O,total Total output power 10 kw g Fig. 6. Te rectified voltages and dc-link currents waveforms for two parallel rectifiers: (a) under balanced condition wen te positive and negative dc-link inductors are equal (Ldc+ = Ldc-) and (b) wen tere is 50% mismatc between te positive and negative dc-link inductors (Ldc- = 0.5Ldc+). avoid SCR unit failure and to reduce te overvoltage to a reasonable limit, an RC snubber branc is connected across eac tyristor. However, te presence of te snubber circuit causes current spikes in te SCR current at te point of commutation. In order to damp te current spikes, small ACside inductors are placed in series prior to te SCR units (i.e., L scr ). Here, two different cases are considered. In te first case study, te performance of te proposed current control tecnique in balancing te dc-link currents is analyzed based on te extra added inductors (L dc- ). Secondly, te advantage of te proposed topology in improving te input current quality is addressed for different situations and number of te modular units (M). Fig. 6 sows te rectified voltages and dc-link current waveforms at bot positive and negative legs for two parallel rectifier units under balanced and unbalanced conditions. As it can be seen from Fig. 6(a), applying te proposed passive control metod (L dc+ = L dc- ) wen one current sensor is used at

7 Fig. 7. Numerical simulations of two parallel rectifier units applying te pase-sifted current control tecnique wit αf = 36 o for 5 t armonic elimination at Po = 100%: (a) input current waveforms, (b) comparison of armonic distribution of total input current. Fig. 9. Numerical simulation of two parallel rectifier units applying te pase-sifted modulated current control tecnique for minimum obtainable THDi: (a) input current waveforms at Po = 100% (10 kw), (b) comparison of armonic distribution of total input current, (c) input current waveform at tree different output power levels. Fig. 8. Numerical simulations of two parallel rectifier units applying te pase-sifted current control tecnique wit αf = 32.2 o for minimum obtainable THDi at Po = 100%: (a) input current waveforms, (b) comparison of armonic distribution of total input current. positive dc-link legs te currents are controlled witin te Hysteresis Band (HB) and sared te currents equally between bot converters. Conventionally wen te firing angle increases te boost converter draws more current in order to adjust te output voltage due to te reduction on te SCR rectified voltage [12]. Te proposed configuration overcomes tis problem wic in return can enance te armonic reduction capability of te system. To furter demonstrate te performance of te proposed tecnique te waveforms are illustrated in Fig. 6(b) for te case wen tere is a mismatc of 50% between te positive and negative dc-link inductors (i.e., L dc- = 0.5L dc+ ). As it can be seen, te negative dc-link currents of bot rectifiers become unbalanced for te second operating mode. Altoug tis is an extreme mismatc condition, it sows te importance of passive components parameters on te performance of te system as it is addressed in te previous section. In order to sow te performance of te proposed multipulse rectifier unit, te armonic elimination capability of te system is evaluated under different configurations.

8 Fig. 10. Harmonic distortion of te total input current (THDig) optimized for different power factor values applying te pasesifted current control sceme wit respect to te number of connected modular rectifier units (M) at Po = 100%. Fig. 12. Harmonic distortion of te total input current (THDig) optimized for different power factor values applying te pasesifted modulated current control sceme wit respect to number of te connected modular rectifier units (M) at Po = 100%. Fig. 11. Input current waveforms of five parallel rectifier units applying te pase-sifted current control tecnique for minimum obtainable THDi at Po = 100%. First, te armonic performance is considered for two parallel units wic only electronic pase-sifting is applied to te units following Fig. 3. Te simulated results for te input currents of eac rectifier units and te total input current at te PCC (i g ) are sown in Fig. 7 wen a pase sift of α f = 36 o is applied. Teoretically, applying tis pase-sift sould completely remove te 5 t armonic (i.e., 5x36 o = 180 o ), owever, te presence of non-ideal parameters especially te grid impedance sligtly affects te applied pase-sift. As it can be seen from Fig. 7(b) applying 36 o pase-sift almost eliminates te 5 t armonic order in te total input current (1.8%). Tis results in THD i = 15.2% and power factor (λ) of However, as it is depicted in Fig. 8, te minimum THD i of 15% and power factor of λ = 0.95 can be obtained wen α f = 32.2 o is considered. Fig. 13. Input current waveforms of five parallel rectifier units applying te pase-sifted modulated current control tecnique for minimum obtainable THDi at Po = 100%. Altoug using te pase-sifted current control can improve te input current quality, but in order to furter reduce te THD i, te current modulation sceme can be employed. Fig. 9 sows te obtained results for two parallel units wen a pulse pattern along wit te pase-sift is applied. Here, te control parameters are optimized for acieving te minimum possible THD i. As it can be seen from Fig. 9(a) and (b) te THD i is greatly improved from 15% in te flat dc-link current down to 10.5%. Notably, te parameters can be optimized based on different armonic performance requirements [5]-[8]. In order to sow te performance of te system under partial loading conditions, same pase-sifted current modulation is applied wen te system is operating at tree different output power levels (i.e., 100%, 50% and 25%). As it can be seen from Fig. 9(c), compared wit Fig. 1, ere te system

9 Fig. 14. Harmonic performance of te total input current in five modular rectifier units wit pase-sifted current control (Fig. 11) and pase-sifted modulated current control (Fig. 13). performance is kept almost te same bot in terms of THD i and power factor (λ). Te electronic pase-sifting tecnique as te advantage of being simple and cost-effective compared wit te current modulation tecnique in wic additional voltage sensors are required for te syncronization purpose. However, applying only pase sift cannot improve te input current quality as muc as wen it is combined wit te modulation tecnique. But te performance of te system in improving te input current quality is igly dependent on te number of te connected rectifier units as well. Terefore, te performance of te pase-sifted flat current control can be comparable wit te modulated current control tecnique if enoug number of rectifiers is connected in parallel. In order to sow tis dependency, optimizations are conducted for aving up to seven parallel rectifier units based on te minimum acievable THD i and different power factors. Te obtained results are illustrated in Fig. 10. As it can be seen wit seven parallel units by only applying pase-sift current control te total input current THD i can be reduced below 5% (i.e., THD ig = λ = 0.91) wile te power factor is 0.91 < λ < As an example te waveforms of te rectifier unit input currents and te total input current for five parallel units, wen te THD i is 6% are depicted in Fig. 11. In order to igligt te performance of te system wit pase-sifted current modulation tecnique te optimization as been considered to obtain te minimum THD i at different power factors for up to five parallel connected rectifier units (see Fig. 12). As it can be seen, te THD i of te total input current can be reduced down to 2.8% wen five rectifier units are utilized, wile according to Fig. 13 wit te same number of te units, wen only pase-sifted current control is applied, te minimum acievable THD i is 6%. Tis clearly differentiates te better performance of te system wen te pulse pattern modulation strategy is used. Fig. 13 sows te rectifier units input currents and te total input current waveforms for te case of aving a THD i of 2.8%. Finally, te armonic distribution of bot cases is illustrated in Fig. 14 sowing te better performance of te proposed current modulation tecnique. IV. CONCLUSIONS In tis paper a new topology based on a multi-rectifier system is proposed for armonic reduction. Te proposed electronic pase-sifting tecnique (transformer-less) results in more compact and cost-effective multi-rectifier systems, wic can be extended from low to ig power for applications suc as ASDs. Moreover, te active dc-link current control along wit te current modulation furter improves te total input current quality. Controlling te dclink currents and saring tem among different number of drives leads to a novel advantage of aving a common dc-bus voltage. Tis feature makes te rectifier units to draw equal amount of current from te grid, independent of te load profile, wic maximizes te armonic reduction capability of te system. Te simulations and analysis verified te performance of te system wic sowed tat applying te proposed multi-rectifier system wit electronic pase-sifting (transformer-less) can significantly improve te input current quality compares wit te traditional transformer-based rectifier systems. REFERENCES [1] J.W. Gray and F. J. Haydock, "Industrial power quality considerations wen installing adjustable speed drive systems," IEEE Trans. Ind. Appl., vol. 32, no. 3, pp , May/Jun [2] D. Kumar and F. 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