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2 A Sub-, 0 ppm/ C, Nanopower oltage Reference Generator Giuseppe De ita, Giuseppe annaccone Dipartimento di ngegneria dell nformazione: Elettronica, nformatica, elecomunicazioni Università di Pisa, ia Caruso 6, -56 Pisa, taly {giuseppe.devita, g.iannaccone}@iet.unipi.it Abstract An extreme low power voltage reference generator operating with a supply voltage ranging from 0.9 to has been implemented in AMS 0.5 µm CMOS process. he maximum supply current measured at the maximum supply voltage and at 80 C is 70 na. A temperature coefficient of 0 ppm/ C is achieved by means of a perfect suppression of the temperature dependence of the mobility, the compensation of the channel length modulation effect on the temperature coefficient and the absence of the body effect. he power supply rejection ratios without any filtering capacitor at 00 Hz and 0 MHz are lower than -5 and - db, respectively. he occupied chip area is 0.05 mm.. NRODUCON Low voltage and extreme low power are essential design requirements for circuits and systems to be deployed in a pervasive electronics scenario, where battery replacement can be very costly or where other scarce energy scavenging techniques are used. his leads to a strong demand for circuit building blocks operating with low supply voltage and sub microwatt power. Among them, voltage reference generators are used in almost all analog and digital systems to generate a DC voltage independent of the supply voltage and of temperature variations and they are preferentially implemented with a standard CMOS process for compatibility with the rest of the system. A common way to generate a reference voltage is to use a bandgap voltage reference, which can be implemented in any standard CMOS technology by exploiting the parasitic vertical BJs [, ]. Bandgap voltage references typically provide a voltage around.5 and then require an even larger supply voltage. Such problem can be solved by resistive subdivision methods [] that allow us to scale down the reference voltage allowing sub- operation. Other voltage references are based on the availability of transistors with two different threshold voltages in the same CMOS technology. Such feature can be obtained by using a selective channel implant [, ], by using different materials for the gate stack [5], by doping differently the polysilicon gates [6]. Such solutions can not be implemented in a standard CMOS technology because they require additional fabrication steps. Other types of voltage references, implemented with a standard CMOS technology, are based on a weighted difference between the gate-source voltages of two MOS transistors [7-9] but they can not usually operate in the sub- regime. n this paper we present a CMOS voltage reference, which exploits the MOS characteristics in the saturation and in the subthreshold regions, able to operate with a supply voltage smaller than and with a power consumption smaller than 00 nw.. CRCU DESCRPON he proposed voltage reference generator is shown in Fig.. A circuit formed by transistors numbered from M to M 8 generates a current 0 as independent as possible of the supply voltage. Such current is then injected into the diode-connected NMOS transistor M 0. he temperature dependence of 0 is compensated by the temperature dependence of the gate-source voltage of M 0 generating a temperature compensated reference voltage. he core of the current generator circuit is represented by transistors M -M, which determine the value of the current 0, whereas transistors M 5 and M 6 impose equal current in M and M and transistors M 7 and M 8 impose equal current 0 in M and M. ransistors M and M (indicated in Fig. with a symbol with a thicker line for the gate) are 5-NMOS transistors with a threshold voltage of 0.7 ; all the other transistors are.-mos transistors with a threshold voltage of 0.5 and for NMOS and PMOS, respectively. he two different threshold voltages allow us to bias M and M in the subthreshold region and, at the same time, to bias M and M in the saturation region. Such behavior is achieved by setting the gate-source voltages of M, M and M, M to a value between 0.5 and 0.7. he - characteristics of an NMOS transistor that operates in the saturation and in the subthreshold region can be approximated by () and (), respectively: C W L ox D GS th, () --00-/06/$ EEE. 07

3 D Fig. : Proposed oltage Reference Circuit. W GS th exp exp, () L m where µ is the electron mobility in the channel, is the thermal voltage, th is the threshold voltage, m is the subthreshold swing parameter, is the channel length modulation coefficient, W and L are the channel width and length, respectively. n the following, the integer subscript i will be added to quantities referred to transistor M i. he gatesource voltages of M and M (M and M ) are identical and can be extracted from () and () by considering M and M in subthreshold with drain current and M and M in saturation with a drain current 0. hen, by enforcing GS GS and GS GS, we have 0 th m th W, () CoxW 0 th m th, () CoxW where we have neglected channel length modulation (=0) and have set the term between square brackets in () to unity. Obviously, since the source terminals of all NMOS transistors are grounded, the body effect plays no role and th th and th th. By subtracting () from (), we can extract the expression of the current 0 : CoxW 0 N W where we define N W / W L. m /, (5) Such current is then injected into the diode connected transistor M 0, in order to generate a temperature compensated reference voltage. M 0 operates in the saturation region and then by using () and (5), we can derive the output voltage m W th 0. (6) N W0 0 W he proposed configuration of the voltage reference generator allows us to generate the current 0 without using any resistance, that are conversely used in similar types of circuits [, 8]. his is particularly important in the case of an ultra-low-power voltage reference generator because a very large resistance would be necessary to generate the small required current 0 (some tens of na). As a consequence, the proposed circuit topology allows us to drastically reduce the area occupation on the chip, as will be shown later from comparison with the literature Since transistors M, M, M 5, M 8 and M 0 are diodeconnected, almost all the variation of the supply voltage drops on the drain-source voltages of transistors M 6, M 7, M 9 of the current mirrors, and on the drain-source voltages of transistors M, M. As a consequence, in order to drastically reduce the channel length modulation effect, the channel length of all the transistors in the current mirrors and of M must be quite large and the drain-source voltage of M, which operates in the subthreshold region, must be much larger than so that the dependence of the current in () becomes negligible. he minimum power consumption of the proposed voltage reference generator and then the minimum acceptable value of the bias current 0 is imposed by M, M and M 0, which must operate in the saturation region. By assuming that W L W, if M operates in the saturation region L with GS th then M, which has the same drain current, will work in the saturation region as well. n such condition, the minimum current 0 can be evaluated by imposing that M operates in the saturation region with GS th. he minimum currents 0MN and MN have thus the following expressions, 0MN CoxW m W th th W m, (7) MN exp. (8) As clear from (7) and (8), in order to achieve a small power consumption, we have to choose small k and k. n order to ensure the operation of M 0 in the saturation region when 0 = 0MN, k 0 must be smaller than k. Since the reference voltage generator has two stable states, corresponding to the current given by (5) and to zero current, a start-up circuit (formed by M S -M S ) is used to ensure that the former stable state is achieved.. SUPPLY OLAGE DYNAMC RANGE he minimum supply voltage is imposed by the current generator circuit. n particular, we have to ensure that M 5 operates in the saturation region with GS5 th5 ( th5 = ) and that M has a drain-source voltage of at least 00 m so that the dependence of the current in M 08

4 can be neglected. Consequently, the following expression has to be satisfied, GS5 MN. (9) hen the supply voltage must be larger then 0.9 in the AMS 0.5 µm CMOS process. Such voltage is also sufficient to ensure the operation of M and M 8 in the saturation region. he maximum supply voltage is imposed by the maximum drain-source voltage allowed for MOS transistors, as shown below, 9. (0) MAX Since in the AMS 0.5 µm CMOS process the maximum value for the drain-source voltage of a MOS transistor is., the maximum value of the supply voltage is about.. EMPERAURE COMPENSAON As a first approximation we can consider that the threshold voltage of an NMOS transistor decreases linearly with the temperature: ) ( ) K ( ), () th ( th 0 0 where K is a BSMv coefficient and in our technology it is 0. m/ C. By differentiating (6) with respect to the temperature and taking into account (), one obtains m k B W K, () N q W0 0 W where k B is the Boltzmann constant and q is the electron charge. As clear from (), the temperature coefficient is independent of the temperature dependence of the carrier mobility. ndeed, in virtue of the topology used, a perfect suppression of the temperature dependence of the mobility is achieved; this leads to a smaller temperature coefficient compared to cases in which the temperature dependence of the mobility is compensated only at the reference temperature [8], degrading the temperature coefficient when moving away from the reference temperature. By setting () to zero, we obtain the condition W K N. () W0 0 k B m q W herefore, if () is satisfied, we obtain that the temperature coefficient () is zero for any temperature. t is clear that this is true within the approximation done in () and the simplified transistor characteristics () and ().. CHANNEL LENGH MODULAON EFFEC n order to take into account the channel length modulation effect on the temperature coefficient, we have to consider that 0 for a MOS in the saturation region. For the transistors in the subthreshold region, instead, if the drainsource voltage is larger than, we can neglect. Since M is diode-connected, we have only considered the channel Fig. : Die Photograph (core). length modulation effect on M. By assuming that the channel length of M is sufficiently large to ensure <<, and by following the same procedure used to calculate (), the temperature coefficient is, to first order in and when () holds: K W K 0 0 tp () th8 0 th0 N W8 8 K where K tp is the temperature coefficient for the threshold voltage of a PMOS and 0 is the reference voltage for =0. We can choose to dimension M 8 so that for a supply voltage in the middle of the supply voltage range ( =.5 ), expression () becomes zero, obtaining, W0 K 0 tp th8. (5) W K th0 From () it is evident that, for. 5 (. 5 ), the temperature coefficient is negative (positive), as shown later.. EXPERMENAL RESULS he proposed voltage reference has been implemented with AMS 0.5 m CMOS process. he die photograph is shown in Fig.. Measurements show that the proposed voltage reference generates a mean reference voltage of about 670 m with a variation of 5.67 m at room temperature, when the supply voltage varies from 0.9 to, as shown in Fig. a. he power supply rejection ratio, without any filtering capacitor, is -7 db at 00 Hz and -0 db at 0 MHz, for the smallest supply voltage. At larger supply voltage the power supply rejection ratio decreases to -5 db at 00 Hz and to - db at 0 MHz, as shown in Fig. b. Fig. shows the output voltage dependence on temperature for different values of the supply voltage. he measured temperature coefficient at = and = is 0 ppm/ C and ppm/ C, respectively, and increases to 8 and 0 ppm/ C at = and = 0.9, respectively, corresponding to the maximum and minimum supply voltage. At 80 C the current drawn at the maximum supply voltage is 70 na and at the minimum supply voltage is 50nA. At room temperature, instead, the current drawn at the maximum supply voltage is 55 na and at the minimum 09

5 Output oltage (m) a) Supply oltage () PSRR (db) b) Frequency (Hz) Fig. : Experiments: a) Output oltage vs. Supply voltage at room temperature, b) PSRR at room temperature and for a supply voltage of. Output oltage (m) = = = = emperature ( C) Fig. : Measured output voltage vs. temperature for values of the supply voltage. supply voltage is 0 na. he occupied chip area is 0.05 mm. A comparison with best performing published voltage reference circuits fabricated with a standard CMOS process is shown in able. t can be noted that the proposed voltage reference has the smallest temperature coefficient, the minimum supply voltage and by large the smallest power consumption, in the tens of nw range. he PSRR and the line sensitivity are comparable to other solutions already presented in the literature.. CONCLUSON A low-voltage, extreme low-power voltage reference generator implemented in AMS 0.5 m CMOS has been presented. he design conditions to minimize the power consumption and the temperature coefficient are described in detail. he complete suppression of the temperature dependence of mobility in a wide temperature range, the compensation of the channel length modulation effect on the temperature coefficient, and the elimination of the body effect have allowed us to obtain a very small temperature ABLE : COMPARSON WH OLAGE ERENCE GENERAORS AALABLE N HE LERAURE his work Leung et al. Leung et al. De ita et al. [8] [] [9] echnology 0.5 m 0.6 m 0.6 m 0.5 m CMOS CMOS CMOS CMOS Supply oltage 0.9 to. to 0.98 to.5.5 to. () Supply Current 0.0@0.9 <9.7 <8 0.08@.5 (A) 0.055@ 0.@. ref 670 m 09.m 60 m 89. m C (ppm/ C) Line Sensitivity 0.7 %/ 0.08 %/ 0.7 %/ 0.6 %/ PSRR =0.9 =. =0.98 Hz -7 db -7 db - db -59 MHz -0 db -0 db -7 db -5 db Die area (mm ) coefficient of 0 ppm/ C. he minimum supply voltage of only 0.9 and the maximum quiescent current of only 70 na leads to a total absorbed power in the decananowatt range, that makes the circuit very attractive for nanopower applications. ACKNOWLEDGMEN his work has been supported by Fondazione Cassa di Risparmio di Pisa. he authors wish to thank Prof. P. Bruschi for support in the characterization. ERENCES [] B.S. Song, P.R. Gray, A precision curvature-compensated CMOS bandgap reference, EEE Journal of Solid State Circuits, vol. DC- 8, pp. 6-6, December 98. [] K.N. Leung, P.K.. Mok, A sub- 5 ppm/ C CMOS Bandgap oltage Reference without requiring Low hreshold oltage Device, EEE Journal of Solid State Circuits, vol. 7, pp , April 00. [] R.A. Blauschild, P.A. ucci, R.S. Muller, R.G. Meyer, A new NMOS emperature Stable oltage Reference, EEE Journal of Solid State Circuits, vol. SC-, pp , December 978. [] H. anaka, Y. Nakagome, J. Etoh, E. Yamasaki, M. Aoki, K. Miyazawa, Sub- µa Dynamic Reference oltage Generator for battery-operated DRAMs, EEE Journal of Solid State Circuits, vol. 9, pp. 8-5, April 99. [5] M.C. obey, D.J. Gialiani, P.B. Askin, Flat-Band oltage Reference, U.S. Patent , August 976. [6] H.J. Oguey, B. Gerber, MOS oltage Reference based on polysilicon gate work function difference, EEE Journal of Solid State Circuit, vol. SC-5, pp. 6-69, June 980. [7] K.N. Leung, P.K.. Mok, K.C. Kwok, CMOS oltage Reference, US Patent 6 680, August 00. [8] K.N. Leung, P.K.. Mok, A CMOS oltage Reference Based on Weighted GS for CMOS Low-Dropout Linear Regulators, EEE Journal of Solid State Circuits, vol. 8, pp. 6-50, January 00. [9] G. De ita, G. annaccone, P. Andreani, A 00 nw, ppm/ C oltage Reference in a Digital 0.5 µm CMOS Process, Proc. of LS Symp., Honolulu, USA, June