Quad, 12-Bit DAC Voltage Output with Readback DAC8412/DAC8413

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1 Data Sheet Quad, -Bit DAC Voltage Output with Readback DAC84/DAC843 FEATURES FUNCTIONAL BLOCK DIAGRAM +5 V to ±5 V operation Unipolar or bipolar operation True voltage output Double-buffered inputs Reset to minimum (DAC843) or center scale (DAC84) Fast bus access time Readback DATA I/O DGND A A R/W V LOGIC V DD V REFH I/O PORT CONTROL LOGIC INPUT REG A INPUT REG B INPUT REG C OUTPUT REG A OUTPUT REG B OUTPUT REG C DAC A DAC B DAC C V OUTA V OUTB V OUTC APPLICATIONS Automatic test equipment Digitally controlled calibration Servo controls Process control equipment CS RESET LDAC INPUT REG D Figure. OUTPUT REG D DAC D V REFL V SS V OUTD 74- GENERAL DESCRIPTION The DAC84/DAC843 are quad, -bit voltage output DACs with readback capability. Built using a complementary BiCMOS process, these monolithic DACs offer the user very high package density. Output voltage swing is set by the two reference inputs VREFH and VREFL. By setting the VREFL input to V and VREFH to a positive voltage, the DAC provides a unipolar positive output range. A similar configuration with VREFH at V and VREFL at a negative voltage provides a unipolar negative output range. Bipolar outputs are configured by connecting both VREFH and VREFL to nonzero voltages. This method of setting output voltage range has advantages over other bipolar offsetting methods because it is not dependent on internal and external resistors with different temperature coefficients. Digital controls allow the user to load or read back data from any DAC, load any DAC, and transfer data to all DACs at one time. An active low RESET loads all DAC output registers to midscale for the DAC84 and zero scale for the DAC843. The DAC84/DAC843 are available in 8-lead plastic DIP, 8-lead ceramic DIP, 8-lead PLCC, and 8-lead LCC packages. They can be operated from a wide variety of supply and reference voltages with supplies ranging from single +5 V to ±5 V, and references from +.5 V to ± V. Power dissipation is less than 33 mw with ±5 V supplies and only 6 mw with a +5 V supply. For MIL-STD-883 applications, contact your local Analog Devices, Inc. sales office for the DAC84/DAC843/883 data sheet, which specifies operation over the 55 C to +5 C temperature range. All 883 parts are also available on Standard Military Drawings MXA through 7644M3A. LINEARITY ERROR (LSB) C V REFH = +V V REFL = V T A = 55 C, +5 C, +5 C +5 C 55 C DIGITAL INPUT CODE (Decimal) Figure. INL vs. Code Over Temperature 74- Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 DAC84/DAC843 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... arevision History... Specifications... 3 Electrical Characteristics... 3 Absolute Maximum Ratings... 7 Thermal Resistance... 7 ESD Caution... 7 Pin Configuration and Function Descriptions... 8 Typical Performance Characteristics... 9 Theory of Operation... 4 Data Sheet Introduction... 4 DACs... 4 Glitch... 4 Reference Inputs... 4 Digital I/O... 4 Coding... 4 Supplies... 5 Amplifiers... 5 Reference Configurations... 6 Single +5 V Supply Operation... 7 Outline Dimensions... 8 Ordering Guide... REVISION HISTORY 4/3 Rev. F to Rev. G Changed Reference Low Input Current from ma (min), ma (typ),.75 ma (max) to.75 ma (min), ma (typ), ma (max); Table... 3 Changes to Reference Configurations Section /9 Rev. E to Rev. F Updated Figure Numbering... Universal Removed Figure Changes to Ordering Guide... 6/7 Rev. D to Rev. E Updated Format... Universal Added CERDIP Package... Universal Changes to Specifications Section... 3 Changes to Absolute Maximum Ratings Section... 7 Updated Outline Dimensions... 8 Changes to Ordering Guide... 3/ Rev. C to Rev. D Rev. G Page of

3 Data Sheet DAC84/DAC843 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD = +5. V, VSS = 5. V, VLOGIC = +5. V, VREFH = +. V, VREFL =. V, 4 C TA +85 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit ACCURACY Integral Nonlinearity Error INL E grade ±.5 ±.5 LSB F grade ± LSB Differential Nonlinearity Error DNL Monotonic over temperature LSB Min-Scale Error VZSE RL = kω ± LSB Full-Scale Error VFSE RL = kω ± LSB Min-Scale Temperature Coefficient TCVZSE RL = kω 5 ppm/ C Full-Scale Temperature Coefficient TCVFSE RL = kω ppm/ C Linearity Matching Adjacent DAC Matching ± LSB REFERENCE Positive Reference Input Voltage Range VREFL +.5 VDD.5 V Negative Reference Input Voltage Range VREFH.5 V Reference High Input Current IREFH ma Reference Low Input Current IREFL.75 ma Large Signal Bandwidth BW 3 db, VREFH = V to V p-p 6 khz AMPLIFIER CHARACTERISTICS Output Current IOUT RL = kω, CL = pf 5 +5 ma Settling Time ts To.%, V step, RL = kω μs Slew Rate SR % to 9%. V/μs Analog Crosstalk 7 db LOGIC CHARACTERISTICS Logic Input High Voltage VINH TA = 5 C.4 V Logic Input Low Voltage VINL TA = 5 C.8 V Logic Output High Voltage VOH IOH =.4 ma.4 V Logic Output Low Voltage VOL IOL =.6 ma.4 V Logic Input Current IIN μa Input Capacitance CIN 8 pf Digital Feedthrough 3 VREFH =.5 V, VREFL = V 5 nv-sec LOGIC TIMING CHARACTERISTICS 3, 4 Chip Select Write Pulse Width twcs 8 ns Write Setup tws twcs = 8 ns ns Write Hold twh twcs = 8 ns ns Address Setup tas ns Address Hold tah ns Load Setup tls 7 ns Load Hold tlh 3 ns Write Data Setup twds twcs = 8 ns ns Write Data Hold twdh twcs = 8 ns ns Load Data Pulse Width tldw 7 ns Reset Pulse Width treset 4 ns Chip Select Read Pulse Width trcs 3 ns Read Data Hold trdh trcs = 3 ns ns Read Data Setup trds trcs = 3 ns ns Data to High-Z tdz CL = pf ns Chip Select to Data tcsd CL = pf 6 ns Rev. G Page 3 of

4 DAC84/DAC843 Data Sheet Parameter Symbol Conditions Min Typ Max Unit SUPPLY CHARACTERISTICS Power Supply Sensitivity PSS 4.5 V VDD 5.75 V 5 ppm/v Positive Supply Current IDD VREFH =.5 V 8.5 ma Negative Supply Current ISS 6.5 ma Power Dissipation PDISS 33 mw All supplies can be varied ±5%, and operation is guaranteed. Device is tested with nominal supplies. Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 3 All parameters are guaranteed by design. 4 All input control signals are specified with tr = tf = 5 ns (% to 9% of 5 V) and timed from a voltage level of.6 V. VDD = VLOGIC = +5. V ± 5%, VSS =. V, VREFH = +.5 V, VREFL =. V, VSS = 5. V ± 5%, VREFL =.5 V, 4 C TA +85 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Units ACCURACY Integral Nonlinearity Error INL E grade ±.5 ± LSB F grade ± LSB VSS =. V, E grade ± LSB VSS =. V, F grade ±4 LSB Differential Nonlinearity Error DNL Monotonic over temperature LSB Min-Scale Error VZSE VSS = 5. V ±4 LSB Full-Scale Error VFSE VSS = 5. V ±4 LSB Min-Scale Error VZSE VSS =. V ±8 LSB Full-Scale Error VFSE VSS =. V ±8 LSB Min-Scale Temperature Coefficient TCVZSE ppm/ C Full-Scale Temperature Coefficient TCVFSE ppm/ C Linearity Matching Adjacent DAC matching ± LSB REFERENCE Positive Reference Input Voltage Range 3 VREFL +.5 VDD.5 V Negative Reference Input Voltage Range VSS =. V VREFH.5 V VSS = 5. V.5 VREFH.5 V Reference High Input Current IREFH Code x. +. ma Large Signal Bandwidth BW 3 db, VREFH = V to.5 V p-p 45 khz AMPLIFIER CHARACTERISTICS Output Current IOUT RL = kω, CL = pf ma Settling Time ts To.%,.5 V step, RL = kω 7 μs Slew Rate SR % to 9%. V/μs LOGIC CHARACTERISTICS Logic Input High Voltage VINH TA = 5 C.4 V Logic Input Low Voltage VINL TA = 5 C.8 V Logic Output High Voltage VOH IOH =.4 ma.4 V Logic Output Low Voltage VOL IOL =.6 ma.45 V Logic Input Current IIN μa Input Capacitance CIN 8 pf LOGIC TIMING CHARACTERISTICS 4, 5 Chip Select Write Pulse Width twcs 5 ns Write Setup tws twcs = 5 ns ns Write Hold twh twcs = 5 ns ns Address Setup tas ns Address Hold tah ns Load Setup tls 7 ns Load Hold tlh 5 ns Rev. G Page 4 of

5 Data Sheet DAC84/DAC843 Parameter Symbol Conditions Min Typ Max Units Write Data Setup twds twcs = 5 ns ns Write Data Hold twdh twcs = 5 ns ns Load Data Pulse Width tldw 8 ns Reset Pulse Width treset 5 ns Chip Select Read Pulse Width trcs 7 ns Read Data Hold trdh trcs = 7 ns ns Read Data Setup trds trcs = 7 ns ns Data to High-Z tdz CL = pf ns Chip Select to Data tcsd CL = pf 3 ns SUPPLY CHARACTERISTICS Power Supply Sensitivity PSS ppm/v Positive Supply Current IDD 7 ma Negative Supply Current ISS VSS = 5. V ma Power Dissipation PDISS VSS = V 6 mw VSS = 5. V mw All supplies can be varied ±5%, and operation is guaranteed. Device is tested with VDD = 4.75 V. For single-supply operation only (VREFL =. V, VSS =. V). Due to internal offset errors, INL and DNL are measured beginning at x5. 3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 4 All parameters are guaranteed by design. 5 All input control signals are specified with tr = tf = 5 ns (% to 9% of 5 V) and timed from a voltage level of.6 V. CS t WCS t WS t WH R/W t AS t AH CS t RDS A/A R/W t RCS t RDH LDAC t LS t LH t LDW t AS t AH A/A DATA IN t WDS t WDH DATA OUT HIGH-Z t CSD DATA VALID t DZ HIGH-Z 74-3 RESET t RESET 74-4 Figure 3. Data Output (Read Timing) Figure 4. Data Write (Input and Output Registers) Timing Rev. G Page 5 of

6 DAC84/DAC843 Data Sheet 8ns 8ns CS CS t WS t WH t WS t WH R/W R/W t AS t AS ADDRESS ADDRESS ONE ADDRESS TWO ADDRESS THREE ADDRESS FOUR ADDRESS ADDRESS ONE ADDRESS TWO ADDRESS THREE ADDRESS FOUR t LS t LH t LS t LH LDAC LDAC DATA IN t WDS DATA VALID DATA VALID DATA3 VALID Figure 5. Single-Buffer Mode DATA4 VALID t WDH 74-5 DATA IN t WDS DATA VALID DATA VALID DATA3 VALID Figure 6. Double-Buffer Mode DATA4 VALID t LDW twdh 74-6 Rev. G Page 6 of

7 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = +5 C, unless otherwise noted. Table 3. Parameter Rating VSS to VDD.3 V, +33. V VSS to VLOGIC.3 V, +33. V VLOGIC to DGND.3 V, +7. V VSS to VREFL.3 V, +VSS. V VREFH to VDD +. V, +33. V VREFH to VREFL +. V, VSS VDD Current into Any VSS pin ±5 ma Digital Input Voltage to DGND.3 V, VLOGIC +.3 V Digital Output Voltage to DGND.3 V, +7. V Operating Temperature Range EP, FP, FPC 4 C to +85 C AT, BT, BTC 55 C to +5 C Junction Temperature 5 C Storage Temperature Range 65 C to +5 C Power Dissipation Package mw Lead Temperature JEDEC Industry Standard Soldering J-STD- THERMAL RESISTANCE DAC84/DAC843 θja is specified for the worst-case mounting conditions, that is, a device in socket. Table 4. Thermal Resistance Package Type θja θjc Unit 8-Lead Plastic DIP (PDIP) 48 C/W 8-Terminal Ceramic Leadless Chip Carrier (LLC) 7 8 C/W 8-Lead Plastic Leaded Chip Carrier (PLLC) 63 5 C/W 8-Lead Ceramic Dual In-Line Package (CERDIP) 5 9 C/W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. G Page 7 of

8 DAC84/DAC843 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V REFH V OUTB V OUTA 3 V SS 4 DGND 5 8 V REFL 7 V OUTC 6 V OUTD 5 V DD 4 V LOGIC 3 CS DAC84/ RESET 6 DAC843 LDAC 7 TOP VIEW A DB (LSB) 8 (Not to Scale) A DB 9 R/W DB 9 DB (MSB) DB3 8 DB DB4 DB5 3 DB6 4 7 DB9 6 DB8 5 DB DGND 5 RESET 6 LDAC 7 DB (LSB) 8 DB 9 DB DB3 V SS V OUTA V OUTB V REFH V REFL V OUTC V OUTD 4 3 PIN INDENTFIER DAC84/ DAC843 TOP VIEW (Not to Scale) DB4 DB5 DB6 DB7 DB8 DB9 DB 5 V DD 4 V LOGIC 3 CS A A R/W 9 DB (MSB) 74-9 DGND 5 RESET 6 LDAC 7 DB (LSB) 8 DB 9 DB DB3 V SS V OUTA V OUTB V REFH V REFL V OUTC V OUTD DAC84/ DAC843 TOP VIEW (Not to Scale) DB4 DB5 DB6 DB7 DB8 DB9 DB Figure 7. PDIP/CERDIP Figure 8. PLCC Figure 9. LCC 5 V DD 4 V LOGIC 3 CS A A R/W 9 DB (MSB) 74- Table 5. Pin Function Descriptions Pin Number Mnemonic Description VREFH High-Side DAC Reference Input. VOUTB DAC B Output. 3 VOUTA DAC A Output. 4 VSS Lower Rail Power Supply. 5 DGND Digital Ground. 6 RESET Reset Input and Output Registers to all s, Enabled at Active Low. 7 LDAC Load Data to DAC, Enabled at Active Low. 8 DB Data Bit, LSB. 9 DB Data Bit. DB Data Bit. DB3 Data Bit 3. DB4 Data Bit 4. 3 DB5 Data Bit 5. 4 DB6 Data Bit 6. 5 DB7 Data Bit 7. 6 DB8 Data Bit 8. 7 DB9 Data Bit 9. 8 DB Data Bit. 9 DB Data Bit, MSB. R/W Active Low to Write Data to DAC. Active high to readback previous data at data bit pins with VLOGIC connected to 5 V. A Address Bit. A Address Bit. 3 CS Chip Select, Enabled at Active Low. 4 VLOGIC Voltage Supply for Readback Function. Can be open circuit if not used. 5 VDD Upper Rail Power Supply. 6 VOUTD DAC D Output. 7 VOUTC DAC C Output. 8 VREFL Low-Side DAC Reference Input. Rev. G Page 8 of

9 Data Sheet DAC84/DAC843 TYPICAL PERFORMANCE CHARACTERISTICS MAXIMUM LINEARITY ERROR (LSB) V REFL = V T A = 5 C MAXIMUM LINEARITY ERROR (LSB) V DD = 5V V SS = V V REFL = V T A = 5 C V REFH (V) 74- V REFH (V) Figure. DNL vs. VREFH Figure 3. DNL vs. VREFH MAXIMUM LINEARITY ERROR (LSB) V DD = 5V V SS = V V REFL = V T A = 5 C MAXIMUM LINEARITY ERROR (LSB).3.. V REFL = V T A = 5 C V REFH (V) V REFH (V) 74-3 Figure. INL vs. VREFH Figure 4. INL vs.vrefh FULL-SCALE ERROR (LSB) V REFH = +V V REFL = V T = HOURS OF OPERATION AT 5 C X+3σ X X 3σ Figure. Full-Scale Error vs. Time Accelerated by Burn-in 74-5 ZERO-SCALE ERROR (LSB) X+3σ X X 3σ V REFH = +V V REFL = V T = HOURS OF OPERATION AT 5 C Figure 5. Zero-Scale Error vs. Time Accelerated by Burn-In 74-6 Rev. G Page 9 of

10 DAC84/DAC843 Data Sheet FULL-SCALE ERROR (LSB)...4 DAC A DAC D V REFH = +V V REFL = V DAC B DAC C LINEARITY ERROR (LSB) V DD = 5V V SS = V V REFH =.5V T A = 5 C TEMPERATURE ( C) Figure 6. Full-Scale Error vs. Temperature DIGITAL INPUT CODE (Decimal) Figure 9. Channel-to-Channel Matching (VSUPPLY = +5 V/GND) 74- ZERO-SCALE ERROR (LSB)...4 DAC A DAC D DAC B V REFH = +V V REFL = V DAC C I DD (ma) 3 7 V REFL = V TEMPERATURE ( C) V REFH (V) 74- Figure 7. Zero-Scale Error vs. Temperature Figure. IDD vs. VREFH (All DACs High) V REFH = V V REFL = V T A = 5 C.375 LINEARITY ERROR (LSB) LINEARITY ERROR (LSB) V REFH = +V V REFL = V T A = 55 C, +5 C, +5 C DIGITAL INPUT CODE (Decimal) DIGITAL INPUT CODE (Decimal) 74- Figure 8. Channel-to-Channel Matching (VSUPPLY = ±5 V) Figure. INL vs. Code Rev. G Page of

11 Data Sheet DAC84/DAC843 V V V/DIV EA TRIG'D V REFH = +V V REFL = V T A = 5 C V/DIV EA TRIG'D V REFH = +V V REFL = V T A = 5 C V 58ns µs/div Figure. Positive Slew Rate 9.4µs 74-6 V 58ns µs/div Figure 5. Negative Slew Rate 9.4µs mV INPUT 5V V REFH = +V V REFL = V T A = 5 C..5 V REFH = +V V REFL = V T A = 5 C mv/div 5V/DIV TRIG'D I VREFH (ma) mV.96µs µs/div Figure 3. Settling Time (Negative) 8.4µs DIGITAL INPUT CODE (Decimal) Figure 6. IVREFH vs. Code mV 5V INPUT..8.6 V REFH = +V V REFL = V T A = 5 C 5mV/DIV 5V/DIV LSB ERROR BAND INL (LSB).4 TRIG'D 7.5mV.96µs µs/div Figure 4. Settling Time (Positive) V REFH = +V V REFL = V T A = 5 C 8.4µs LOAD RESISTANCE (kω) Figure 7. INL vs. Load Resistance 74-8 Rev. G Page of

12 DAC84/DAC843 Data Sheet FULL-SCALE VOLTAGE (V) V REFH = +V V REFL = V T A = 5 C.. LOAD RESISTANCE (kω) Figure 8. Output Swing vs. Load Resistance 74-9 POWER SUPPLY REJECTION RATIO (db) PSRR: ±Vp PSRR: ±V V REFH = +V ALL DATA +PSRR PSRR k k k FREQUENCY (Hz) Figure 3. PSRR vs. Frequency M 74-3 GAIN (db) V REFH = ±mv V REFL = V DATA BITS = +5V mv p-p k k k FREQUENCY (Hz) Figure 9. Small Signal Response M M 74-3 NOISE DENSITY (µv).. NOISE FREQUENCY (Hz) V REFH = +V V REFL = V T A = 5 C. k k Figure 3. Noise Density vs. Noise Frequency POWER SUPPLY CURRENT (ma) 6 6 I DD I SS I OUT (ma) V REFH = +V V REFL = V T A = 5 C DATA = x I SC +I SC TEMPERATURE ( C) V OUT (V) Figure 3. Power Supply Current vs. Temperature Figure 33. IOUT vs. VOUT Rev. G Page of

Data Sheet DAC84/DAC843 µs CH MEAN 66.9µV V 4µs GLITCH AT DAC OUTPUT V REFH = +V V REFL = V T A = 5 C µv/div M µs A CH.9mV Figure 34. Broadband Noise 74-35 DEGLITCHER OUTPUT V CH.

13 Data Sheet DAC84/DAC843 µs CH MEAN 66.9µV V 4µs GLITCH AT DAC OUTPUT V REFH = +V V REFL = V T A = 5 C µv/div M µs A CH.9mV Figure 34. Broadband Noise DEGLITCHER OUTPUT V CH.86V Figure 36. Glitch and Deglitched Results I OUT (ma) V SS = V V REFH = +V V REFL = V T A = 5 C DATA = x8 +I SC 5 I SC V OUT (V) Figure 35. IOUT vs. VOUT Rev. G Page 3 of

14 DAC84/DAC843 THEORY OF OPERATION INTRODUCTION The DAC84/DAC843 are quad, voltage output, -bit parallel input DACs featuring a -bit data bus with readback capability. The only differences between the DAC84/DAC843 are the reset functions. The DAC84 resets to midscale (Code x8), and the DAC843 resets to minimum scale (Code x). The ability to operate from a single 5 V supply is a unique feature of these DACs. Operation of the DAC84/DAC843 can be viewed by dividing the system into three separate functional groups: the digital I/O and logic, the digital-to-analog converters, and the output amplifiers. DACS Each DAC is a voltage switched, high impedance (R = 5 kω), R-R ladder configuration. Each R resistor is driven by a pair of switches that connect the resistor to either VREFH or VREFL. GLITCH Worst-case glitch occurs at the transition between Half-Scale Digital Code to half-scale minus LSB,. It can be measured at about V μs (see Figure 36). For demanding applications such as waveform generation or precision instrumentation control, a deglitcher circuit can be implemented with a standard sample-and-hold circuit (see Figure 37). When CS is enabled by synchronizing the hold period to be longer than the glitch tradition, the output voltage can be smoothed with minimum disturbance. A quad sample-and-hold amplifier, SMP4, has been used to illustrate the deglitching result (see Figure 36). DACOUT CS S/H DACOUT S/H DACOUT DACOUT H S H S Figure 37. Data Output (Read Timing) Data Sheet REFERENCE INPUTS All four DACs share common reference high (VREFH) and reference low (VREFL) inputs. The voltages applied to these reference inputs set the output high and low voltage limits of all four of the DACs. Each reference input has voltage restrictions with respect to the other reference and to the power supplies. The VREFL can be set at any voltage between VSS and VREFH.5 V, and VREFH can be set to any value between +VDD.5 V and VREFL +.5 V. Note that because of these restrictions, the DAC84 references cannot be inverted (that is, VREFL cannot be greater than VREFH). It is important to note that the DAC84 VREFH input both sinks and sources current. In addition, the input current of both VREFH and VREFL are code-dependent. Many references have limited current-sinking capability and must be buffered with an amplifier to drive VREFH. The VREFL has no such special requirements. It is recommended that the reference inputs be bypassed with. μf capacitors when operating with ± V references. This limits the reference bandwidth. DIGITAL I/O See Table 6 for the digital control logic truth table. Digital I/O consists of a -bit bidirectional data bus, two registers select inputs, A and A, a R/W input, a RESET input, a chip select (CS), and a load DAC (LDAC) input. Control of the DACs and bus direction is determined by these inputs as shown in Table 6. Digital data bits are labeled with the MSB defined as Data Bit and the LSB as Data Bit. All digital pins are TTL/CMOS compatible. See Figure 38 for a simplified I/O logic diagram. The register select inputs A and A select individual DAC registers A (Binary Code ) through D (Binary Code ). Decoding of the registers is enabled by the CS input. When CS is high, no decoding takes place, and neither the writing nor the reading of the input registers is enabled. The loading of the second bank of registers is controlled by the asynchronous LDAC input. By taking LDAC low while CS is enabled, all output registers can be updated simultaneously. Note that the tldw required pulse width for updating all DACs is a minimum of 7 ns. The R/W input, when enabled by CS, controls the writing to and reading from the input register. CODING Both DAC84/DAC843 use binary coding. The output voltage can be calculated by ( VREFH VREFL) N VOUT VREFL 496 where N is the digital code in decimal. Rev. G Page 4 of

15 Data Sheet RESET The RESET function can be used either at power-up or at any time during DAC operation. The RESET function is independent of CS. This pin is active low and sets the DAC output registers to either center code for the DAC84, or zero code for the DAC843. The reset-to-center code is most useful when the DAC is configured for bipolar references and an output of V after reset is desired. SUPPLIES Supplies required are VSS, VDD, and VLOGIC. The VSS supply can be set between 5 V and V. VDD is the positive supply; its operating range is between 5 V and 5 V. DAC84/DAC843 VLOGIC is the digital output supply voltage for the readback function. It is normally connected to +5 V. This pin is a logic reference input only. It does not supply current to the device. If the readback function is not being used, VLOGIC can be left opencircuit. While VLOGIC does not supply current to the DAC84, it does supply currents to the digital outputs when readback is used. AMPLIFIERS Unlike many voltage output DACs, the DAC84 features buffered voltage outputs. Each output is capable of both sourcing and sinking 5 ma at ± V, eliminating the need for external amplifiers when driving 5 pf or smaller capacitive load in most applications. These amplifiers are short-circuit protected. Table 6. DAC84/DAC843 Logic Table A A R/W CS RS LDAC Input Register Output Register Mode DAC L L L L H L Write Write Transparent A L H L L H L Write Write Transparent B H L L L H L Write Write Transparent C H H L L H L Write Write Transparent D L L L L H H Write Hold Write input A L H L L H H Write Hold Write input B H L L L H H Write Hold Write input C H H L L H H Write Hold Write input D L L H L H H Read Hold Read input A L H H L H H Read Hold Read input B H L H L H H Read Hold Read input C H H H L H H Read Hold Read input D X X X H H L Hold Update all output registers All X X X H H H Hold Hold Hold All X X X X L X All registers reset to midscale/zero-scale All X X X H X All registers latched to midscale/zero-scale All DAC84 resets to midscale, and DAC843 resets to zero scale. L = logic low; H = logic high; X = don t care. Input and output registers are transparent when asserted. Rev. G Page 5 of

16 DAC84/DAC843 Data Sheet V REFH V DD V SS CS RDDACA WRDACA WRDB WRDB WRDB DAC A V OUTA A A R/W DB..DB V LOGIC WRDB3 RDDACB WRDB4 DAC B WRDACB WRDB5 INPUT OUTPUT REGISTER WRDB6 REGISTER RDDACC WRDB7 DAC C WRDB8 WRDACC WRDB9 RDDACD WRDB DAC D WRDB WRDACD V OUTB V OUTC V OUTD V REFL LDAC RESET READOUTBAR READBACKDATAIN_DB READBACKDATAIN_DB READBACK DATAOUT_DB READOUT DGND Figure 38. Simplified I/O Logic Diagram Careful attention to grounding is important for accurate operation of the DAC84. This is not because the DAC84 is more sensitive than other -bit DACs, but because with four outputs and two references, there is greater potential for ground loops. Because the DAC84 has no analog ground, the ground must be specified with respect to the reference. REFERENCE CONFIGURATIONS Output voltage ranges can be configured as either unipolar or bipolar, and within these choices, a wide variety of options exists. The unipolar configuration can be either positive or negative voltage output, and the bipolar configuration can be either symmetrical or nonsymmetrical. INPUT +5V REF + OUTPUT TRIM kω V REFH OP4.µF V REFL +V OPERATION +5V V DD DAC84 OR DAC843 V SS 5V Figure 39. Unipolar + V Operation.µF //µf 74-4 GAIN kω BALANCE kω +5V 39kΩ AD688 FOR ±V AD588 FOR ±5V µf 6.Ω.µF 6.Ω.µF +5V V DD V REFH DAC84 OR DAC843 V REFL V SS 5V ±5 OR ±V OPERATION Figure 4. Symmetrical Bipolar Operation.µF //µf Figure 4 (symmetrical bipolar operation) shows the DAC84 configured for ± V operation. See the AD688 data sheet for a full explanation of reference operation. Adjustments may not be required for many applications since the AD688 is a very high accuracy reference. However, if additional adjustments are required, adjust the DAC84 full scale first. Begin by loading the digital full-scale code (xfff), and then adjust the gain adjust potentiometer to attain a DAC output voltage of V. Then, adjust the balance adjust to set the center-scale output voltage to. V Rev. G Page 6 of

17 Data Sheet DAC84/DAC843 The. μf bypass capacitors shown at the reference inputs in Figure 4 should be used whenever ± V references are used. Applications with single references or references to ±5 V may not require the. μf bypassing. The 6. Ω resistor in series with the output of the reference amplifier keeps the amplifier from oscillating with the capacitive load. This 6. Ω resistor has been found to be large enough to stabilize this circuit. Larger resistor values are acceptable, provided that the drop across the resistor does not exceed VBE. Assuming a minimum VBE of.6 V and a maximum current of.75 ma, then the resistor should be under Ω for the loading of a single DAC84. Using two separate references is not recommended. Having two references can cause different drifts with time and temperature; whereas with a single reference, most drifts track. Unipolar positive full-scale operation can usually be set with a reference with the correct output voltage. This is preferable to using a reference and dividing down to the required value. For a V full-scale output, the circuit can be configured as shown in Figure 4. In this configuration, the full-scale value is set first by adjusting the kω resistor for a full-scale output of V. GND kω TRIM VOLTAGE REFERENCE.µF OUTPUT.µF V REFH V REFL V DD DAC84 OR DAC843 V SS.µF //µf Figure 4 shows the DAC84 configured for V to V operation. A V full-scale output voltage reference is connected directly to VREFL for the reference voltage. SINGLE +5 V SUPPLY OPERATION For operation with a 5 V supply, the reference voltage should be set between. V and.5 V for optimum linearity. Figure 4 shows a REF43 used to supply a.5 V reference voltage. The headroom of the reference and DAC are both sufficient to support a 5 V supply with ±5% tolerance. VDD and VLOGIC should be connected to the same supply. Separate bypassing to each pin should also be used. 5V REF43 INPUT OUTPUT GND µf.µf TRIM kω V REFH.µF V REFL V DD DAC84 OR DAC843 V SS ZERO TO.5V OPERATION SINGLE 5V SUPPLY Figure V Single-Supply Operation.µF //µf µf ZERO TO V OPERATION 5V Figure 4. Unipolar V Operation 74-4 Rev. G Page 7 of

18 DAC84/DAC843 Data Sheet OUTLINE DIMENSIONS.458 (.63).44 (.3) SQ. (.54).64 (.63).458 (.63) MAX SQ.88 (.4).54 (.37).75 (.9) REF.5 (.7).75 (.9) REF.55 (.4).45 (.4) BOTTON VIEW (7.6) REF 5. (.5) MIN.8 (.7). (.56).5 (3.8) REF.95 (.4).75 (.9) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure Terminal Ceramic Leadless Chip Carrier [LCC] (E-8-) Dimensions shown in inches and (millimeters) 6-A.565 (39.75).38 (35.5) (4.73).485 (.3) 4.5 (6.35) MAX. (5.8).5 (.9). (.56).4 (.36). (.54) BSC.5 (.38) GAUGE.5 PLANE (.38) MIN SEATING PLANE.5 (.3) MIN.65 (5.88).6 (5.4).7 (7.78) MAX.95 (4.95).5 (3.7).5 (.38).8 (.).7 (.78).5 (.7) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS. Figure Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-8-) Dimensions shown in inches and (millimeters) 76-A Rev. G Page 8 of

19 Data Sheet DAC84/DAC (.).4 (.7).48 (.).4 (.7) 4 5 PIN IDENTIFIER TOP VIEW (PINS DOWN) (.58) SQ.45 (.43).495 (.57).485 (.3) SQ.56 (.4).4 (.7).5 (.7) BSC. (3.4).9 (.9).8 (4.57).65 (4.9). (.5) MIN. (.53).3 (.33).3 (.8).6 (.66).45 (.4).5 (.64) R.43 (.9).39 (9.9) BOTTOM VIEW (PINS UP) COMPLIANT TO JEDEC STANDARDS MO-47-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Plastic Leaded Chip Carrier [PLCC] (P-8) Dimensions shown in inches and (millimeters) 458-A.5 (.3) MIN. (.54) MAX (5.49).5 (.7) PIN.5(5.7) MAX. (5.8).5 (3.8).6 (.66).4 (.36) 4.49 (37.85) MAX. (.54) BSC.7 (.78).3 (.76).5 (.38) MIN.5 (3.8) MIN SEATING PLANE 5.6 (5.75).59 (4.99).8 (.46).8 (.) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Ceramic Dual In-Line Package [CERDIP] (Q-8-) Dimensions shown in inches and (millimeters) 36-A Rev. G Page 9 of

20 DAC84/DAC843 Data Sheet ORDERING GUIDE Model Notes Temperature Range INL Package Description Package Option DAC84AT/883C 55 C to +5 C ±.75 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8- DAC84BT/883C 55 C to +5 C ±.5 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8- DAC84BTC/883C 55 C to +5 C ±.5 8-Terminal Ceramic Leadless Chip Carrier [LCC] E-8- DAC84EP 4 C to +85 C ±.5 8-Lead Plastic Dual In-Line Package [PDIP] N-8- DAC84EPZ 4 C to +85 C ±.5 8-Lead Plastic Dual In-Line Package [PDIP] N-8- DAC84FP 4 C to +85 C ± 8-Lead Plastic Dual In-Line Package [PDIP] N-8- DAC84FPC 4 C to +85 C ± 8-Lead Plastic Leaded Chip Carrier [PLCC] P-8 DAC84FPC-REEL 4 C to +85 C ± 8-Lead Plastic Leaded Chip Carrier [PLCC] P-8 DAC84FPCZ 4 C to +85 C ± 8-Lead Plastic Leaded Chip Carrier [PLCC] P-8 DAC84FPCZ-REEL 4 C to +85 C ± 8-Lead Plastic Leaded Chip Carrier [PLCC] P-8 DAC84FPZ 4 C to +85 C ± 8-Lead Plastic Dual In-Line Package [PDIP] N-8- DAC843AT/883C 55 C to +5 C ±.75 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8- DAC843BT/883C 55 C to +5 C ±.5 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8- DAC843BTC/883C 55 C to +5 C ±.5 8-Terminal Ceramic Leadless Chip Carrier [LCC] E-8- DAC843EP 4 C to +85 C ±.5 8-Lead Plastic Dual In-Line Package [PDIP] N-8- DAC843EPZ 4 C to +85 C ±.5 8-Lead Plastic Dual In-Line Package [PDIP] N-8- DAC843FP 4 C to +85 C ± 8-Lead Plastic Dual In-Line Package [PDIP] N-8- DAC843FPC 4 C to +85 C ± 8-Lead Plastic Leaded Chip Carrier [PLCC] P-8 DAC843FPC-REEL 4 C to +85 C ± 8-Lead Plastic Leaded Chip Carrier [PLCC] P-8 DAC843FPCZ 4 C to +85 C ± 8-Lead Plastic Leaded Chip Carrier [PLCC] P-8 DAC843FPC-REEL 4 C to +85 C ± 8-Lead Plastic Dual In-Line Package [PDIP] N-8- DAC843FPZ 4 C to +85 C ± 8-Lead Plastic Dual In-Line Package [PDIP] N-8- Z = RoHS Compliant Part. If burn-in is required, these models are available in CERDIP. Contact sales. 3 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D74--4/3(G) Rev. G Page of

Quad, 12-Bit, Parallel Input, Unipolar/Bipolar, Voltage Output DAC AD5725

Data Sheet Quad, 12-Bit, Parallel Input, Unipolar/Bipolar, Voltage Output DAC FEATURES FUNCTIONAL BLOCK DIAGRAM +5 V to ±15 V operation Unipolar or bipolar operation ±.5 LSB max INL error, ±1 LSB max DNL